Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6491	1			T11	6		T12	20		T17	8
testmodes[AdcCtrlTestmodeNormal]	5325	1			T10	2		T11	10		T13	1
testmodes[AdcCtrlTestmodeLowpower]	5559	1			T13	1		T14	1		T15	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3407	1			T11	2		T12	19		T17	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1726	1			T11	3		T17	4		T20	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1252	1			T41	22		T42	15		T43	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1697	1			T11	3		T17	4		T20	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1956	1			T10	1		T11	7		T17	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1343	1			T20	1		T22	1		T41	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1271	1			T41	17		T42	13		T43	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1324	1			T13	1		T14	1		T20	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2710	1			T16	9		T19	10		T22	3