Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21509

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3531

1

T17

40

T18

12

T20

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19352

1

T6

1

T27

2

T28

1

auto[1]

5688

1

T10

2

T13

22

T14

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39	1			T137	21		T206	1		T207	11
values[1]	592	1			T13	11		T17	13		T18	12
values[2]	579	1			T14	26		T22	5		T102	1
values[3]	659	1			T18	15		T22	2		T89	1
values[4]	643	1			T38	4		T92	5		T129	7
values[5]	515	1			T23	13		T91	5		T208	1
values[6]	895	1			T14	2		T63	1		T38	9
values[7]	671	1			T13	11		T17	43		T18	5
values[8]	778	1			T20	7		T97	1		T151	22
values[9]	3214	1			T10	2		T15	9		T21	2
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	760	1			T13	11		T17	13		T18	12
values[1]	654	1			T14	26		T18	15		T22	5
values[2]	737	1			T22	2		T89	1		T38	3
values[3]	491	1			T38	1		T92	5		T129	7
values[4]	703	1			T23	13		T38	9		T91	5
values[5]	734	1			T14	2		T17	16		T63	1
values[6]	2741	1			T10	2		T13	11		T15	9
values[7]	826	1			T18	5		T151	22		T93	1
values[8]	784	1			T62	1		T89	1		T101	23
values[9]	155	1			T103	10		T122	27		T209	10
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	7		T210	1		T95	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T17	1		T18	1		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	13		T18	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T22	3		T100	12		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T38	3		T120	11		T93	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T22	2		T89	1		T39	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T129	5		T94	1		T103	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	1		T92	1		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T23	13		T38	5		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T91	3		T120	11		T93	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	1		T17	1		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T102	1		T100	15		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T10	2		T13	7		T15	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	13		T20	6		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	1		T151	11		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T137	13		T130	13		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T62	1		T102	1		T91	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T89	1		T101	10		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T103	10		T212	3		T213	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T122	14		T209	1		T214	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	4		T210	8		T95	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T17	12		T18	11		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	13		T18	14		T210	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T22	2		T100	13		T114	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T120	10		T138	4		T155	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	9		T215	6		T137	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T129	2		T131	12		T216	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T92	4		T107	2		T217	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	4		T112	14		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T91	2		T120	12		T96	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T17	15		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T100	14		T218	5		T219	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T13	4		T220	19		T221	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	14		T20	1		T120	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T18	4		T151	11		T95	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T137	16		T222	15		T57	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T92	12		T223	4		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T101	13		T104	5		T95	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T212	1		T213	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T122	13		T209	9		T214	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T206	1		T225	1		T226	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T137	10		T207	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	7		T210	1		T96	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T17	1		T18	1		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	13		T102	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T22	3		T100	12		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T18	1		T120	11		T93	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	2		T89	1		T39	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T38	3		T129	5		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	1		T92	1		T215	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T23	13		T208	1		T59	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T91	3		T227	5		T228	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T14	1		T63	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T100	15		T120	11		T96	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	7		T17	1		T18	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T17	13		T102	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T97	1		T151	11		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	6		T137	13		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T10	2		T15	9		T21	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T89	1		T101	10		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T226	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T137	11		T207	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	4		T210	8		T96	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	12		T18	11		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	13		T210	18		T95	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T22	2		T100	13		T114	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T18	14		T120	10		T138	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	9		T137	15		T138	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T129	2		T155	1		T96	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T92	4		T215	6		T108	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T229	3		T216	8		T112	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T91	2		T107	2		T109	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	1		T38	4		T105	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T100	14		T120	12		T96	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	4		T17	15		T18	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	14		T120	11		T104	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T151	11		T95	13		T118	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T20	1		T137	16		T222	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T92	12		T220	19		T221	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T101	13		T104	5		T95	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	5		T210	9		T95	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T17	13		T18	12		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	14		T18	15		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T22	4		T100	14		T114	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T38	3		T120	11		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T22	2		T89	1		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T129	3		T94	1		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	1		T92	5		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T23	1		T38	7		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T91	3		T120	13		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	2		T17	16		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T102	1		T100	15		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T10	2		T13	5		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T17	15		T20	5		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T18	5		T151	12		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T137	17		T130	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T62	1		T102	1		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T89	1		T101	14		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T103	1		T212	3		T213	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T122	14		T209	10		T214	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T13	6		T95	6		T96	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T215	9		T137	9		T230	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	12		T53	3		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T22	1		T100	11		T122	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T120	10		T93	2		T138	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	7		T215	8		T98	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T129	4		T103	12		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T232	10		T217	5		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T23	12		T38	2		T234	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T91	2		T120	10		T93	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T98	14		T229	2		T112	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T100	14		T227	4		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T13	6		T15	8		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	12		T20	2		T120	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T151	10		T95	12		T118	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T137	12		T130	12		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T91	8		T103	13		T235	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T101	9		T95	11		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T103	9		T212	1		T213	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T122	13		T237	14		T238	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T206	1		T225	1		T226	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T137	12		T207	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	5		T210	9		T96	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T17	13		T18	12		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	14		T102	1		T210	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	4		T100	14		T114	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T18	15		T120	11		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T22	2		T89	1		T39	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T38	3		T129	3		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	1		T92	5		T215	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T23	1		T208	1		T59	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T91	3		T227	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	2		T63	1		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T100	15		T120	13		T96	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	5		T17	16		T18	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	15		T102	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T97	1		T151	12		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	5		T137	17		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T10	2		T15	1		T21	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T89	1		T101	14		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T226	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T137	9		T207	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	6		T96	10		T133	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T215	9		T230	4		T60	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	12		T95	6		T53	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T22	1		T100	11		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T120	10		T93	2		T138	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	7		T98	7		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T129	4		T103	12		T96	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T215	8		T93	12		T232	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T23	12		T229	2		T112	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T91	2		T227	4		T228	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	2		T98	14		T234	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T100	14		T120	10		T96	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	6		T130	5		T168	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	12		T120	1		T171	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T151	10		T95	12		T118	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	2		T137	12		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1093	1			T15	8		T91	8		T150	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T101	9		T130	12		T95	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21619

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3421

1

T17

43

T18

27

T20

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19409

1

T6

1

T27

2

T28

1

auto[1]

5631

1

T10

2

T13

11

T14

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T144	1		-	-		-	-
values[0]	55	1			T132	1		T228	12		T156	16
values[1]	747	1			T20	7		T210	9		T137	21
values[2]	3031	1			T10	2		T13	11		T15	9
values[3]	797	1			T17	16		T18	15		T102	1
values[4]	601	1			T18	5		T22	2		T62	1
values[5]	641	1			T17	13		T89	1		T38	3
values[6]	598	1			T13	11		T14	2		T63	1
values[7]	479	1			T14	26		T18	12		T89	1
values[8]	557	1			T62	1		T38	9		T92	5
values[9]	1078	1			T22	5		T23	13		T102	2
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1081	1			T13	11		T20	7		T38	1
values[1]	2904	1			T10	2		T15	9		T17	27
values[2]	798	1			T17	16		T18	20		T102	1
values[3]	702	1			T22	2		T62	1		T89	1
values[4]	502	1			T17	13		T92	13		T94	1
values[5]	671	1			T13	11		T14	2		T18	12
values[6]	477	1			T62	1		T38	9		T208	1
values[7]	441	1			T14	26		T23	13		T92	5
values[8]	875	1			T22	5		T102	2		T90	1
values[9]	105	1			T129	7		T215	15		T104	2
minimum	16484	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	7		T90	1		T98	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T20	6		T38	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T10	2		T15	9		T21	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T17	13		T101	10		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T18	1		T99	1		T239	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	1		T18	1		T102	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T62	1		T151	11		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	2		T89	1		T38	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T17	1		T103	10		T230	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T92	1		T94	1		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	7		T14	1		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T18	1		T89	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T62	1		T130	6		T96	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	5		T208	1		T93	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	13		T208	1		T93	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T23	13		T92	1		T120	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T102	1		T90	1		T97	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T22	3		T102	1		T91	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T129	5		T215	9		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T104	1		T59	2		T241	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16339	1			T11	16		T12	20		T16	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	4		T236	13		T242	25
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T20	1		T210	8		T137	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T220	19		T221	16		T138	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T17	14		T101	13		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T18	4		T224	12		T105	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T17	15		T18	14		T39	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T151	11		T118	24		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	13		T137	16		T122	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T17	12		T230	6		T133	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T92	12		T60	9		T218	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	4		T14	1		T104	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T18	11		T39	1		T137	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T96	14		T223	4		T209	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T38	4		T172	2		T243	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	13		T218	11		T244	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T92	4		T120	11		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T57	14		T218	16		T242	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T22	2		T91	2		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T129	2		T215	6		T126	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T104	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	1		T27	2		T28	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T144	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T228	12		T156	16		T245	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T132	1		T246	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T94	1		T236	5		T242	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	6		T210	1		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T10	2		T13	7		T15	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T17	13		T101	10		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T99	1		T239	2		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	1		T18	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T18	1		T62	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T22	2		T39	8		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	1		T151	11		T103	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T89	1		T38	3		T92	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	7		T14	1		T63	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	1		T208	1		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	13		T96	15		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T18	1		T89	1		T103	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T62	1		T208	1		T93	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T38	5		T92	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T102	1		T90	1		T97	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T22	3		T23	13		T102	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T247	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T246	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T236	13		T242	13		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	1		T210	8		T137	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T13	4		T220	19		T221	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T17	14		T101	13		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T138	4		T118	24		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T17	15		T18	14		T210	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T18	4		T236	11		T105	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	9		T100	14		T249	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T17	12		T151	11		T105	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T92	12		T100	13		T137	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	4		T14	1		T104	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	1		T137	15		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T14	13		T96	14		T209	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T18	11		T107	2		T126	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T223	4		T216	12		T128	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T38	4		T92	4		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T129	2		T215	6		T57	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T22	2		T91	2		T120	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1