Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21518

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3522

1

T13

11

T17

40

T18

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19361

1

T6

1

T27

2

T28

1

auto[1]

5679

1

T10

2

T13

22

T14

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	195	1			T89	1		T103	14		T309	1
values[0]	27	1			T137	21		T225	1		T226	5
values[1]	609	1			T13	11		T17	13		T18	12
values[2]	602	1			T14	26		T22	5		T102	1
values[3]	696	1			T18	15		T22	2		T89	1
values[4]	643	1			T38	4		T92	5		T129	7
values[5]	477	1			T23	13		T91	5		T208	1
values[6]	877	1			T14	2		T63	1		T38	9
values[7]	681	1			T13	11		T17	43		T62	1
values[8]	780	1			T18	5		T20	7		T97	1
values[9]	2998	1			T10	2		T15	9		T21	2
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	586	1			T13	11		T90	1		T215	20
values[1]	649	1			T18	15		T22	5		T102	1
values[2]	758	1			T14	26		T22	2		T89	1
values[3]	504	1			T38	1		T92	5		T129	7
values[4]	670	1			T23	13		T38	9		T91	5
values[5]	733	1			T14	2		T17	16		T63	1
values[6]	2733	1			T10	2		T13	11		T15	9
values[7]	859	1			T18	5		T151	22		T99	1
values[8]	827	1			T62	1		T89	1		T101	23
values[9]	86	1			T122	27		T212	4		T213	23
minimum	16635	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T210	1		T95	7		T133	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	7		T90	1		T215	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T18	1		T102	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T22	3		T98	8		T100	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T14	13		T38	3		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T22	2		T89	1		T39	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T129	5		T94	1		T103	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	1		T92	1		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T23	13		T38	5		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T91	3		T120	11		T93	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T17	1		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T102	1		T100	15		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T10	2		T13	7		T15	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	13		T20	6		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T18	1		T151	11		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T137	13		T130	13		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T62	1		T102	1		T91	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T89	1		T101	10		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T212	3		T213	11		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T122	14		T321	16		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16362	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T17	1		T18	1		T94	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T210	8		T95	8		T133	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	4		T215	9		T230	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	14		T210	18		T53	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T22	2		T100	13		T114	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	13		T120	10		T138	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T39	9		T215	6		T137	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T129	2		T131	12		T216	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T92	4		T107	2		T217	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T38	4		T218	16		T112	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T91	2		T120	12		T96	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T17	15		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T100	14		T218	5		T317	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T13	4		T220	19		T221	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T17	14		T20	1		T120	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T18	4		T151	11		T95	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T137	16		T222	15		T57	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T92	12		T223	4		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T101	13		T104	5		T95	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T212	1		T213	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T122	13		T321	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T17	12		T18	11		T131	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T103	14		T105	1		T235	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T89	1		T309	1		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T137	10		T225	1		T226	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T210	1		T96	11		T206	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	7		T17	1		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	13		T102	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T22	3		T100	12		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T18	1		T120	11		T93	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	2		T89	1		T39	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T38	3		T129	5		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	1		T92	1		T215	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T23	13		T208	1		T59	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T91	3		T93	13		T227	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	1		T63	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T100	15		T120	11		T96	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	7		T17	1		T62	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T17	13		T102	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	1		T97	1		T151	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T20	6		T137	13		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1433	1			T10	2		T15	9		T21	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T101	10		T208	1		T130	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T105	13		T108	3		T212	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T209	9		T124	11		T285	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T137	11		T226	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T210	8		T96	10		T133	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	4		T17	12		T18	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	13		T210	18		T95	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T22	2		T100	13		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T18	14		T120	10		T138	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T39	9		T137	15		T138	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T129	2		T155	1		T259	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T92	4		T215	6		T217	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T216	8		T109	15		T112	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T91	2		T107	2		T109	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	1		T38	4		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T100	14		T120	12		T96	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	4		T17	15		T168	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	14		T120	11		T104	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T18	4		T151	11		T95	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T20	1		T137	16		T222	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T92	12		T220	19		T221	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T101	13		T104	5		T95	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T210	9		T95	9		T133	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	5		T90	1		T215	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T18	15		T102	1		T210	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	4		T98	1		T100	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	14		T38	3		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T22	2		T89	1		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T129	3		T94	1		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	1		T92	5		T107	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T23	1		T38	7		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T91	3		T120	13		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	2		T17	16		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T102	1		T100	15		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T10	2		T13	5		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	15		T20	5		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T18	5		T151	12		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T137	17		T130	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T62	1		T102	1		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T89	1		T101	14		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T212	3		T213	13		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T122	14		T321	17		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16528	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T17	13		T18	12		T94	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T95	6		T133	1		T174	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	6		T215	9		T230	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T53	3		T231	7		T174	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T22	1		T98	7		T100	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	12		T120	10		T93	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	7		T215	8		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T129	4		T103	12		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T232	10		T217	5		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T23	12		T38	2		T234	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T91	2		T120	10		T93	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T229	2		T282	8		T112	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T100	14		T125	12		T252	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T13	6		T15	8		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T17	12		T20	2		T120	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T151	10		T95	12		T118	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T137	12		T130	12		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T91	8		T103	22		T242	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T101	9		T95	11		T266	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T212	1		T213	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T122	13		T321	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T137	9		T96	10		T322	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T131	2		T197	7		T315	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T103	1		T105	14		T235	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T89	1		T309	1		T209	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T137	12		T225	1		T226	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T210	9		T96	11		T206	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	5		T17	13		T18	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	14		T102	1		T210	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T22	4		T100	14		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T18	15		T120	11		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T22	2		T89	1		T39	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T38	3		T129	3		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T38	1		T92	5		T215	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T23	1		T208	1		T59	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T91	3		T93	1		T227	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T14	2		T63	1		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T100	15		T120	13		T96	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	5		T17	16		T62	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	15		T102	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T18	5		T97	1		T151	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T20	5		T137	17		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T10	2		T15	1		T21	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T101	14		T208	1		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T103	13		T235	10		T173	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T323	9		T285	13		T176	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T137	9		T226	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T96	10		T133	1		T174	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	6		T215	9		T230	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	12		T95	6		T53	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T22	1		T100	11		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T120	10		T93	2		T138	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	7		T98	7		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T129	4		T103	12		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T215	8		T232	10		T217	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T23	12		T112	5		T324	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T91	2		T93	12		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	2		T98	14		T234	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T100	14		T120	10		T96	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	6		T130	5		T168	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	12		T120	1		T171	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T151	10		T95	12		T118	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	2		T137	12		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T15	8		T91	8		T150	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T101	9		T130	12		T95	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8