Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21917

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3123

1

T13

11

T14

26

T17

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18924

1

T6

1

T27

2

T28

1

auto[1]

6116

1

T10

2

T14

26

T15

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T158	3		T213	7		-	-
values[0]	113	1			T95	24		T128	26		T325	3
values[1]	617	1			T18	17		T102	1		T38	3
values[2]	655	1			T89	1		T101	23		T91	5
values[3]	744	1			T20	7		T62	1		T39	2
values[4]	644	1			T13	11		T17	27		T38	10
values[5]	703	1			T22	5		T23	13		T102	1
values[6]	561	1			T14	26		T17	13		T90	1
values[7]	561	1			T63	1		T102	1		T215	1
values[8]	2664	1			T10	2		T14	2		T15	9
values[9]	1313	1			T13	11		T18	15		T22	2
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	875	1			T18	17		T102	1		T38	3
values[1]	646	1			T89	1		T101	23		T91	5
values[2]	750	1			T13	11		T62	1		T38	1
values[3]	787	1			T17	27		T20	7		T22	5
values[4]	557	1			T14	26		T17	13		T102	1
values[5]	514	1			T23	13		T102	1		T215	1
values[6]	2667	1			T10	2		T15	9		T21	2
values[7]	638	1			T13	11		T14	2		T17	16
values[8]	843	1			T62	1		T129	7		T120	34
values[9]	269	1			T18	15		T22	2		T97	1
minimum	16494	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T239	2		T94	1		T118	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T18	2		T102	1		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T101	10		T91	3		T98	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T89	1		T39	8		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	7		T62	1		T92	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T38	1		T208	1		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T22	3		T38	5		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T17	13		T20	6		T171	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T17	1		T208	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	13		T102	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T102	1		T215	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T23	13		T234	15		T289	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T10	2		T15	9		T21	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T138	17		T53	4		T59	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	1		T17	1		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	7		T89	1		T215	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T62	1		T129	5		T120	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T120	11		T94	1		T96	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T18	1		T97	1		T130	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T22	2		T151	11		T95	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16332	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T326	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T118	24		T122	8		T133	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T18	15		T92	4		T95	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T101	13		T91	2		T261	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T39	9		T137	15		T218	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	4		T92	12		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T120	12		T172	9		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	2		T38	4		T104	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	14		T20	1		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T17	12		T96	10		T133	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	13		T230	6		T218	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T210	8		T122	13		T105	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T219	3		T257	18		T299	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T220	19		T221	16		T100	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T138	4		T53	4		T218	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	1		T17	15		T95	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T13	4		T215	15		T104	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T129	2		T120	11		T137	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T120	10		T96	12		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T18	14		T327	6		T274	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T151	11		T95	13		T96	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	1		T27	2		T28	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T213	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T158	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T328	6		T329	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T95	12		T128	15		T325	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T100	12		T94	1		T118	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T18	2		T102	1		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T101	10		T91	3		T92	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T89	1		T97	1		T39	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T62	1		T39	1		T98	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T20	6		T120	11		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	7		T38	5		T222	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	13		T38	1		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	3		T208	1		T122	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T23	13		T102	1		T103	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T17	1		T210	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	13		T90	1		T234	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T63	1		T102	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T53	4		T235	3		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T10	2		T14	1		T15	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T89	1		T215	9		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T18	1		T62	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T13	7		T22	2		T151	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T213	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T158	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T329	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T95	12		T128	11		T330	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T100	13		T118	24		T122	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T18	15		T92	4		T57	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T101	13		T91	2		T92	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T39	9		T137	15		T155	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T39	1		T210	18		T114	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T20	1		T120	12		T253	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	4		T38	4		T222	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T17	14		T137	11		T230	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T22	2		T122	13		T96	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T60	9		T259	2		T218	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T17	12		T210	8		T317	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	13		T257	18		T331	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T100	14		T105	13		T242	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T53	4		T219	3		T192	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T14	1		T17	15		T220	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T215	6		T120	10		T138	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T18	14		T129	2		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T13	4		T151	11		T215	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T239	2		T94	1		T118	31
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T18	17		T102	1		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T101	14		T91	3		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T89	1		T39	10		T137	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	5		T62	1		T92	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T38	1		T208	1		T120	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T22	4		T38	7		T104	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	15		T20	5		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	13		T208	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	14		T102	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T102	1		T215	1		T210	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T23	1		T234	1		T289	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T10	2		T15	1		T21	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T138	5		T53	5		T59	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	2		T17	16		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	5		T89	1		T215	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T62	1		T129	3		T120	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T120	11		T94	1		T96	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T18	15		T97	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T22	2		T151	12		T95	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16482	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T326	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T118	8		T122	2		T133	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T95	11		T57	10		T234	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T101	9		T91	2		T98	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T39	7		T137	10		T156	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	6		T222	12		T123	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T120	10		T172	10		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T22	1		T38	2		T168	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T17	12		T20	2		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T103	12		T96	10		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T14	12		T103	13		T230	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T122	13		T227	4		T111	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T23	12		T234	14		T235	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T15	8		T150	10		T270	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T138	16		T53	3		T192	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T91	8		T95	6		T53	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T13	6		T215	17		T98	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T129	4		T120	1		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T120	10		T96	9		T106	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T130	12		T274	1		T332	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T151	10		T95	12		T96	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T100	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T213	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T158	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T328	1		T329	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T95	13		T128	12		T325	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T100	14		T94	1		T118	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T18	17		T102	1		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T101	14		T91	3		T92	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T89	1		T97	1		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T62	1		T39	2		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T20	5		T120	13		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	5		T38	7		T222	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T17	15		T38	1		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T22	4		T208	1		T122	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T23	1		T102	1		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T17	13		T210	9		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	14		T90	1		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T63	1		T102	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T53	5		T235	1		T219	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T10	2		T14	2		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T89	1		T215	7		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T18	15		T62	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T13	5		T22	2		T151	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T213	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T328	5		T329	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T95	11		T128	14		T325	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T100	11		T118	8		T122	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T57	10		T234	2		T217	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T101	9		T91	2		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T39	7		T137	10		T252	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T98	7		T130	5		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	2		T120	10		T253	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	6		T38	2		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	12		T171	9		T137	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T22	1		T122	13		T96	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T23	12		T103	13		T60	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T103	12		T333	10		T111	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	12		T234	14		T232	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T100	14		T93	12		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T53	3		T235	2		T192	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T15	8		T91	8		T150	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T215	8		T120	10		T138	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T129	4		T120	1		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T13	6		T151	10		T215	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8