dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25040 1 T6 1 T27 2 T28 1



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 21677 1 T6 1 T27 2 T28 1
auto[ADC_CTRL_FILTER_COND_OUT] 3363 1 T14 28 T17 29 T18 5



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19219 1 T6 1 T27 2 T28 1
auto[1] 5821 1 T10 2 T13 22 T14 26



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20908 1 T10 2 T11 16 T12 20
auto[1] 4132 1 T6 1 T27 2 T28 1



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 258 1 T22 2 T101 23 T92 5
values[0] 39 1 T255 12 T308 1 T301 26
values[1] 817 1 T17 27 T22 5 T89 1
values[2] 571 1 T18 12 T102 1 T97 1
values[3] 645 1 T13 11 T38 3 T97 1
values[4] 651 1 T20 7 T102 2 T38 9
values[5] 2560 1 T10 2 T15 9 T21 2
values[6] 723 1 T13 11 T18 5 T90 1
values[7] 696 1 T14 28 T17 13 T23 13
values[8] 748 1 T18 15 T89 1 T38 1
values[9] 877 1 T17 16 T62 1 T39 2
minimum 16455 1 T6 1 T27 2 T28 1



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 619 1 T17 27 T22 5 T102 1
values[1] 698 1 T18 12 T38 3 T97 1
values[2] 489 1 T13 11 T97 1 T215 1
values[3] 2770 1 T10 2 T15 9 T20 7
values[4] 457 1 T62 1 T90 1 T39 17
values[5] 756 1 T13 11 T18 5 T99 1
values[6] 776 1 T14 28 T17 13 T23 13
values[7] 746 1 T17 16 T18 15 T38 1
values[8] 725 1 T22 2 T62 1 T101 23
values[9] 221 1 T100 25 T252 26 T110 3
minimum 16783 1 T6 1 T27 2 T28 1



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21507 1 T6 1 T27 2 T28 1
auto[1] 3533 1 T13 12 T14 12 T15 8



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 209 1 T17 13 T102 1 T309 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T22 3 T90 1 T215 9
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T18 1 T129 5 T236 5
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 252 1 T38 3 T97 1 T98 8
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T13 7 T210 1 T104 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T97 1 T215 1 T93 14
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1368 1 T10 2 T15 9 T21 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T20 6 T102 1 T92 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T39 8 T138 9 T96 15
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 104 1 T62 1 T90 1 T120 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T13 7 T95 12 T60 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T18 1 T99 1 T94 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T63 1 T89 1 T91 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T14 14 T17 1 T23 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T18 1 T138 17 T130 6
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T17 1 T38 1 T39 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 113 1 T22 2 T101 10 T215 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 247 1 T62 1 T92 1 T99 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 30 1 T252 13 T110 1 T237 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 78 1 T100 12 T233 14 T334 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16392 1 T11 16 T12 20 T16 10
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 89 1 T89 1 T208 1 T99 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 131 1 T17 14 T105 11 T107 7
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T22 2 T215 6 T218 16
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 105 1 T18 11 T129 2 T236 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 229 1 T120 12 T104 5 T224 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T13 4 T210 8 T155 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 93 1 T114 9 T105 6 T303 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1038 1 T38 4 T220 19 T221 16
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T20 1 T92 12 T151 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 103 1 T39 9 T138 4 T96 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 93 1 T120 11 T137 15 T95 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 211 1 T13 4 T95 12 T60 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T18 4 T95 13 T96 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T104 1 T222 15 T223 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T14 14 T17 12 T122 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 273 1 T18 14 T138 4 T218 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T17 15 T39 1 T137 11
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T101 13 T215 9 T56 5
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T92 4 T100 14 T120 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 28 1 T252 13 T110 2 T335 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 85 1 T100 13 T334 2 T299 4
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 227 1 T6 1 T27 2 T28 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 75 1 T118 24 T53 4 T231 9



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 33 1 T22 2 T101 10 T131 12
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 77 1 T92 1 T100 12 T120 11
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T308 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 24 1 T255 12 T301 12 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 259 1 T17 13 T91 3 T208 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T22 3 T89 1 T90 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 116 1 T18 1 T102 1 T129 5
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T97 1 T98 23 T120 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T13 7 T210 1 T104 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 243 1 T38 3 T97 1 T215 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T102 1 T38 5 T130 13
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T20 6 T102 1 T92 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1382 1 T10 2 T15 9 T21 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 75 1 T62 1 T151 11 T137 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T13 7 T95 12 T60 8
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 201 1 T18 1 T90 1 T120 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T63 1 T91 9 T103 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T14 14 T17 1 T23 13
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T18 1 T89 1 T138 17
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 160 1 T38 1 T137 10 T103 14
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T215 10 T208 1 T56 6
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 283 1 T17 1 T62 1 T39 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16318 1 T11 16 T12 20 T16 10
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 45 1 T101 13 T131 14 T219 3
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 103 1 T92 4 T100 13 T120 10
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T301 14 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 202 1 T17 14 T91 2 T218 5
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T22 2 T215 6 T118 24
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 108 1 T18 11 T129 2 T105 11
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T120 12 T224 12 T174 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T13 4 T210 8 T155 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T210 18 T114 9 T104 5
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T38 4 T96 12 T249 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T20 1 T92 12 T122 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1030 1 T39 9 T220 19 T221 16
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 73 1 T151 11 T137 15 T242 13
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T13 4 T95 12 T60 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T18 4 T120 11 T95 21
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 188 1 T104 1 T222 15 T236 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T14 14 T17 12 T122 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 262 1 T18 14 T138 4 T223 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T137 11 T236 11 T253 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T215 9 T56 5 T224 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 229 1 T17 15 T39 1 T100 14
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 137 1 T6 1 T27 2 T28 1



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T17 15 T102 1 T309 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T22 4 T90 1 T215 7
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T18 12 T129 3 T236 14
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 268 1 T38 3 T97 1 T98 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T13 5 T210 9 T104 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 133 1 T97 1 T215 1 T93 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1387 1 T10 2 T15 1 T21 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 235 1 T20 5 T102 1 T92 13
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T39 10 T138 5 T96 15
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 122 1 T62 1 T90 1 T120 12
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 260 1 T13 5 T95 13 T60 10
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T18 5 T99 1 T94 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 231 1 T63 1 T89 1 T91 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T14 16 T17 13 T23 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 318 1 T18 15 T138 5 T130 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T17 16 T38 1 T39 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 195 1 T22 2 T101 14 T215 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 263 1 T62 1 T92 5 T99 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 33 1 T252 14 T110 3 T237 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 95 1 T100 14 T233 1 T334 3
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16569 1 T6 1 T27 2 T28 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 101 1 T89 1 T208 1 T99 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T17 12 T227 4 T123 7
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 125 1 T22 1 T215 8 T98 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 85 1 T129 4 T236 4 T235 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 213 1 T98 7 T120 10 T125 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 96 1 T13 6 T96 9 T234 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T93 12 T103 9 T122 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1019 1 T15 8 T38 2 T150 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T20 2 T151 10 T122 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T39 7 T138 8 T96 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 75 1 T120 1 T137 10 T95 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T13 6 T95 11 T60 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T95 12 T96 10 T242 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T91 8 T103 12 T222 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T14 12 T23 12 T122 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T138 16 T130 5 T234 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 116 1 T137 9 T103 13 T172 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 77 1 T101 9 T215 9 T56 3
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T100 14 T120 10 T93 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 25 1 T252 12 T237 1 T335 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 68 1 T100 11 T233 13 T207 2
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 50 1 T91 2 T171 9 T282 8
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 63 1 T118 8 T53 3 T231 8



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 55 1 T22 2 T101 14 T131 16
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T92 5 T100 14 T120 11
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T308 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 16 1 T255 1 T301 15 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 258 1 T17 15 T91 3 T208 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T22 4 T89 1 T90 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T18 12 T102 1 T129 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T97 1 T98 2 T120 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T13 5 T210 9 T104 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 226 1 T38 3 T97 1 T215 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T102 1 T38 7 T130 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T20 5 T102 1 T92 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1364 1 T10 2 T15 1 T21 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 91 1 T62 1 T151 12 T137 16
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 215 1 T13 5 T95 13 T60 10
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T18 5 T90 1 T120 12
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 222 1 T63 1 T91 1 T103 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T14 16 T17 13 T23 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 309 1 T18 15 T89 1 T138 5
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T38 1 T137 12 T103 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 235 1 T215 10 T208 1 T56 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 293 1 T17 16 T62 1 T39 2
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16455 1 T6 1 T27 2 T28 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 23 1 T101 9 T131 10 T336 4
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 63 1 T100 11 T120 10 T228 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 22 1 T255 11 T301 11 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 203 1 T17 12 T91 2 T171 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T22 1 T215 8 T118 8
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 86 1 T129 4 T235 10 T174 11
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T98 21 T120 10 T125 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 93 1 T13 6 T236 4 T174 14
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T93 12 T103 9 T133 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 118 1 T38 2 T130 12 T96 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T20 2 T122 3 T134 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1048 1 T15 8 T150 10 T39 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 57 1 T151 10 T137 10 T242 13
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T13 6 T95 11 T60 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T120 1 T95 18 T96 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T91 8 T103 12 T222 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T14 12 T23 12 T122 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T138 16 T130 5 T108 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T137 9 T103 13 T236 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 130 1 T215 9 T56 3 T234 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T100 14 T93 2 T137 12



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 21507 1 T6 1 T27 2 T28 1
auto[1] auto[0] 3533 1 T13 12 T14 12 T15 8

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%