Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21546

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3494

1

T14

26

T17

13

T22

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19253

1

T6

1

T27

2

T28

1

auto[1]

5787

1

T10

2

T14

2

T15

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	154	1			T90	1		T91	9		T122	11
values[0]	17	1			T256	1		T273	7		T319	9
values[1]	941	1			T22	5		T62	1		T89	1
values[2]	678	1			T62	1		T120	23		T96	29
values[3]	576	1			T14	28		T17	16		T18	5
values[4]	764	1			T13	11		T22	2		T92	13
values[5]	2689	1			T10	2		T13	11		T15	9
values[6]	528	1			T102	2		T38	3		T208	1
values[7]	587	1			T17	13		T18	15		T20	7
values[8]	537	1			T39	19		T129	7		T239	2
values[9]	1114	1			T18	12		T92	5		T215	19
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	891	1			T62	1		T97	1		T98	23
values[1]	755	1			T14	28		T18	5		T62	1
values[2]	609	1			T17	16		T22	2		T101	23
values[3]	2632	1			T10	2		T13	11		T15	9
values[4]	692	1			T13	11		T17	27		T23	13
values[5]	625	1			T17	13		T102	1		T208	1
values[6]	475	1			T18	15		T20	7		T63	1
values[7]	576	1			T39	19		T129	7		T137	26
values[8]	981	1			T90	1		T91	9		T92	5
values[9]	149	1			T18	12		T168	30		T174	24
minimum	16655	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T62	1		T98	8		T137	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T97	1		T98	15		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T18	1		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	13		T210	1		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T17	1		T95	7		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T22	2		T101	10		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T10	2		T13	7		T15	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T92	1		T215	9		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	7		T17	13		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T23	13		T102	1		T38	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T171	10		T93	13		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T17	1		T102	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T18	1		T20	6		T100	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T63	1		T215	1		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T39	8		T129	5		T337	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	1		T137	11		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T90	1		T92	1		T120	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T91	9		T215	10		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T18	1		T168	15		T135	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T174	13		T207	15		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16374	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T89	1		T94	1		T206	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T137	11		T138	4		T224	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T122	13		T105	6		T216	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	1		T18	4		T172	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T14	13		T210	8		T120	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	15		T95	8		T218	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T101	13		T151	11		T53	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T13	4		T91	2		T220	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T92	12		T215	6		T137	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	4		T17	14		T104	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	4		T104	1		T223	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T209	9		T105	11		T317	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	12		T100	14		T120	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T18	14		T20	1		T100	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T53	8		T219	3		T254	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T39	9		T129	2		T124	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T39	1		T137	15		T118	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T92	4		T120	11		T138	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T215	9		T210	18		T261	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T18	11		T168	15		T338	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T174	11		T207	17		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T285	13		T339	2		T213	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T90	1		T122	3		T250	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T91	9		T231	9		T281	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T273	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T256	1		T319	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T22	3		T62	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T89	1		T97	1		T98	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T62	1		T224	1		T172	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T120	11		T96	15		T230	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	1		T17	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	13		T101	10		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	7		T95	19		T57	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T22	2		T92	1		T215	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T10	2		T13	7		T15	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T23	13		T38	5		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T93	13		T104	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T102	2		T38	3		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T18	1		T20	6		T100	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	1		T63	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T39	8		T129	5		T239	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	1		T137	11		T94	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T18	1		T92	1		T120	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T215	10		T210	1		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T122	8		T244	5		T322	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T231	9		T281	9		T340	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T319	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T22	2		T137	11		T138	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T122	13		T105	6		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T224	9		T172	9		T236	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T120	12		T96	14		T230	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	1		T17	15		T18	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	13		T101	13		T151	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	4		T95	20		T57	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T92	12		T215	6		T137	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T13	4		T17	14		T91	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T38	4		T104	1		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T104	5		T209	9		T105	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T120	10		T143	5		T128	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T18	14		T20	1		T100	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	12		T100	14		T96	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T39	9		T129	2		T124	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	1		T137	15		T155	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T18	11		T92	4		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T215	9		T210	18		T118	24
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T62	1		T98	1		T137	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T97	1		T98	1		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	2		T18	5		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	14		T210	9		T120	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T17	16		T95	9		T218	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	2		T101	14		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T10	2		T13	5		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T92	13		T215	7		T137	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	5		T17	15		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T23	1		T102	1		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T171	1		T93	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	13		T102	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T18	15		T20	5		T100	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T63	1		T215	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T39	10		T129	3		T337	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T39	2		T137	16		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T90	1		T92	5		T120	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T91	1		T215	10		T210	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T18	12		T168	16		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T174	12		T207	18		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16523	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T89	1		T94	1		T206	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T98	7		T137	9		T138	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T98	14		T103	9		T122	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T172	10		T236	4		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	12		T120	10		T96	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T95	6		T242	5		T174	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T101	9		T151	10		T53	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T13	6		T15	8		T91	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T215	8		T137	12		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	6		T17	12		T130	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T23	12		T38	2		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T171	9		T93	12		T228	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T100	14		T120	10		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T20	2		T100	11		T93	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T130	12		T53	9		T271	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T39	7		T129	4		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T137	10		T118	8		T96	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T120	1		T138	16		T103	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T91	8		T215	9		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T168	14		T135	15		T338	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T174	12		T207	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T22	1		T232	10		T332	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T285	11		T328	5		T292	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T90	1		T122	9		T250	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T91	1		T231	10		T281	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T273	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T256	1		T319	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T22	4		T62	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T89	1		T97	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T62	1		T224	10		T172	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T120	13		T96	15		T230	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	2		T17	16		T18	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	14		T101	14		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	5		T95	22		T57	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T22	2		T92	13		T215	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T10	2		T13	5		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T23	1		T38	7		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T93	1		T104	6		T209	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T102	2		T38	3		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T18	15		T20	5		T100	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	13		T63	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	10		T129	3		T239	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T39	2		T137	16		T94	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T18	12		T92	5		T120	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T215	10		T210	19		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T122	2		T250	2		T135	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T91	8		T231	8		T281	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T273	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T22	1		T98	7		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T98	14		T103	9		T122	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T172	10		T236	4		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T120	10		T96	14		T230	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T174	14		T268	3		T111	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	12		T101	9		T151	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	6		T95	17		T57	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T215	8		T137	12		T125	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T13	6		T15	8		T17	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T23	12		T38	2		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T93	12		T228	11		T277	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T120	10		T122	1		T128	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	2		T100	11		T171	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T100	14		T130	12		T96	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T39	7		T129	4		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T137	10		T96	9		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T120	1		T138	16		T103	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T215	9		T118	8		T234	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8