Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21645

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3395

1

T17

43

T18

27

T20

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19435

1

T6

1

T27

2

T28

1

auto[1]

5605

1

T10

2

T13

11

T14

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	294	1			T56	11		T240	1		T236	15
values[0]	89	1			T242	27		T228	12		T156	16
values[1]	732	1			T20	7		T210	9		T137	21
values[2]	2992	1			T10	2		T13	11		T15	9
values[3]	876	1			T17	16		T18	15		T102	1
values[4]	541	1			T18	5		T22	2		T62	1
values[5]	670	1			T17	13		T89	1		T38	3
values[6]	560	1			T13	11		T14	2		T63	1
values[7]	497	1			T18	12		T62	1		T89	1
values[8]	595	1			T14	26		T38	9		T208	2
values[9]	739	1			T22	5		T23	13		T102	2
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	822	1			T20	7		T38	1		T90	1
values[1]	2873	1			T10	2		T13	11		T15	9
values[2]	882	1			T17	16		T18	20		T102	1
values[3]	630	1			T22	2		T62	1		T89	1
values[4]	513	1			T17	13		T92	13		T39	2
values[5]	590	1			T13	11		T14	2		T18	12
values[6]	538	1			T62	1		T38	9		T208	1
values[7]	494	1			T14	26		T92	5		T208	2
values[8]	838	1			T22	5		T23	13		T102	2
values[9]	100	1			T129	7		T215	15		T59	2
minimum	16760	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T90	1		T98	15		T236	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T20	6		T38	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T10	2		T13	7		T15	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	13		T101	10		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T18	1		T99	1		T239	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	1		T18	1		T102	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T62	1		T151	11		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	2		T89	1		T38	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	1		T103	10		T234	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T92	1		T39	1		T94	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	7		T14	1		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T18	1		T89	1		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T62	1		T130	6		T96	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	5		T208	1		T93	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	13		T208	1		T93	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T92	1		T208	1		T120	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T102	1		T90	1		T97	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T22	3		T23	13		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T129	5		T215	9		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T59	2		T241	10		T341	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16424	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T114	1		T53	4		T271	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T236	13		T242	12		T248	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T20	1		T210	8		T137	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T13	4		T220	19		T221	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T17	14		T101	13		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T18	4		T138	4		T118	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	15		T18	14		T39	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T151	11		T105	24		T219	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	13		T137	16		T122	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T17	12		T133	4		T342	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T92	12		T39	1		T60	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	4		T14	1		T104	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T18	11		T137	15		T224	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T96	14		T223	4		T209	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T38	4		T172	2		T269	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	13		T218	27		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T92	4		T120	11		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	14		T242	7		T216	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T22	2		T91	2		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T129	2		T215	6		T126	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T114	9		T53	4		T158	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T240	1		T242	8		T231	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T56	6		T236	8		T343	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T242	14		T228	12		T156	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T176	3		T246	1		T344	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T94	1		T236	5		T123	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	6		T210	1		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T10	2		T13	7		T15	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T17	13		T101	10		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T91	9		T99	1		T239	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	1		T18	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	1		T62	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T22	2		T215	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	1		T151	11		T103	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T89	1		T38	3		T92	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	7		T14	1		T63	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	1		T137	11		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T62	1		T96	15		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T18	1		T89	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	13		T208	1		T93	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T38	5		T208	1		T120	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T102	1		T90	1		T97	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T22	3		T23	13		T102	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T242	7		T231	9		T126	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T56	5		T236	7		T343	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T242	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T246	7		T344	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T236	13		T248	11		T174	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T20	1		T210	8		T137	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T13	4		T220	19		T221	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T17	14		T101	13		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T138	4		T118	24		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T17	15		T18	14		T39	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T18	4		T236	11		T105	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T100	14		T259	2		T249	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T17	12		T151	11		T105	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T92	12		T100	13		T137	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	4		T14	1		T104	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	1		T137	15		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T96	14		T209	9		T105	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T18	11		T107	2		T126	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	13		T223	4		T216	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T38	4		T120	11		T172	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T129	2		T215	6		T57	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	2		T91	2		T92	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T90	1		T98	1		T236	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T20	5		T38	1		T210	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T10	2		T13	5		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T17	15		T101	14		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T18	5		T99	1		T239	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T17	16		T18	15		T102	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T62	1		T151	12		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T22	2		T89	1		T38	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	13		T103	1		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T92	13		T39	2		T94	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	5		T14	2		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T18	12		T89	1		T137	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T62	1		T130	1		T96	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T38	7		T208	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	14		T208	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T92	5		T208	1		T120	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T102	1		T90	1		T97	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T22	4		T23	1		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T129	3		T215	7		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T59	2		T241	1		T341	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16529	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T114	10		T53	5		T271	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T98	14		T236	4		T242	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T20	2		T137	9		T103	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T13	6		T15	8		T91	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	12		T101	9		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	8		T118	8		T122	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T39	7		T98	7		T100	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T151	10		T171	9		T156	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T100	11		T137	12		T122	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T103	9		T234	2		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T60	7		T125	11		T133	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	6		T230	4		T172	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T137	10		T173	7		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T130	5		T96	14		T128	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T38	2		T93	12		T103	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	12		T93	2		T157	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T120	1		T131	2		T266	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T57	10		T234	14		T242	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T22	1		T23	12		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T129	4		T215	8		T126	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T241	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T242	13		T228	11		T156	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T53	3		T271	11		T257	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T240	1		T242	8		T231	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T56	8		T236	8		T343	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T242	14		T228	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T176	1		T246	8		T344	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T94	1		T236	14		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T20	5		T210	9		T137	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T10	2		T13	5		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T17	15		T101	14		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T91	1		T99	1		T239	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T17	16		T18	15		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T18	5		T62	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T22	2		T215	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	13		T151	12		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T89	1		T38	3		T92	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	5		T14	2		T63	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	2		T137	16		T224	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T62	1		T96	15		T209	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T18	12		T89	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	14		T208	1		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T38	7		T208	1		T120	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T102	1		T90	1		T97	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T22	4		T23	1		T102	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T242	7		T231	8		T126	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T56	3		T236	7		T343	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T242	13		T228	11		T156	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T176	2		T344	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T236	4		T123	7		T174	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	2		T137	9		T95	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T13	6		T15	8		T150	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T17	12		T101	9		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T91	8		T138	8		T118	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	7		T98	7		T95	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T171	9		T236	10		T156	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T100	14		T252	5		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T151	10		T103	9		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T100	11		T137	12		T122	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	6		T230	4		T172	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T137	10		T253	10		T252	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T96	14		T254	12		T157	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T103	13		T123	9		T173	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	12		T93	2		T130	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T38	2		T120	1		T93	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T129	4		T215	8		T57	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	1		T23	12		T91	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8