Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19477

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

5563

1

T10

2

T13

11

T15

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19645

1

T6

1

T27

2

T28

1

auto[1]

5395

1

T10

2

T13

11

T15

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	247	1			T89	1		T99	1		T95	15
values[0]	77	1			T18	5		T104	6		T192	2
values[1]	811	1			T13	11		T14	26		T20	7
values[2]	653	1			T22	7		T62	1		T63	1
values[3]	602	1			T17	27		T91	5		T98	15
values[4]	810	1			T18	12		T23	13		T102	1
values[5]	569	1			T89	1		T90	1		T39	17
values[6]	601	1			T13	11		T18	15		T102	1
values[7]	811	1			T17	13		T62	1		T101	23
values[8]	509	1			T102	1		T38	3		T97	1
values[9]	2895	1			T10	2		T14	2		T15	9
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	762	1			T13	11		T14	26		T20	7
values[1]	2801	1			T10	2		T15	9		T21	2
values[2]	586	1			T17	27		T23	13		T102	1
values[3]	655	1			T18	12		T92	5		T151	22
values[4]	523	1			T89	1		T102	1		T90	1
values[5]	845	1			T13	11		T18	15		T215	19
values[6]	671	1			T17	13		T62	1		T101	23
values[7]	479	1			T14	2		T102	1		T38	3
values[8]	756	1			T17	16		T89	1		T38	9
values[9]	211	1			T224	10		T236	22		T126	27
minimum	16751	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	7		T14	13		T22	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T20	6		T215	9		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T22	3		T62	1		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1417	1			T10	2		T15	9		T21	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T102	1		T91	3		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	13		T23	13		T171	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T18	1		T151	11		T345	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T92	1		T137	13		T122	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T39	8		T56	6		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T89	1		T102	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T215	10		T98	8		T137	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	7		T18	1		T239	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T101	10		T38	1		T229	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	1		T62	1		T103	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	1		T102	1		T95	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T38	3		T97	1		T100	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T17	1		T38	5		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T89	1		T91	9		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T224	1		T310	13		T275	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T236	11		T126	13		T277	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16399	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T114	1		T104	1		T132	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	4		T14	13		T131	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T20	1		T215	6		T210	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T22	2		T129	2		T120	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1113	1			T220	19		T221	16		T139	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T91	2		T137	15		T96	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	14		T172	9		T131	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T18	11		T151	11		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T92	4		T137	16		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T39	9		T56	5		T209	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T138	4		T118	24		T96	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T215	9		T137	11		T60	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	4		T18	14		T168	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T101	13		T229	3		T133	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	12		T122	13		T53	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T14	1		T95	13		T223	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T100	13		T53	8		T218	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T17	15		T38	4		T92	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	1		T138	4		T95	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T224	9		T310	12		T275	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T236	11		T126	14		T277	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T114	9		T104	5		T126	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T95	7		T230	5		T224	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T89	1		T99	1		T277	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T18	1		T192	2		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T104	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	7		T14	13		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T20	6		T215	9		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T22	5		T62	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T99	1		T120	11		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T91	3		T120	11		T130	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	13		T98	15		T309	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T18	1		T102	1		T151	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T23	13		T92	1		T171	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T39	8		T56	6		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T89	1		T90	1		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T215	10		T98	8		T137	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	7		T18	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T101	10		T38	1		T60	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T17	1		T62	1		T103	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T102	1		T223	1		T133	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	3		T97	1		T100	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T17	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1478	1			T10	2		T15	9		T21	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T95	8		T230	6		T224	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T277	11		T272	11		T346	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T18	4		T158	14		T278	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T104	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	4		T14	13		T104	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T20	1		T215	6		T210	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T22	2		T129	2		T96	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T120	10		T155	1		T172	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T91	2		T120	12		T96	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	14		T172	9		T131	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T18	11		T151	11		T137	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T92	4		T137	16		T118	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	9		T56	5		T209	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T138	4		T96	12		T57	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T215	9		T137	11		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	4		T18	14		T168	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T101	13		T60	9		T236	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T17	12		T124	6		T108	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T223	4		T133	4		T216	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T100	13		T122	13		T53	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	1		T17	15		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1110	1			T39	1		T220	19		T221	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	5		T14	14		T22	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T20	5		T215	7		T210	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T22	4		T62	1		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1460	1			T10	2		T15	1		T21	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T102	1		T91	3		T137	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T17	15		T23	1		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	12		T151	12		T345	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T92	5		T137	17		T122	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	10		T56	8		T209	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T89	1		T102	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T215	10		T98	1		T137	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	5		T18	15		T239	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T101	14		T38	1		T229	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	13		T62	1		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	2		T102	1		T95	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	3		T97	1		T100	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T17	16		T38	7		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T89	1		T91	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T224	10		T310	13		T275	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T236	12		T126	15		T277	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16608	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T114	10		T104	6		T132	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	6		T14	12		T93	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	2		T215	8		T120	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T22	1		T129	4		T120	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1070	1			T15	8		T150	10		T98	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T91	2		T137	10		T130	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	12		T23	12		T171	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T151	10		T228	11		T174	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	12		T122	2		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T39	7		T56	3		T282	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T138	16		T103	12		T118	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T215	9		T98	7		T137	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	6		T168	14		T156	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T101	9		T229	2		T133	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T103	13		T122	13		T53	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T95	12		T128	12		T233	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T100	11		T53	9		T242	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T38	2		T100	14		T95	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T91	8		T138	8		T95	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T310	12		T283	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T236	10		T126	12		T277	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T134	12		T244	11		T278	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T126	12		T241	5		T306	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T95	9		T230	7		T224	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T89	1		T99	1		T277	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T18	5		T192	2		T158	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T104	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T13	5		T14	14		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T20	5		T215	7		T210	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T22	6		T62	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T99	1		T120	11		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T91	3		T120	13		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	15		T98	1		T309	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T18	12		T102	1		T151	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T23	1		T92	5		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	10		T56	8		T209	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T89	1		T90	1		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T215	10		T98	1		T137	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	5		T18	15		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T101	14		T38	1		T60	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T17	13		T62	1		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T102	1		T223	5		T133	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	3		T97	1		T100	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	2		T17	16		T38	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1462	1			T10	2		T15	1		T21	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T95	6		T230	4		T106	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T277	8		T347	1		T348	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T278	13		T279	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	6		T14	12		T93	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T20	2		T215	8		T120	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T22	1		T129	4		T96	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T120	10		T172	9		T269	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T91	2		T120	10		T130	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	12		T98	14		T172	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T151	10		T137	10		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T23	12		T171	9		T93	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T39	7		T56	3		T282	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T138	16		T103	12		T96	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T215	9		T98	7		T137	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T13	6		T168	14		T173	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T101	9		T60	7		T236	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T103	13		T108	2		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T133	14		T231	7		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T100	11		T122	13		T53	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T38	2		T100	14		T95	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1126	1			T15	8		T91	8		T150	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8