Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21944

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3096

1

T13

11

T14

26

T17

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18901

1

T6

1

T27

2

T28

1

auto[1]

6139

1

T10

2

T14

26

T15

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	288	1			T22	2		T95	26		T224	13
values[0]	89	1			T95	24		T128	26		T328	6
values[1]	679	1			T18	17		T102	1		T38	3
values[2]	595	1			T89	1		T101	23		T91	5
values[3]	746	1			T62	1		T39	2		T98	8
values[4]	769	1			T13	11		T17	27		T20	7
values[5]	552	1			T22	5		T102	1		T208	1
values[6]	625	1			T14	26		T17	13		T23	13
values[7]	573	1			T102	1		T215	1		T99	1
values[8]	2601	1			T10	2		T14	2		T15	9
values[9]	1068	1			T13	11		T18	15		T62	1
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	630	1			T18	5		T102	1		T38	3
values[1]	601	1			T89	1		T101	23		T91	5
values[2]	796	1			T13	11		T20	7		T62	1
values[3]	774	1			T17	27		T22	5		T38	9
values[4]	528	1			T14	26		T17	13		T102	1
values[5]	573	1			T23	13		T102	1		T215	1
values[6]	2637	1			T10	2		T14	2		T15	9
values[7]	640	1			T17	16		T89	1		T90	1
values[8]	995	1			T13	11		T18	15		T22	2
values[9]	136	1			T62	1		T95	26		T96	29
minimum	16730	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T239	2		T122	3		T337	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T18	1		T102	1		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T101	10		T91	3		T92	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T89	1		T97	1		T39	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	7		T62	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T20	6		T38	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T22	3		T38	5		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	13		T171	10		T137	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T17	1		T208	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	13		T102	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T102	1		T215	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T23	13		T234	15		T289	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T10	2		T14	1		T15	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T138	17		T53	4		T59	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T17	1		T90	1		T91	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T89	1		T215	9		T98	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T18	1		T97	1		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T13	7		T22	2		T151	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T62	1		T166	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T95	13		T96	15		T158	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16400	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T18	1		T93	1		T95	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T122	8		T133	10		T231	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	4		T92	4		T155	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T101	13		T91	2		T92	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T39	9		T137	15		T218	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	4		T39	1		T210	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T20	1		T120	12		T172	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T22	2		T38	4		T104	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	14		T137	11		T230	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T17	12		T96	10		T236	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	13		T60	9		T259	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T210	8		T122	13		T105	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T219	3		T257	18		T299	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T14	1		T220	19		T221	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T138	4		T53	4		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	15		T95	8		T53	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T215	6		T104	5		T295	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T18	14		T129	2		T120	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	4		T151	11		T215	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T327	6		T349	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T95	13		T96	14		T158	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T18	11		T95	12		T350	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T156	7		T166	1		T174	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T22	2		T95	13		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T328	6		T329	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T95	12		T128	15		T351	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T100	12		T94	1		T118	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T18	2		T102	1		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T101	10		T91	3		T92	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T89	1		T97	1		T39	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T62	1		T39	1		T98	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T120	11		T59	1		T228	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	7		T38	5		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	13		T20	6		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T22	3		T208	1		T122	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T102	1		T103	14		T345	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T17	1		T210	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	13		T23	13		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T102	1		T215	1		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T53	4		T235	3		T352	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T10	2		T14	1		T15	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T89	1		T215	9		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T18	1		T62	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T13	7		T151	11		T215	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T156	7		T353	4		T252	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T95	13		T224	12		T174	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T329	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T95	12		T128	11		T351	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T100	13		T118	24		T122	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T18	15		T92	4		T155	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T101	13		T91	2		T92	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T39	9		T137	15		T218	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	1		T210	18		T114	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T120	12		T231	11		T252	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	4		T38	4		T104	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	14		T20	1		T137	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T22	2		T122	13		T96	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T60	9		T259	2		T218	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	12		T210	8		T105	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	13		T219	3		T257	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T100	14		T223	4		T242	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T53	4		T175	4		T192	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T14	1		T17	15		T220	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T215	6		T120	10		T138	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T18	14		T129	2		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	4		T151	11		T215	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T239	2		T122	9		T337	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T18	5		T102	1		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T101	14		T91	3		T92	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T89	1		T97	1		T39	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	5		T62	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T20	5		T38	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T22	4		T38	7		T104	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T17	15		T171	1		T137	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	13		T208	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	14		T102	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T102	1		T215	1		T210	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T23	1		T234	1		T289	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T10	2		T14	2		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T138	5		T53	5		T59	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T17	16		T90	1		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T89	1		T215	7		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T18	15		T97	1		T129	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T13	5		T22	2		T151	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T62	1		T166	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T95	14		T96	15		T158	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16578	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T18	12		T93	1		T95	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T122	2		T133	12		T231	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T57	10		T234	2		T128	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T101	9		T91	2		T130	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T39	7		T137	10		T156	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	6		T98	7		T123	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	2		T120	10		T172	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	1		T38	2		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	12		T171	9		T137	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T103	12		T96	10		T236	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T14	12		T103	13		T60	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T122	13		T227	4		T111	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T23	12		T234	14		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T15	8		T150	10		T270	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T138	16		T53	3		T235	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T91	8		T95	6		T53	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T215	8		T98	14		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T129	4		T120	1		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	6		T151	10		T215	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T332	14		T286	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T95	12		T96	14		T212	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T100	11		T118	8		T173	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T95	11		T145	6		T354	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T156	8		T166	1		T174	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T22	2		T95	14		T224	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T328	1		T329	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T95	13		T128	12		T351	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T100	14		T94	1		T118	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	17		T102	1		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T101	14		T91	3		T92	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T89	1		T97	1		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T62	1		T39	2		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T120	13		T59	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	5		T38	7		T104	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T17	15		T20	5		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T22	4		T208	1		T122	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T102	1		T103	1		T345	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T17	13		T210	9		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	14		T23	1		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T102	1		T215	1		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T53	5		T235	1		T352	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T10	2		T14	2		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T89	1		T215	7		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T18	15		T62	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	5		T151	12		T215	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T156	6		T252	12		T282	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T95	12		T174	11		T212	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T328	5		T329	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T95	11		T128	14		T351	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T100	11		T118	8		T122	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T57	10		T234	2		T217	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T101	9		T91	2		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T39	7		T137	10		T126	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T98	7		T130	5		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T120	10		T228	11		T156	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	6		T38	2		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	12		T20	2		T171	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T22	1		T122	13		T96	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T103	13		T60	7		T131	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T103	12		T333	10		T111	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	12		T23	12		T234	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T100	14		T93	12		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T53	3		T235	2		T192	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T15	8		T91	8		T150	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T215	8		T120	10		T138	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T129	4		T120	1		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	6		T151	10		T215	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8