Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T13	5		T90	1		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T20	5		T38	1		T210	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T10	2		T15	1		T21	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T17	15		T101	14		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T18	5		T99	1		T239	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T17	16		T18	15		T102	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T62	1		T151	12		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T22	2		T89	1		T38	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	13		T103	1		T230	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T92	13		T94	1		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	5		T14	2		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T18	12		T89	1		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T62	1		T130	1		T96	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T38	7		T208	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	14		T208	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T23	1		T92	5		T120	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T102	1		T90	1		T97	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T22	4		T102	1		T91	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T129	3		T215	7		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T104	2		T59	2		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T6	1		T27	2		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	6		T98	14		T236	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T20	2		T137	9		T95	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T15	8		T91	8		T150	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	12		T101	9		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T122	1		T125	9		T235	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	7		T98	7		T100	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T151	10		T171	9		T118	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T100	11		T137	12		T122	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T103	9		T230	4		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T60	7		T125	11		T133	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	6		T172	10		T133	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T137	10		T103	13		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T130	5		T96	14		T128	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	2		T93	12		T172	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T14	12		T93	2		T157	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T23	12		T120	1		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T57	10		T234	14		T242	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	1		T91	2		T120	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T129	4		T215	8		T250	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T241	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T228	11		T251	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T144	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T228	1		T156	1		T245	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T132	1		T246	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T94	1		T236	14		T242	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T20	5		T210	9		T137	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T10	2		T13	5		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T17	15		T101	14		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T99	1		T239	2		T138	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T17	16		T18	15		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T18	5		T62	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	2		T39	10		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	13		T151	12		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T89	1		T38	3		T92	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	5		T14	2		T63	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	2		T208	1		T137	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	14		T96	15		T209	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T18	12		T89	1		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T62	1		T208	1		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	7		T92	5		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T102	1		T90	1		T97	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T22	4		T23	1		T102	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T228	11		T156	15		T245	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T236	4		T242	13		T123	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T20	2		T137	9		T95	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T13	6		T15	8		T91	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T17	12		T101	9		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T138	8		T118	8		T122	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T98	7		T138	16		T95	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T171	9		T236	10		T156	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	7		T100	14		T252	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T151	10		T103	9		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T100	11		T137	12		T122	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	6		T230	4		T172	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T137	10		T125	11		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T14	12		T96	14		T254	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T103	13		T123	9		T173	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T93	2		T130	5		T128	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T38	2		T120	1		T93	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T129	4		T215	8		T57	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T22	1		T23	12		T91	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8