Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21500

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3540

1

T13

11

T14

28

T17

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18935

1

T6

1

T27

2

T28

1

auto[1]

6105

1

T10

2

T13

11

T15

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	427	1			T22	1		T41	3		T42	8
values[0]	56	1			T126	23		T111	6		T128	18
values[1]	666	1			T13	11		T102	2		T92	5
values[2]	3036	1			T10	2		T15	9		T17	13
values[3]	685	1			T101	23		T91	14		T97	1
values[4]	628	1			T14	26		T18	17		T215	15
values[5]	652	1			T17	16		T62	1		T38	1
values[6]	722	1			T14	2		T17	27		T90	1
values[7]	486	1			T23	13		T62	1		T89	1
values[8]	575	1			T13	11		T89	1		T38	3
values[9]	1076	1			T20	7		T22	7		T63	1
minimum	16031	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	918	1			T13	11		T102	2		T92	5
values[1]	3081	1			T10	2		T15	9		T17	13
values[2]	585	1			T18	12		T101	23		T91	14
values[3]	581	1			T14	26		T17	16		T18	5
values[4]	683	1			T97	1		T210	19		T208	1
values[5]	662	1			T14	2		T17	27		T62	1
values[6]	566	1			T23	13		T38	9		T129	7
values[7]	476	1			T13	11		T20	7		T89	1
values[8]	865	1			T22	5		T102	1		T90	1
values[9]	139	1			T22	2		T63	1		T100	25
minimum	16484	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	7		T102	1		T92	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T102	1		T210	1		T100	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T10	2		T15	9		T21	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	1		T18	1		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T18	1		T101	10		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T91	12		T208	1		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T18	1		T38	1		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	13		T17	1		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T208	1		T130	13		T95	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T97	1		T210	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	13		T90	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T62	1		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T38	5		T129	5		T98	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T23	13		T104	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T20	6		T89	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	7		T118	15		T122	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T102	1		T151	11		T98	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	3		T90	1		T239	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T22	2		T253	3		T255	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T63	1		T100	12		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16319	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T257	7		T258	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	4		T92	4		T53	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T210	8		T100	14		T222	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1122	1			T92	12		T215	9		T220	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	12		T18	14		T137	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T18	11		T101	13		T39	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T91	2		T95	13		T57	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T18	4		T96	12		T229	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	13		T17	15		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T95	8		T122	8		T259	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T210	18		T120	10		T95	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T17	14		T224	9		T172	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T216	12		T219	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T38	4		T129	2		T260	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T218	16		T133	10		T261	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T20	1		T39	1		T131	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	4		T118	24		T122	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T151	11		T137	11		T104	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T22	2		T137	15		T230	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T253	1		T262	12		T263	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T100	13		T264	16		T265	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T257	6		T258	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T22	1		T41	3		T42	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T126	13		T111	2		T128	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	7		T102	1		T92	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T102	1		T210	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T10	2		T15	9		T21	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T17	1		T18	1		T100	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T101	10		T97	1		T39	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T91	12		T208	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T18	2		T215	9		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	13		T210	1		T93	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	1		T208	1		T130	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	1		T62	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	13		T90	1		T122	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	1		T97	1		T95	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	5		T129	5		T98	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T23	13		T62	1		T89	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T89	1		T38	3		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	7		T104	1		T118	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T20	6		T22	2		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T22	3		T63	1		T90	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T104	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T126	10		T111	4		T128	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	4		T92	4		T53	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T210	8		T222	15		T219	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T92	12		T220	19		T221	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T17	12		T18	14		T100	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T101	13		T39	9		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T91	2		T104	5		T95	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T18	15		T215	6		T253	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	13		T210	18		T114	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T95	8		T96	12		T259	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	15		T120	21		T96	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	14		T122	8		T224	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	1		T95	12		T96	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T38	4		T129	2		T219	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T218	16		T261	14		T266	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T39	1		T131	2		T216	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	4		T118	24		T122	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T20	1		T151	11		T137	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T22	2		T100	13		T137	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	5		T102	1		T92	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T102	1		T210	9		T100	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T10	2		T15	1		T21	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T17	13		T18	15		T137	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T18	12		T101	14		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T91	4		T208	1		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T18	5		T38	1		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	14		T17	16		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T208	1		T130	1		T95	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T97	1		T210	19		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T17	15		T90	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	2		T62	1		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T38	7		T129	3		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T23	1		T104	1		T218	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T20	5		T89	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	5		T118	31		T122	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T102	1		T151	12		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T22	4		T90	1		T239	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T22	2		T253	2		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T63	1		T100	14		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16456	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T257	7		T258	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	6		T130	5		T53	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T100	14		T103	13		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T15	8		T150	10		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T137	12		T242	13		T235	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T101	9		T39	7		T215	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T91	10		T95	12		T57	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T96	9		T123	9		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	12		T120	1		T93	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T130	12		T95	6		T122	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T120	10		T95	11		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T17	12		T172	10		T227	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T156	6		T232	10		T267	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T38	2		T129	4		T98	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T23	12		T133	12		T268	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T20	2		T131	2		T112	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	6		T118	8		T122	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T151	10		T98	14		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T22	1		T137	10		T230	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T253	2		T255	11		T135	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T100	11		T264	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T257	6		T258	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	427	1			T22	1		T41	3		T42	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T126	11		T111	5		T128	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	5		T102	1		T92	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T102	1		T210	9		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T10	2		T15	1		T21	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T17	13		T18	15		T100	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T101	14		T97	1		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T91	4		T208	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T18	17		T215	7		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	14		T210	19		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	1		T208	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T17	16		T62	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T17	15		T90	1		T122	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	2		T97	1		T95	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	7		T129	3		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T23	1		T62	1		T89	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T89	1		T38	3		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	5		T104	1		T118	31
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T20	5		T22	2		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T22	4		T63	1		T90	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16031	1			T6	1		T27	2		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T126	12		T111	1		T128	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	6		T53	12		T236	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T222	12		T125	12		T269	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T15	8		T150	10		T270	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T100	14		T137	12		T103	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T101	9		T39	7		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T91	10		T95	12		T60	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T215	8		T171	9		T253	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	12		T93	2		T103	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T130	12		T95	6		T96	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T120	11		T122	1		T96	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T17	12		T122	2		T172	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T95	11		T96	10		T172	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	2		T129	4		T98	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T23	12		T266	4		T254	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T271	11		T131	2		T112	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	6		T118	8		T122	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T20	2		T151	10		T98	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T22	1		T100	11		T137	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8