Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19535

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

5505

1

T10

2

T13

11

T15

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19623

1

T6

1

T27

2

T28

1

auto[1]

5417

1

T10

2

T13

11

T15

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	33	1			T197	16		T272	12		T273	5
values[0]	109	1			T104	6		T126	23		T109	14
values[1]	789	1			T13	11		T14	26		T18	5
values[2]	621	1			T22	7		T62	1		T63	1
values[3]	642	1			T17	27		T91	5		T98	15
values[4]	827	1			T18	12		T23	13		T102	1
values[5]	532	1			T89	1		T39	17		T215	1
values[6]	673	1			T13	11		T18	15		T102	1
values[7]	756	1			T62	1		T101	23		T38	1
values[8]	590	1			T17	13		T102	1		T38	3
values[9]	3013	1			T10	2		T14	2		T15	9
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	976	1			T13	11		T14	26		T18	5
values[1]	2877	1			T10	2		T15	9		T17	27
values[2]	573	1			T23	13		T91	5		T99	1
values[3]	718	1			T18	12		T102	1		T92	5
values[4]	534	1			T89	1		T102	1		T90	1
values[5]	729	1			T13	11		T18	15		T215	19
values[6]	711	1			T17	13		T62	1		T101	23
values[7]	542	1			T14	2		T102	1		T38	3
values[8]	713	1			T17	16		T89	1		T38	9
values[9]	211	1			T224	10		T236	22		T232	11
minimum	16456	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T13	7		T14	13		T18	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	6		T215	9		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T22	3		T62	1		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1441	1			T10	2		T15	9		T17	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T91	3		T171	10		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T23	13		T99	1		T103	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	1		T102	1		T151	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T92	1		T93	3		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T39	8		T56	6		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T89	1		T102	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T215	10		T137	10		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	7		T18	1		T239	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T101	10		T38	1		T98	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	1		T62	1		T103	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	1		T102	1		T95	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T38	3		T97	1		T100	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T17	1		T38	5		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T89	1		T39	1		T99	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T224	1		T274	4		T275	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T236	11		T232	11		T126	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16319	1			T11	16		T12	20		T16	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T13	4		T14	13		T18	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T20	1		T215	6		T210	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T22	2		T129	2		T120	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1122	1			T17	14		T220	19		T221	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T91	2		T137	15		T96	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T172	9		T131	2		T105	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T18	11		T151	11		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T92	4		T137	16		T118	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T39	9		T56	5		T209	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T138	4		T96	12		T276	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T215	9		T137	11		T60	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	4		T18	14		T168	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T101	13		T223	4		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	12		T122	13		T124	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T14	1		T95	13		T133	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T100	13		T138	4		T53	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	15		T38	4		T92	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T39	1		T95	12		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T224	9		T274	1		T275	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T236	11		T126	14		T277	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T197	8		T272	1		T273	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T109	1		T278	22		T279	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T104	1		T126	13		T280	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	7		T14	13		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T20	6		T215	9		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T22	5		T62	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T99	1		T155	3		T172	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T91	3		T120	11		T130	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	13		T98	15		T93	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T18	1		T102	1		T151	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T23	13		T92	1		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	8		T56	6		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T89	1		T215	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T215	10		T98	8		T137	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	7		T18	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T101	10		T38	1		T60	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T62	1		T103	14		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T102	1		T223	1		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T17	1		T38	3		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T14	1		T17	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1420	1			T10	2		T15	9		T21	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T197	8		T272	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T109	13		T278	17		T279	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T104	5		T126	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	4		T14	13		T18	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T20	1		T215	6		T210	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T22	2		T129	2		T224	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	1		T172	2		T124	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T91	2		T120	12		T96	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	14		T172	9		T218	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T18	11		T151	11		T137	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T92	4		T137	16		T118	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	9		T56	5		T209	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T138	4		T96	12		T57	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T215	9		T137	11		T236	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	4		T18	14		T168	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T101	13		T60	9		T229	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T124	6		T108	7		T281	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T223	4		T216	8		T107	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	12		T100	13		T122	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	1		T17	15		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1081	1			T39	1		T220	19		T221	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T13	5		T14	14		T18	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T20	5		T215	7		T210	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T22	4		T62	1		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1469	1			T10	2		T15	1		T17	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T91	3		T171	1		T137	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T23	1		T99	1		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T18	12		T102	1		T151	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T92	5		T93	1		T137	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	10		T56	8		T209	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T89	1		T102	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T215	10		T137	12		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	5		T18	15		T239	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T101	14		T38	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T17	13		T62	1		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	2		T102	1		T95	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T38	3		T97	1		T100	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T17	16		T38	7		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T89	1		T39	2		T99	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T224	10		T274	4		T275	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T236	12		T232	1		T126	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16456	1			T6	1		T27	2		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	6		T14	12		T93	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	2		T215	8		T120	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T22	1		T129	4		T120	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1094	1			T15	8		T17	12		T150	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T91	2		T171	9		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T23	12		T103	9		T172	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T151	10		T125	9		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T93	2		T137	12		T118	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T39	7		T56	3		T282	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T138	16		T103	12		T96	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T215	9		T137	9		T60	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	6		T168	14		T156	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T101	9		T98	7		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T103	13		T122	13		T108	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T95	12		T133	1		T128	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T100	11		T138	8		T53	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	2		T91	8		T100	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T95	11		T123	7		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T274	1		T283	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T236	10		T232	10		T126	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T197	9		T272	12		T273	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T109	14		T278	19		T279	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T104	6		T126	11		T280	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T13	5		T14	14		T18	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T20	5		T215	7		T210	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T22	6		T62	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T99	1		T155	4		T172	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T91	3		T120	13		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	15		T98	1		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T18	12		T102	1		T151	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T23	1		T92	5		T137	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	10		T56	8		T209	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T89	1		T215	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T215	10		T98	1		T137	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	5		T18	15		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T101	14		T38	1		T60	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T62	1		T103	1		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T102	1		T223	5		T216	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T17	13		T38	3		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T14	2		T17	16		T38	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1440	1			T10	2		T15	1		T21	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T197	7		T273	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T278	20		T279	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T126	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	6		T14	12		T93	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T20	2		T215	8		T120	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T22	1		T129	4		T131	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T172	9		T284	6		T285	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T91	2		T120	10		T130	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T17	12		T98	14		T93	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T151	10		T171	9		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T23	12		T137	12		T103	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T39	7		T56	3		T282	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T138	16		T103	12		T96	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T215	9		T98	7		T137	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	6		T168	14		T173	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T101	9		T60	7		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T103	13		T108	2		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T231	7		T128	12		T267	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T100	11		T122	13		T53	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T38	2		T91	8		T100	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1061	1			T15	8		T150	10		T270	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8