Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21567

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3473

1

T14

26

T17

43

T18

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19381

1

T6

1

T27

2

T28

1

auto[1]

5659

1

T10

2

T13

11

T14

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T206	1		T244	6		T286	6
values[0]	88	1			T59	1		T287	10		T288	9
values[1]	636	1			T17	13		T23	13		T38	1
values[2]	850	1			T18	12		T62	1		T101	23
values[3]	648	1			T14	26		T89	1		T137	26
values[4]	2765	1			T10	2		T15	9		T21	2
values[5]	645	1			T14	2		T89	1		T102	1
values[6]	711	1			T129	7		T99	1		T259	3
values[7]	683	1			T18	5		T97	1		T215	1
values[8]	582	1			T13	11		T20	7		T62	1
values[9]	964	1			T13	11		T17	43		T18	15
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	971	1			T17	13		T18	12		T23	13
values[1]	831	1			T14	26		T62	1		T89	1
values[2]	520	1			T99	1		T93	1		T94	1
values[3]	2788	1			T10	2		T15	9		T21	2
values[4]	758	1			T14	2		T39	2		T100	25
values[5]	613	1			T129	7		T215	1		T99	1
values[6]	723	1			T13	11		T18	5		T20	7
values[7]	514	1			T18	15		T62	1		T91	9
values[8]	751	1			T17	43		T22	2		T38	9
values[9]	116	1			T13	11		T38	3		T289	1
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T17	1		T23	13		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T18	1		T101	10		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T89	1		T137	11		T104	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	13		T62	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T93	1		T94	1		T95	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T99	1		T224	1		T131	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T10	2		T15	9		T21	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T22	3		T63	1		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	1		T39	1		T100	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T120	11		T239	2		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T129	5		T215	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T103	10		T105	1		T108	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	7		T20	6		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T18	1		T97	1		T98	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T94	1		T103	14		T95	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T18	1		T62	1		T91	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T22	2		T38	5		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	14		T92	1		T96	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T13	7		T38	3		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T289	1		T290	1		T192	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	12		T151	11		T120	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T18	11		T101	13		T91	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T137	15		T104	6		T118	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	13		T39	9		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T95	13		T155	1		T236	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T224	12		T131	12		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T220	19		T221	16		T138	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	2		T137	11		T222	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	1		T39	1		T100	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T120	10		T60	9		T172	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T129	2		T259	2		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T105	13		T108	3		T126	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	4		T20	1		T210	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T18	4		T137	16		T105	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T95	12		T236	11		T124	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T18	14		T223	4		T242	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T38	4		T120	12		T96	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	29		T92	12		T96	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T13	4		T291	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T192	1		T258	7		T292	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T244	1		T286	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T206	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T293	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T59	1		T287	10		T288	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	1		T23	13		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T38	1		T91	3		T92	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T102	1		T118	15		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T18	1		T62	1		T101	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T89	1		T137	11		T95	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	13		T168	15		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T10	2		T15	9		T21	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T22	3		T63	1		T171	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T39	1		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T89	1		T102	1		T120	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T129	5		T99	1		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T172	11		T105	1		T108	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T215	1		T210	1		T138	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T18	1		T97	1		T98	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	7		T20	6		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T62	1		T91	9		T92	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T13	7		T22	2		T38	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T17	14		T18	1		T96	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T244	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T288	4		T272	18		T294	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T17	12		T151	11		T120	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T91	2		T92	4		T215	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T118	24		T281	9		T126	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T18	11		T101	13		T39	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	15		T95	13		T155	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	13		T168	15		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T220	19		T221	16		T100	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	2		T222	15		T56	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	1		T39	1		T209	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T120	10		T137	11		T60	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T129	2		T259	2		T218	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T172	9		T105	13		T108	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T210	18		T138	4		T53	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T18	4		T105	11		T295	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	4		T20	1		T95	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T92	12		T137	16		T249	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	4		T38	4		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	29		T18	14		T96	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T17	13		T23	1		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T18	12		T101	14		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T89	1		T137	16		T104	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	14		T62	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T93	1		T94	1		T95	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T99	1		T224	13		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T10	2		T15	1		T21	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T22	4		T63	1		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	2		T39	2		T100	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T120	11		T239	2		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T129	3		T215	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T103	1		T105	14		T108	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	5		T20	5		T210	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T18	5		T97	1		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T94	1		T103	1		T95	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T18	15		T62	1		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T22	2		T38	7		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	31		T92	13		T96	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T13	5		T38	3		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T289	1		T290	1		T192	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T23	12		T151	10		T120	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T101	9		T91	2		T215	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T137	10		T118	8		T236	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	12		T39	7		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T95	12		T236	4		T296	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T131	8		T242	7		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T15	8		T150	10		T270	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	1		T171	9		T137	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T100	11		T123	9		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T120	10		T60	7		T172	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T129	4		T172	9		T227	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T103	9		T108	2		T126	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	6		T20	2		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T98	7		T93	12		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T103	13		T95	11		T236	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T91	8		T242	5		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T38	2		T120	10		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T17	12		T96	14		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T13	6		T135	15		T297	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T192	1		T258	7		T298	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T244	6		T286	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T206	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T293	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T59	1		T287	1		T288	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T17	13		T23	1		T151	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T38	1		T91	3		T92	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T102	1		T118	31		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T18	12		T62	1		T101	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T89	1		T137	16		T95	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	14		T168	16		T224	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T10	2		T15	1		T21	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T22	4		T63	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	2		T39	2		T209	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T89	1		T102	1		T120	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T129	3		T99	1		T259	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T172	10		T105	14		T108	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T215	1		T210	19		T138	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T18	5		T97	1		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	5		T20	5		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T62	1		T91	1		T92	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	5		T22	2		T38	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T17	31		T18	15		T96	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T286	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T293	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T287	9		T288	4		T145	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T23	12		T151	10		T120	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T91	2		T215	8		T100	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T118	8		T281	7		T126	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T101	9		T39	7		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T137	10		T95	12		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	12		T168	14		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T15	8		T150	10		T270	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	1		T171	9		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T123	9		T229	2		T108	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T120	10		T137	9		T60	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T129	4		T227	4		T252	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T172	10		T108	2		T156	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T138	8		T53	9		T172	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T98	7		T103	9		T234	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	6		T20	2		T103	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T91	8		T93	12		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	6		T38	2		T120	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	12		T96	14		T234	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8