Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21550

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3490

1

T13

11

T14

28

T17

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19376

1

T6

1

T27

2

T28

1

auto[1]

5664

1

T10

2

T13

22

T14

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T100	25		T299	5		-	-
values[0]	27	1			T300	1		T301	26		-	-
values[1]	816	1			T89	1		T90	1		T91	5
values[2]	584	1			T17	27		T18	12		T22	5
values[3]	665	1			T13	11		T38	3		T97	1
values[4]	598	1			T20	7		T102	2		T38	9
values[5]	2592	1			T10	2		T15	9		T21	2
values[6]	723	1			T13	11		T18	5		T90	1
values[7]	738	1			T14	28		T17	13		T23	13
values[8]	686	1			T18	15		T89	1		T38	1
values[9]	1126	1			T17	16		T22	2		T62	1
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	937	1			T17	27		T22	5		T89	1
values[1]	679	1			T18	12		T102	1		T38	3
values[2]	515	1			T13	11		T102	1		T38	9
values[3]	2721	1			T10	2		T15	9		T20	7
values[4]	503	1			T62	1		T90	1		T39	17
values[5]	745	1			T13	11		T18	5		T99	1
values[6]	802	1			T14	28		T17	13		T23	13
values[7]	715	1			T17	16		T18	15		T38	1
values[8]	645	1			T22	2		T62	1		T92	5
values[9]	294	1			T101	23		T100	29		T252	26
minimum	16484	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T17	13		T91	3		T171	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T22	3		T89	1		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T18	1		T102	1		T120	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T38	3		T97	1		T98	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	7		T38	5		T129	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T102	1		T97	1		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T10	2		T15	9		T21	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	6		T92	1		T151	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	8		T138	9		T95	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T62	1		T90	1		T120	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T95	12		T60	8		T240	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	7		T18	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T63	1		T89	1		T91	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	14		T17	1		T23	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T18	1		T138	17		T130	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	1		T38	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T22	2		T215	10		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T62	1		T92	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T252	13		T110	1		T263	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T101	10		T100	15		T282	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T215	9		T243	1		T302	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T17	14		T91	2		T118	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T22	2		T53	4		T224	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	11		T120	12		T236	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T104	5		T133	4		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T13	4		T38	4		T129	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T210	8		T212	9		T303	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T220	19		T221	16		T139	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T20	1		T92	12		T151	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T39	9		T138	4		T95	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T120	11		T137	15		T96	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T95	12		T60	9		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	4		T18	4		T95	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T104	1		T222	15		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	14		T17	12		T122	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T18	14		T138	4		T172	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	15		T39	1		T137	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T215	9		T53	8		T56	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T92	4		T100	13		T120	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T252	13		T110	2		T263	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T101	13		T100	14		T276	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T215	6		T243	2		T302	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T100	12		T299	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T300	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T301	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T91	3		T171	10		T118	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T89	1		T90	1		T215	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T17	13		T18	1		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T22	3		T97	1		T98	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	7		T155	3		T236	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T38	3		T97	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T102	1		T38	5		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T20	6		T102	1		T92	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T10	2		T15	9		T21	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T62	1		T151	11		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T104	1		T95	19		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	7		T18	1		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T63	1		T91	9		T138	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	14		T17	1		T23	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T18	1		T89	1		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	1		T137	10		T103	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	2		T215	10		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T17	1		T62	1		T101	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T100	13		T299	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T301	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T91	2		T118	24		T218	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T215	6		T53	4		T218	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	14		T18	11		T129	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T22	2		T224	12		T108	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	4		T155	1		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T210	26		T114	9		T104	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T38	4		T122	8		T96	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T20	1		T92	12		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T39	9		T220	19		T221	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T151	11		T137	15		T96	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T104	1		T95	20		T60	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	4		T18	4		T120	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T138	4		T222	15		T57	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	14		T17	12		T122	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T18	14		T223	4		T105	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	11		T218	11		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T215	9		T53	8		T56	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T17	15		T101	13		T92	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T17	15		T91	3		T171	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T22	4		T89	1		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T18	12		T102	1		T120	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T38	3		T97	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	5		T38	7		T129	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T102	1		T97	1		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T10	2		T15	1		T21	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T20	5		T92	13		T151	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T39	10		T138	5		T95	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T62	1		T90	1		T120	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T95	13		T60	10		T240	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	5		T18	5		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T63	1		T89	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	16		T17	13		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T18	15		T138	5		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	16		T38	1		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T22	2		T215	10		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T62	1		T92	5		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T252	14		T110	3		T263	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T101	14		T100	15		T282	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T215	7		T243	3		T302	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T17	12		T91	2		T171	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T22	1		T98	14		T53	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T120	10		T236	4		T174	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T98	7		T125	12		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	6		T38	2		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T93	12		T103	9		T122	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T15	8		T150	10		T270	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T20	2		T151	10		T134	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T39	7		T138	8		T95	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T120	1		T137	10		T96	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T95	11		T60	7		T123	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	6		T95	12		T96	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T91	8		T222	12		T57	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	12		T23	12		T103	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T138	16		T130	5		T234	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T137	9		T103	13		T236	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T215	9		T53	9		T56	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T100	11		T120	10		T93	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T252	12		T263	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T101	9		T100	14		T282	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T215	8		T302	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T100	14		T299	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T300	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T301	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T91	3		T171	1		T118	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T89	1		T90	1		T215	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	15		T18	12		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T22	4		T97	1		T98	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	5		T155	4		T236	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T38	3		T97	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T102	1		T38	7		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T20	5		T102	1		T92	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T10	2		T15	1		T21	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T62	1		T151	12		T137	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T104	2		T95	22		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	5		T18	5		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T63	1		T91	1		T138	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	16		T17	13		T23	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T18	15		T89	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T38	1		T137	12		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T22	2		T215	10		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	427	1			T17	16		T62	1		T101	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T100	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T301	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T91	2		T171	9		T118	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T215	8		T53	3		T271	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	12		T129	4		T120	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T22	1		T98	21		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	6		T236	4		T174	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T93	12		T103	9		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T38	2		T130	12		T122	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T20	2		T122	1		T134	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T15	8		T150	10		T39	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T151	10		T137	10		T96	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T95	17		T60	7		T172	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	6		T120	1		T95	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T91	8		T138	16		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	12		T23	12		T103	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T130	5		T108	2		T268	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T137	9		T103	13		T236	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T215	9		T53	9		T56	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T101	9		T100	14		T120	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8