Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21566

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3474

1

T14

26

T17

43

T18

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19381

1

T6

1

T27

2

T28

1

auto[1]

5659

1

T10

2

T13

11

T14

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T22	2		T38	3		T96	22
values[0]	41	1			T287	10		T288	9		T145	7
values[1]	681	1			T17	13		T23	13		T91	5
values[2]	811	1			T18	12		T62	1		T101	23
values[3]	708	1			T14	26		T89	1		T99	1
values[4]	2702	1			T10	2		T15	9		T21	2
values[5]	657	1			T14	2		T89	1		T120	21
values[6]	742	1			T39	2		T129	7		T99	1
values[7]	686	1			T18	5		T20	7		T97	1
values[8]	550	1			T13	11		T62	1		T91	9
values[9]	736	1			T13	11		T17	43		T18	15
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	712	1			T18	12		T23	13		T101	23
values[1]	819	1			T14	26		T62	1		T38	1
values[2]	598	1			T89	1		T99	1		T94	1
values[3]	2734	1			T10	2		T15	9		T21	2
values[4]	741	1			T14	2		T89	1		T39	2
values[5]	672	1			T129	7		T215	1		T99	1
values[6]	683	1			T13	11		T18	5		T20	7
values[7]	550	1			T18	15		T91	9		T92	13
values[8]	761	1			T13	11		T17	43		T22	2
values[9]	74	1			T289	1		T132	1		T290	1
minimum	16696	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T23	13		T102	1		T151	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T18	1		T101	10		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T137	11		T104	1		T118	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	13		T62	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T89	1		T94	1		T95	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T99	1		T224	1		T131	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T10	2		T15	9		T21	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T22	3		T63	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	1		T39	1		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T89	1		T120	11		T239	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T129	5		T215	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T103	10		T105	1		T108	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	7		T20	6		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T18	1		T62	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T94	1		T103	14		T95	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T18	1		T91	9		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T13	7		T22	2		T38	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T17	14		T96	15		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T132	1		T277	2		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T289	1		T290	1		T192	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16359	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T92	1		T100	15		T59	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T151	11		T120	11		T104	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T18	11		T101	13		T91	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T137	15		T104	5		T118	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	13		T39	9		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T95	13		T155	1		T236	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T224	12		T131	12		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T220	19		T221	16		T100	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T22	2		T222	15		T56	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	1		T39	1		T218	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T120	10		T137	11		T60	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T129	2		T259	2		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T105	13		T108	3		T126	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	4		T20	1		T210	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T18	4		T137	16		T105	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T95	12		T53	4		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T18	14		T92	12		T223	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	4		T38	4		T120	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T17	29		T96	14		T253	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T192	1		T264	16		T304	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T92	4		T100	14		T276	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T22	2		T38	3		T96	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T289	1		T125	12		T253	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T287	10		T288	5		T145	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	1		T23	13		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T91	3		T92	1		T215	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T102	1		T104	1		T118	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T18	1		T62	1		T101	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T89	1		T137	11		T95	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	13		T99	1		T168	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T10	2		T15	9		T21	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	3		T63	1		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T209	1		T123	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T89	1		T120	11		T239	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	1		T129	5		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T103	10		T222	1		T172	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T20	6		T215	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T18	1		T97	1		T98	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	7		T94	1		T103	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T62	1		T91	9		T92	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	7		T38	5		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T17	14		T18	1		T96	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T96	12		T133	1		T253	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T253	1		T107	2		T258	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T288	4		T294	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	12		T151	11		T120	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T91	2		T92	4		T215	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T104	5		T118	24		T281	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	11		T101	13		T39	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T137	15		T95	13		T155	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	13		T168	15		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T220	19		T221	16		T100	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T22	2		T56	5		T57	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	1		T209	9		T229	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T120	10		T137	11		T222	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	1		T129	2		T259	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T172	9		T108	3		T143	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T20	1		T210	18		T138	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T18	4		T105	24		T295	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	4		T95	12		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T92	12		T137	16		T124	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	4		T38	4		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	29		T18	14		T96	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T23	1		T102	1		T151	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T18	12		T101	14		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T137	16		T104	6		T118	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T14	14		T62	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T89	1		T94	1		T95	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T99	1		T224	13		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T10	2		T15	1		T21	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T22	4		T63	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	2		T39	2		T218	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T89	1		T120	11		T239	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T129	3		T215	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T103	1		T105	14		T108	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	5		T20	5		T210	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T18	5		T62	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T94	1		T103	1		T95	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T18	15		T91	1		T92	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	5		T22	2		T38	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	31		T96	15		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T132	1		T277	2		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T289	1		T290	1		T192	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16521	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T92	5		T100	15		T59	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T23	12		T151	10		T120	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T101	9		T91	2		T215	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T137	10		T118	8		T281	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	12		T39	7		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T95	12		T236	11		T242	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T131	8		T242	7		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T15	8		T150	10		T270	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	1		T171	9		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T123	9		T229	2		T108	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T120	10		T137	9		T60	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T129	4		T172	9		T227	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T103	9		T108	2		T126	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	6		T20	2		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T98	7		T93	12		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T103	13		T95	11		T53	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T91	8		T242	5		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	6		T38	2		T120	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T17	12		T96	14		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T192	1		T264	2		T304	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T267	4		T305	12		T306	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T100	14		T276	3		T287	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T22	2		T38	3		T96	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T289	1		T125	1		T253	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T287	1		T288	5		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T17	13		T23	1		T151	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T91	3		T92	5		T215	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T102	1		T104	6		T118	31
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T18	12		T62	1		T101	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T89	1		T137	16		T95	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	14		T99	1		T168	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T10	2		T15	1		T21	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T22	4		T63	1		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	2		T209	10		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T89	1		T120	11		T239	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T39	2		T129	3		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T103	1		T222	1		T172	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T20	5		T215	1		T210	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T18	5		T97	1		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	5		T94	1		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T62	1		T91	1		T92	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	5		T38	7		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T17	31		T18	15		T96	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T96	9		T235	10		T133	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T125	11		T253	2		T258	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T287	9		T288	4		T145	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T23	12		T151	10		T120	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T91	2		T215	8		T100	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T118	8		T281	7		T126	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T101	9		T39	7		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T137	10		T95	12		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	12		T168	14		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T15	8		T150	10		T270	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	1		T171	9		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T123	9		T229	2		T108	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T120	10		T137	9		T222	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T129	4		T172	9		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T103	9		T172	10		T108	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T20	2		T138	8		T53	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T98	7		T234	2		T156	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	6		T103	13		T95	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T91	8		T93	12		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	6		T38	2		T120	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T17	12		T96	14		T234	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8