Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21230

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3810

1

T13

11

T14

28

T17

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18961

1

T6

1

T27

2

T28

1

auto[1]

6079

1

T10

2

T13

11

T15

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	758	1			T22	3		T41	3		T42	8
values[0]	11	1			T235	1		T307	9		T308	1
values[1]	767	1			T13	11		T102	2		T92	5
values[2]	2967	1			T10	2		T15	9		T17	13
values[3]	708	1			T101	23		T91	14		T97	1
values[4]	586	1			T14	26		T17	16		T18	17
values[5]	682	1			T38	1		T208	1		T99	1
values[6]	684	1			T14	2		T17	27		T89	1
values[7]	556	1			T62	1		T38	9		T129	7
values[8]	520	1			T13	11		T23	13		T89	1
values[9]	770	1			T20	7		T22	5		T63	1
minimum	16031	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	820	1			T13	11		T102	2		T92	5
values[1]	2991	1			T10	2		T15	9		T17	13
values[2]	564	1			T18	12		T101	23		T91	14
values[3]	593	1			T14	26		T17	16		T18	5
values[4]	691	1			T97	1		T208	1		T99	1
values[5]	673	1			T14	2		T17	27		T62	1
values[6]	616	1			T23	13		T38	9		T129	7
values[7]	401	1			T13	11		T20	7		T89	1
values[8]	922	1			T22	5		T63	1		T102	1
values[9]	92	1			T22	2		T100	25		T255	12
minimum	16677	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	7		T102	1		T92	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T102	1		T215	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T10	2		T15	9		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T18	1		T215	10		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T18	1		T101	10		T91	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T91	9		T215	9		T208	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T38	1		T39	8		T93	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	13		T17	1		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T208	1		T130	13		T122	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T97	1		T99	1		T120	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	13		T90	1		T122	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	1		T62	1		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T38	5		T129	5		T93	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T23	13		T98	8		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T20	6		T89	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	7		T118	15		T131	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T102	1		T90	1		T137	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T22	3		T63	1		T151	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T22	2		T135	16		T237	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T100	12		T255	12		T262	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16420	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T309	1		T219	1		T310	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	4		T92	4		T53	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T210	8		T100	14		T222	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T17	12		T92	12		T220	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T18	14		T215	9		T137	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T18	11		T101	13		T91	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T215	6		T95	13		T57	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T39	9		T114	9		T95	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	13		T17	15		T18	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T242	12		T249	4		T229	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T120	10		T95	12		T96	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T17	14		T122	8		T172	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	1		T224	9		T124	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T38	4		T129	2		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T168	15		T218	16		T261	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T20	1		T39	1		T236	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	4		T118	24		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T137	11		T104	1		T218	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T22	2		T151	11		T137	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T100	13		T262	12		T264	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T219	3		T310	10		T311	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	534	1			T22	3		T41	3		T42	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T137	11		T230	5		T125	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T235	1		T307	6		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	7		T102	1		T92	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T102	1		T215	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T10	2		T15	9		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T18	1		T100	15		T137	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T101	10		T91	3		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T91	9		T215	19		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T18	1		T171	10		T93	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	13		T17	1		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T38	1		T208	1		T130	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T99	1		T120	13		T96	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	13		T90	1		T122	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	1		T89	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T38	5		T129	5		T93	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T62	1		T98	8		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T89	1		T38	3		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	7		T23	13		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T20	6		T102	1		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T22	3		T63	1		T151	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T104	1		T236	11		T269	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T137	15		T230	6		T133	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T307	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	4		T92	4		T53	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T210	8		T222	15		T219	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T17	12		T92	12		T220	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T18	14		T100	14		T137	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T101	13		T91	2		T39	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T215	15		T138	4		T95	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T18	11		T114	9		T155	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	13		T17	15		T18	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T95	8		T242	12		T249	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T120	21		T96	26		T259	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	14		T122	8		T172	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	1		T95	12		T96	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T38	4		T129	2		T219	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T218	16		T261	14		T156	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T39	1		T131	2		T133	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	4		T118	24		T122	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T20	1		T137	11		T218	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T22	2		T151	11		T100	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	5		T102	1		T92	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T102	1		T215	1		T210	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T10	2		T15	1		T17	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T18	15		T215	10		T137	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	12		T101	14		T91	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T91	1		T215	7		T208	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T38	1		T39	10		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T14	14		T17	16		T18	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T208	1		T130	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T97	1		T99	1		T120	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T17	15		T90	1		T122	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	2		T62	1		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T38	7		T129	3		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T23	1		T98	1		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T20	5		T89	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	5		T118	31		T131	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T102	1		T90	1		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T22	4		T63	1		T151	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T22	2		T135	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T100	14		T255	1		T262	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16519	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T309	1		T219	4		T310	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	6		T130	5		T103	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T100	14		T222	12		T242	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T15	8		T150	10		T270	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T215	9		T137	12		T138	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T101	9		T91	2		T171	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T91	8		T215	8		T95	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T39	7		T93	2		T95	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	12		T120	1		T103	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T130	12		T122	1		T242	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T120	10		T95	11		T96	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	12		T122	2		T172	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T156	6		T267	13		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T38	2		T129	4		T93	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T23	12		T98	7		T168	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T20	2		T236	4		T131	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T13	6		T118	8		T131	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T137	9		T103	9		T234	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	1		T151	10		T98	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T135	15		T237	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T100	11		T255	11		T264	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T53	9		T106	16		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T292	13		T311	1		T312	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	491	1			T22	3		T41	3		T42	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T137	16		T230	7		T125	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T235	1		T307	6		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	5		T102	1		T92	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T102	1		T215	1		T210	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T10	2		T15	1		T17	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T18	15		T100	15		T137	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T101	14		T91	3		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T91	1		T215	17		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T18	12		T171	1		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T14	14		T17	16		T18	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	1		T208	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T99	1		T120	23		T96	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	15		T90	1		T122	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	2		T89	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T38	7		T129	3		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T62	1		T98	1		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T89	1		T38	3		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	5		T23	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T20	5		T102	1		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T22	4		T63	1		T151	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16031	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T103	9		T236	10		T111	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T137	10		T230	4		T125	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T307	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	6		T130	5		T53	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T222	12		T125	12		T126	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T15	8		T150	10		T270	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T100	14		T137	12		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T101	9		T91	2		T39	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T91	8		T215	17		T138	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T171	9		T93	2		T253	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	12		T103	12		T56	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T130	12		T95	6		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T120	11		T96	23		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T17	12		T122	2		T172	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T95	11		T96	10		T172	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T38	2		T129	4		T93	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T98	7		T234	2		T156	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T131	2		T133	12		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	6		T23	12		T118	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T20	2		T137	9		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T22	1		T151	10		T98	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8