Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25040

1

T6

1

T27

2

T28

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21537

1

T6

1

T27

2

T28

1

auto[ADC_CTRL_FILTER_COND_OUT]

3503

1

T14

28

T17

13

T22

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19235

1

T6

1

T27

2

T28

1

auto[1]

5805

1

T10

2

T15

9

T17

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T10

2

T11

16

T12

20

auto[1]

4132

1

T6

1

T27

2

T28

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T313	2		T314	1		T315	10
values[0]	88	1			T256	1		T285	25		T278	23
values[1]	884	1			T22	5		T62	1		T89	1
values[2]	649	1			T62	1		T120	23		T96	29
values[3]	595	1			T14	28		T17	16		T18	5
values[4]	769	1			T13	22		T22	2		T92	13
values[5]	2675	1			T10	2		T15	9		T17	27
values[6]	567	1			T102	2		T38	3		T208	1
values[7]	541	1			T17	13		T18	15		T20	7
values[8]	559	1			T39	17		T129	7		T239	2
values[9]	1245	1			T18	12		T90	1		T91	9
minimum	16455	1			T6	1		T27	2		T28	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1053	1			T22	5		T62	1		T89	1
values[1]	734	1			T14	28		T18	5		T38	1
values[2]	641	1			T17	16		T22	2		T62	1
values[3]	2670	1			T10	2		T13	11		T15	9
values[4]	673	1			T13	11		T17	27		T23	13
values[5]	543	1			T17	13		T102	1		T208	1
values[6]	512	1			T18	15		T20	7		T63	1
values[7]	518	1			T39	19		T129	7		T239	2
values[8]	984	1			T90	1		T91	9		T92	5
values[9]	206	1			T18	12		T168	30		T166	1
minimum	16506	1			T6	1		T27	2		T28	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

3533

1

T13

12

T14

12

T15

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T22	3		T62	1		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T89	1		T97	1		T98	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	1		T38	1		T172	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	14		T210	1		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T17	1		T62	1		T95	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T22	2		T101	10		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T10	2		T13	7		T15	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T92	1		T215	9		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	7		T17	13		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T23	13		T102	1		T38	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T120	11		T171	10		T93	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	1		T102	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T18	1		T20	6		T100	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T63	1		T215	1		T100	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	8		T129	5		T239	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T39	1		T137	11		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T90	1		T92	1		T120	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T91	9		T215	10		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T18	1		T168	15		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T233	10		T280	1		T286	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16319	1			T11	16		T12	20		T16	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T206	1		T213	13		T316	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T22	2		T137	11		T138	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T122	13		T105	6		T216	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	4		T172	9		T236	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	14		T210	8		T120	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T17	15		T95	8		T57	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T101	13		T151	11		T53	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T13	4		T91	2		T220	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T92	12		T215	6		T137	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	4		T17	14		T104	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T38	4		T104	1		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T120	10		T209	9		T317	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	12		T96	10		T143	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T18	14		T20	1		T100	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T100	14		T53	8		T219	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T39	9		T129	2		T124	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T39	1		T137	15		T118	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T92	4		T120	11		T138	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T215	9		T210	18		T261	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T18	11		T168	15		T318	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T148	25		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	1		T27	2		T28	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T213	15		T316	12		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T313	1		T314	1		T315	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T291	12		T273	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T256	1		T285	12		T278	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	3		T62	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T89	1		T97	1		T98	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T62	1		T224	1		T172	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T120	11		T96	15		T230	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T17	1		T18	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	14		T101	10		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	14		T95	19		T57	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	2		T92	1		T151	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T10	2		T15	9		T17	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T23	13		T38	5		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T120	11		T93	13		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T102	2		T38	3		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T18	1		T20	6		T100	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T17	1		T63	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T39	8		T129	5		T239	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T137	11		T94	1		T155	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T18	1		T90	1		T92	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T91	9		T39	1		T215	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T11	16		T12	20		T16	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T313	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T291	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T285	13		T278	9		T319	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T22	2		T137	11		T138	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T122	13		T105	6		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T224	9		T172	9		T236	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T120	12		T96	14		T230	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	15		T18	4		T218	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	14		T101	13		T210	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	8		T95	20		T57	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T92	12		T151	11		T215	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T17	14		T91	2		T220	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	4		T104	1		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T120	10		T104	5		T209	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T143	5		T128	18		T244	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T18	14		T20	1		T100	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	12		T100	14		T96	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T39	9		T129	2		T124	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T137	15		T155	1		T96	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T18	11		T92	4		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T39	1		T215	9		T210	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T27	2		T28	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T22	4		T62	1		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T89	1		T97	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T18	5		T38	1		T172	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T14	16		T210	9		T120	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T17	16		T62	1		T95	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T22	2		T101	14		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T10	2		T13	5		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T92	13		T215	7		T137	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	5		T17	15		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T23	1		T102	1		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T120	11		T171	1		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T17	13		T102	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T18	15		T20	5		T100	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T63	1		T215	1		T100	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T39	10		T129	3		T239	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T39	2		T137	16		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T90	1		T92	5		T120	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T91	1		T215	10		T210	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T18	12		T168	16		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T233	1		T280	1		T286	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16464	1			T6	1		T27	2		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T206	1		T213	16		T316	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T22	1		T98	7		T137	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T98	14		T103	9		T122	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T172	10		T236	4		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	12		T120	10		T96	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T95	6		T57	10		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T101	9		T151	10		T53	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T13	6		T15	8		T91	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T215	8		T137	12		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	6		T17	12		T130	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T23	12		T38	2		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T120	10		T171	9		T93	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T122	1		T96	10		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T20	2		T100	11		T93	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	14		T130	12		T53	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T39	7		T129	4		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T137	10		T118	8		T96	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T120	1		T138	16		T103	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T91	8		T215	9		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T168	14		T318	4		T135	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T233	9		T286	12		T320	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T213	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T313	2		T314	1		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T291	12		T273	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T256	1		T285	14		T278	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T22	4		T62	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T89	1		T97	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T62	1		T224	10		T172	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T120	13		T96	15		T230	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	16		T18	5		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	16		T101	14		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	10		T95	22		T57	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T22	2		T92	13		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T10	2		T15	1		T17	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T23	1		T38	7		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T120	11		T93	1		T104	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T102	2		T38	3		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T18	15		T20	5		T100	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	13		T63	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T39	10		T129	3		T239	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T137	16		T94	1		T155	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T18	12		T90	1		T92	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T91	1		T39	2		T215	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16455	1			T6	1		T27	2		T28	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T315	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T291	11		T273	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T285	11		T278	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T22	1		T98	7		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T98	14		T103	9		T122	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T172	10		T236	4		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T120	10		T96	14		T230	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T174	14		T268	3		T111	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	12		T101	9		T53	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	12		T95	17		T57	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T151	10		T215	8		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T15	8		T17	12		T91	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T23	12		T38	2		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	10		T93	12		T228	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T122	1		T271	11		T128	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T20	2		T100	11		T171	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T100	14		T130	12		T96	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T39	7		T129	4		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	10		T96	9		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T120	1		T138	16		T103	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T91	8		T215	9		T118	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21507

1

T6

1

T27

2

T28

1

auto[1]

auto[0]

3533

1

T13

12

T14

12

T15

8