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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.48 98.98 95.69 100.00 100.00 98.18 98.64 90.87


Total test records in report: 906
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T774 /workspace/coverage/default/8.adc_ctrl_filters_interrupt.606857152 Jan 24 07:09:36 PM PST 24 Jan 24 07:26:46 PM PST 24 481230435283 ps
T775 /workspace/coverage/default/30.adc_ctrl_poweron_counter.923731384 Jan 24 07:20:24 PM PST 24 Jan 24 07:20:32 PM PST 24 5016832446 ps
T776 /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1717055121 Jan 24 08:06:48 PM PST 24 Jan 24 08:07:28 PM PST 24 44977056219 ps
T777 /workspace/coverage/default/44.adc_ctrl_fsm_reset.1894454208 Jan 24 07:27:24 PM PST 24 Jan 24 07:31:42 PM PST 24 74704101227 ps
T778 /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1556016822 Jan 24 07:13:20 PM PST 24 Jan 24 07:25:47 PM PST 24 330610709547 ps
T779 /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2884070790 Jan 24 07:26:12 PM PST 24 Jan 24 07:27:32 PM PST 24 35499007541 ps
T319 /workspace/coverage/default/3.adc_ctrl_filters_interrupt.695093185 Jan 24 07:07:51 PM PST 24 Jan 24 07:09:12 PM PST 24 161942247383 ps
T780 /workspace/coverage/default/33.adc_ctrl_clock_gating.3823734312 Jan 24 07:32:35 PM PST 24 Jan 24 07:50:27 PM PST 24 487193794927 ps
T781 /workspace/coverage/default/21.adc_ctrl_poweron_counter.3694996772 Jan 24 07:16:02 PM PST 24 Jan 24 07:16:06 PM PST 24 3746084099 ps
T782 /workspace/coverage/default/34.adc_ctrl_smoke.176749940 Jan 24 07:22:02 PM PST 24 Jan 24 07:22:07 PM PST 24 6191001227 ps
T302 /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2759899425 Jan 24 07:10:53 PM PST 24 Jan 24 07:11:39 PM PST 24 120574438271 ps
T363 /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2597681905 Jan 24 07:07:40 PM PST 24 Jan 24 07:10:39 PM PST 24 46311308191 ps
T321 /workspace/coverage/default/37.adc_ctrl_filters_both.2733292102 Jan 24 07:24:04 PM PST 24 Jan 24 07:36:17 PM PST 24 328004672252 ps
T783 /workspace/coverage/default/1.adc_ctrl_alert_test.3800929200 Jan 24 07:07:41 PM PST 24 Jan 24 07:07:44 PM PST 24 368803582 ps
T784 /workspace/coverage/default/45.adc_ctrl_stress_all.1150318120 Jan 24 07:27:46 PM PST 24 Jan 24 07:31:28 PM PST 24 370841971851 ps
T785 /workspace/coverage/default/14.adc_ctrl_clock_gating.3486156435 Jan 24 07:12:23 PM PST 24 Jan 24 07:15:27 PM PST 24 333685671431 ps
T786 /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3395784744 Jan 24 07:19:42 PM PST 24 Jan 24 07:23:36 PM PST 24 241930535015 ps
T787 /workspace/coverage/default/44.adc_ctrl_alert_test.2795975596 Jan 24 09:29:33 PM PST 24 Jan 24 09:29:35 PM PST 24 300917378 ps
T788 /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4215263836 Jan 24 07:28:07 PM PST 24 Jan 24 07:28:30 PM PST 24 166339250547 ps
T789 /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1744966384 Jan 24 07:08:54 PM PST 24 Jan 24 07:14:52 PM PST 24 160977138987 ps
T790 /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2283542472 Jan 24 07:11:20 PM PST 24 Jan 24 07:14:29 PM PST 24 156826611843 ps
T791 /workspace/coverage/default/35.adc_ctrl_poweron_counter.2392773436 Jan 24 07:23:00 PM PST 24 Jan 24 07:23:07 PM PST 24 4111601849 ps
T792 /workspace/coverage/default/20.adc_ctrl_filters_both.4075737073 Jan 24 07:15:33 PM PST 24 Jan 24 07:18:55 PM PST 24 333114589398 ps
T793 /workspace/coverage/default/45.adc_ctrl_filters_polled.3902995537 Jan 24 09:04:05 PM PST 24 Jan 24 09:06:20 PM PST 24 162320031918 ps
T794 /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2263899165 Jan 24 07:10:55 PM PST 24 Jan 24 07:20:35 PM PST 24 497625653675 ps
T795 /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3327894031 Jan 24 07:43:55 PM PST 24 Jan 24 07:45:49 PM PST 24 164014183370 ps
T294 /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1874060361 Jan 24 07:19:53 PM PST 24 Jan 24 07:25:47 PM PST 24 164162920214 ps
T796 /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2208545371 Jan 24 07:24:16 PM PST 24 Jan 24 07:30:30 PM PST 24 170899627662 ps
T797 /workspace/coverage/default/15.adc_ctrl_filters_both.82690485 Jan 24 07:12:48 PM PST 24 Jan 24 07:19:42 PM PST 24 169154130491 ps
T798 /workspace/coverage/default/41.adc_ctrl_filters_polled.297352886 Jan 24 07:25:40 PM PST 24 Jan 24 07:27:23 PM PST 24 158796055575 ps
T265 /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1335577713 Jan 24 07:22:45 PM PST 24 Jan 24 07:40:56 PM PST 24 493189101908 ps
T799 /workspace/coverage/default/23.adc_ctrl_alert_test.3869176618 Jan 24 07:17:27 PM PST 24 Jan 24 07:17:30 PM PST 24 436847492 ps
T800 /workspace/coverage/default/20.adc_ctrl_poweron_counter.3297392987 Jan 24 07:16:19 PM PST 24 Jan 24 07:16:23 PM PST 24 4218498723 ps
T801 /workspace/coverage/default/34.adc_ctrl_poweron_counter.3387993641 Jan 24 07:22:25 PM PST 24 Jan 24 07:22:28 PM PST 24 2649744848 ps
T802 /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.11007994 Jan 24 07:13:10 PM PST 24 Jan 24 07:24:40 PM PST 24 336290956266 ps
T803 /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4003866205 Jan 24 07:22:46 PM PST 24 Jan 24 07:24:21 PM PST 24 164154730572 ps
T161 /workspace/coverage/default/15.adc_ctrl_filters_polled.1538132592 Jan 24 07:12:37 PM PST 24 Jan 24 07:17:17 PM PST 24 484735537392 ps
T804 /workspace/coverage/default/15.adc_ctrl_smoke.1848570745 Jan 24 07:12:38 PM PST 24 Jan 24 07:12:42 PM PST 24 5807958041 ps
T805 /workspace/coverage/default/49.adc_ctrl_alert_test.1500103876 Jan 24 07:29:17 PM PST 24 Jan 24 07:29:18 PM PST 24 590526000 ps
T806 /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1625088171 Jan 24 07:23:27 PM PST 24 Jan 24 07:24:24 PM PST 24 22625085451 ps
T807 /workspace/coverage/default/9.adc_ctrl_clock_gating.570644526 Jan 24 10:43:02 PM PST 24 Jan 24 10:43:56 PM PST 24 164976203800 ps
T293 /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2834436271 Jan 24 07:58:58 PM PST 24 Jan 24 08:03:14 PM PST 24 108857934123 ps
T808 /workspace/coverage/default/5.adc_ctrl_smoke.3158038962 Jan 24 07:08:34 PM PST 24 Jan 24 07:08:52 PM PST 24 5704574002 ps
T809 /workspace/coverage/default/48.adc_ctrl_alert_test.317202209 Jan 24 07:28:57 PM PST 24 Jan 24 07:29:05 PM PST 24 327314291 ps
T312 /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3488184963 Jan 24 09:09:46 PM PST 24 Jan 24 09:16:50 PM PST 24 329405337916 ps
T810 /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2821087182 Jan 24 07:41:57 PM PST 24 Jan 24 07:51:17 PM PST 24 486462112762 ps
T811 /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1898432734 Jan 24 07:34:28 PM PST 24 Jan 24 07:41:15 PM PST 24 164987050007 ps
T812 /workspace/coverage/default/2.adc_ctrl_alert_test.416069803 Jan 24 07:15:47 PM PST 24 Jan 24 07:15:50 PM PST 24 529845714 ps
T813 /workspace/coverage/default/37.adc_ctrl_poweron_counter.4098733744 Jan 24 08:55:14 PM PST 24 Jan 24 08:55:24 PM PST 24 3642989817 ps
T349 /workspace/coverage/default/46.adc_ctrl_filters_interrupt.288721903 Jan 24 07:27:55 PM PST 24 Jan 24 07:47:11 PM PST 24 495770608011 ps
T814 /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4075600239 Jan 24 07:20:28 PM PST 24 Jan 24 07:20:45 PM PST 24 26478834197 ps
T341 /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3196078028 Jan 24 07:18:44 PM PST 24 Jan 24 07:32:25 PM PST 24 339447973847 ps
T815 /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3861879196 Jan 24 07:12:08 PM PST 24 Jan 24 07:19:50 PM PST 24 358348840713 ps
T816 /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3401707843 Jan 24 07:43:54 PM PST 24 Jan 24 07:44:09 PM PST 24 23891466935 ps
T817 /workspace/coverage/default/36.adc_ctrl_poweron_counter.587871686 Jan 24 07:23:27 PM PST 24 Jan 24 07:23:31 PM PST 24 3878923402 ps
T818 /workspace/coverage/default/14.adc_ctrl_poweron_counter.47186194 Jan 24 07:12:21 PM PST 24 Jan 24 07:12:33 PM PST 24 4494072966 ps
T819 /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3608231003 Jan 24 07:09:08 PM PST 24 Jan 24 07:19:18 PM PST 24 487274413260 ps
T820 /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3586367808 Jan 24 07:26:35 PM PST 24 Jan 24 07:39:06 PM PST 24 329997268347 ps
T821 /workspace/coverage/default/9.adc_ctrl_poweron_counter.2118878316 Jan 24 07:10:08 PM PST 24 Jan 24 07:10:15 PM PST 24 2823335238 ps
T822 /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.735723272 Jan 24 07:22:16 PM PST 24 Jan 24 07:27:11 PM PST 24 494025486033 ps
T823 /workspace/coverage/default/24.adc_ctrl_filters_polled.1233565214 Jan 24 07:17:27 PM PST 24 Jan 24 07:23:56 PM PST 24 332315716357 ps
T824 /workspace/coverage/default/0.adc_ctrl_clock_gating.4043364594 Jan 24 07:07:09 PM PST 24 Jan 24 07:12:53 PM PST 24 163851492563 ps
T825 /workspace/coverage/default/30.adc_ctrl_smoke.2899095955 Jan 24 07:53:07 PM PST 24 Jan 24 07:53:13 PM PST 24 5972492355 ps
T826 /workspace/coverage/default/12.adc_ctrl_alert_test.1990538144 Jan 24 07:11:44 PM PST 24 Jan 24 07:11:47 PM PST 24 501769634 ps
T827 /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1756496153 Jan 24 07:21:19 PM PST 24 Jan 24 07:22:14 PM PST 24 43814957923 ps
T828 /workspace/coverage/default/16.adc_ctrl_poweron_counter.2961140724 Jan 24 07:13:23 PM PST 24 Jan 24 07:13:27 PM PST 24 3780522940 ps
T829 /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2402524941 Jan 24 07:16:40 PM PST 24 Jan 24 07:16:49 PM PST 24 33311559987 ps
T830 /workspace/coverage/default/21.adc_ctrl_filters_both.1136606962 Jan 24 07:16:00 PM PST 24 Jan 24 07:17:39 PM PST 24 169367226080 ps
T831 /workspace/coverage/default/10.adc_ctrl_filters_both.1137108973 Jan 24 07:10:32 PM PST 24 Jan 24 07:12:03 PM PST 24 164833127344 ps
T832 /workspace/coverage/default/9.adc_ctrl_filters_both.3028643240 Jan 24 07:10:12 PM PST 24 Jan 24 07:15:44 PM PST 24 518018249919 ps
T833 /workspace/coverage/default/12.adc_ctrl_smoke.3074753276 Jan 24 08:11:16 PM PST 24 Jan 24 08:11:19 PM PST 24 5761667399 ps
T834 /workspace/coverage/default/40.adc_ctrl_poweron_counter.2629808909 Jan 24 07:25:22 PM PST 24 Jan 24 07:25:37 PM PST 24 2973752609 ps
T835 /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2292614662 Jan 24 07:13:58 PM PST 24 Jan 24 07:14:12 PM PST 24 23935402735 ps
T836 /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3945522351 Jan 24 07:07:45 PM PST 24 Jan 24 07:14:16 PM PST 24 159883156313 ps
T837 /workspace/coverage/default/39.adc_ctrl_alert_test.555625219 Jan 24 07:25:15 PM PST 24 Jan 24 07:25:17 PM PST 24 366332116 ps
T329 /workspace/coverage/default/38.adc_ctrl_clock_gating.2662201845 Jan 24 07:24:24 PM PST 24 Jan 24 07:32:13 PM PST 24 494614415012 ps
T838 /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2585878220 Jan 24 07:11:41 PM PST 24 Jan 24 07:13:14 PM PST 24 161834338926 ps
T316 /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1814399855 Jan 24 07:29:05 PM PST 24 Jan 24 07:48:29 PM PST 24 494743119893 ps
T839 /workspace/coverage/default/47.adc_ctrl_filters_polled.3293632400 Jan 24 07:28:10 PM PST 24 Jan 24 07:34:29 PM PST 24 328951774017 ps
T840 /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3747980834 Jan 24 07:36:43 PM PST 24 Jan 24 07:38:07 PM PST 24 165915469696 ps
T841 /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2678159733 Jan 24 07:27:23 PM PST 24 Jan 24 07:27:55 PM PST 24 43549060291 ps
T842 /workspace/coverage/default/35.adc_ctrl_clock_gating.2077876293 Jan 24 07:22:58 PM PST 24 Jan 24 07:29:20 PM PST 24 168889651104 ps
T843 /workspace/coverage/default/6.adc_ctrl_stress_all.689719564 Jan 24 07:08:59 PM PST 24 Jan 24 07:28:59 PM PST 24 329029430253 ps
T844 /workspace/coverage/default/11.adc_ctrl_fsm_reset.4119391432 Jan 24 07:11:07 PM PST 24 Jan 24 07:18:09 PM PST 24 95632411978 ps
T845 /workspace/coverage/default/37.adc_ctrl_alert_test.864099568 Jan 24 08:01:26 PM PST 24 Jan 24 08:01:28 PM PST 24 313213301 ps
T846 /workspace/coverage/default/25.adc_ctrl_fsm_reset.3000528133 Jan 24 07:18:34 PM PST 24 Jan 24 07:27:29 PM PST 24 126937898816 ps
T847 /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3169843179 Jan 24 07:55:10 PM PST 24 Jan 24 07:56:39 PM PST 24 334558069090 ps
T848 /workspace/coverage/default/48.adc_ctrl_smoke.2302201183 Jan 24 08:09:00 PM PST 24 Jan 24 08:09:17 PM PST 24 5816581632 ps
T279 /workspace/coverage/default/35.adc_ctrl_stress_all.3479964803 Jan 24 07:23:14 PM PST 24 Jan 24 07:32:30 PM PST 24 289064034222 ps
T849 /workspace/coverage/default/6.adc_ctrl_filters_polled.643678674 Jan 24 09:00:48 PM PST 24 Jan 24 09:04:10 PM PST 24 163967402352 ps
T850 /workspace/coverage/default/46.adc_ctrl_lowpower_counter.639905965 Jan 24 07:28:02 PM PST 24 Jan 24 07:28:22 PM PST 24 37413618043 ps
T225 /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1382759010 Jan 24 07:53:53 PM PST 24 Jan 24 07:54:59 PM PST 24 77828187612 ps
T148 /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3820549346 Jan 24 07:36:21 PM PST 24 Jan 24 07:41:09 PM PST 24 449912077394 ps
T851 /workspace/coverage/default/39.adc_ctrl_clock_gating.854395992 Jan 24 07:34:03 PM PST 24 Jan 24 07:35:38 PM PST 24 167204993613 ps
T852 /workspace/coverage/default/12.adc_ctrl_poweron_counter.889699272 Jan 24 07:11:27 PM PST 24 Jan 24 07:11:45 PM PST 24 3872882242 ps
T853 /workspace/coverage/default/33.adc_ctrl_smoke.1230162598 Jan 24 07:21:32 PM PST 24 Jan 24 07:21:37 PM PST 24 5872953430 ps
T854 /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1458037281 Jan 24 07:37:49 PM PST 24 Jan 24 07:40:53 PM PST 24 160673339253 ps
T855 /workspace/coverage/default/48.adc_ctrl_fsm_reset.2216893672 Jan 24 07:28:47 PM PST 24 Jan 24 07:34:49 PM PST 24 94860506562 ps
T226 /workspace/coverage/default/32.adc_ctrl_stress_all.730463120 Jan 24 07:21:24 PM PST 24 Jan 24 07:29:47 PM PST 24 438471011979 ps
T247 /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2543662445 Jan 24 07:15:39 PM PST 24 Jan 24 07:18:09 PM PST 24 320753824160 ps
T83 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.883151158 Jan 24 02:51:22 PM PST 24 Jan 24 02:51:31 PM PST 24 554358139 ps
T856 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3680208848 Jan 24 02:51:20 PM PST 24 Jan 24 02:51:29 PM PST 24 369961452 ps
T356 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4047950708 Jan 24 02:51:05 PM PST 24 Jan 24 02:51:40 PM PST 24 8251490869 ps
T857 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.669312535 Jan 24 02:52:05 PM PST 24 Jan 24 02:52:10 PM PST 24 448426114 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1399031689 Jan 24 02:50:58 PM PST 24 Jan 24 02:51:13 PM PST 24 460190526 ps
T859 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3095789115 Jan 24 02:50:57 PM PST 24 Jan 24 02:51:18 PM PST 24 2127217347 ps
T860 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1320937815 Jan 24 02:50:37 PM PST 24 Jan 24 02:50:48 PM PST 24 425966964 ps
T359 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2592191343 Jan 24 02:51:24 PM PST 24 Jan 24 02:51:41 PM PST 24 8590951204 ps
T861 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.842694178 Jan 24 02:51:19 PM PST 24 Jan 24 02:51:28 PM PST 24 2847780149 ps
T862 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1224936505 Jan 24 02:51:46 PM PST 24 Jan 24 02:51:55 PM PST 24 316268740 ps
T863 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2113158607 Jan 24 02:52:02 PM PST 24 Jan 24 02:52:06 PM PST 24 590737295 ps
T864 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3723751187 Jan 24 02:52:26 PM PST 24 Jan 24 02:52:39 PM PST 24 432150318 ps
T865 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2701249187 Jan 24 02:52:05 PM PST 24 Jan 24 02:52:12 PM PST 24 461986344 ps
T866 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2744120138 Jan 24 02:52:21 PM PST 24 Jan 24 02:52:29 PM PST 24 477856671 ps
T867 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.759300463 Jan 24 02:51:47 PM PST 24 Jan 24 02:51:56 PM PST 24 507178288 ps
T360 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1700880823 Jan 24 02:51:51 PM PST 24 Jan 24 02:52:22 PM PST 24 8530545895 ps
T868 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.782920000 Jan 24 02:52:05 PM PST 24 Jan 24 02:52:11 PM PST 24 439068278 ps
T869 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1420657036 Jan 24 02:51:21 PM PST 24 Jan 24 02:51:30 PM PST 24 542391785 ps
T870 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.846211198 Jan 24 02:51:22 PM PST 24 Jan 24 02:51:37 PM PST 24 8590481833 ps
T871 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3855554740 Jan 24 02:56:35 PM PST 24 Jan 24 02:56:38 PM PST 24 516117641 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1397211105 Jan 24 02:51:54 PM PST 24 Jan 24 02:52:07 PM PST 24 4271259048 ps
T873 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.904194859 Jan 24 02:51:09 PM PST 24 Jan 24 02:51:27 PM PST 24 2052353307 ps
T357 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1578134369 Jan 24 02:50:47 PM PST 24 Jan 24 02:51:11 PM PST 24 4252419873 ps
T874 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1471095781 Jan 24 02:51:24 PM PST 24 Jan 24 02:51:37 PM PST 24 2246550864 ps
T875 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2982981510 Jan 24 02:52:20 PM PST 24 Jan 24 02:52:27 PM PST 24 333490175 ps
T876 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1037267906 Jan 24 02:51:20 PM PST 24 Jan 24 02:51:29 PM PST 24 478997976 ps
T877 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2712958532 Jan 24 02:51:41 PM PST 24 Jan 24 02:51:54 PM PST 24 435374859 ps
T878 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3642078440 Jan 24 02:51:32 PM PST 24 Jan 24 02:51:47 PM PST 24 485131598 ps
T879 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4257369160 Jan 24 02:51:32 PM PST 24 Jan 24 02:52:06 PM PST 24 7872039785 ps
T880 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1616056209 Jan 24 02:52:24 PM PST 24 Jan 24 02:52:50 PM PST 24 8105022771 ps
T881 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2610089251 Jan 24 02:56:00 PM PST 24 Jan 24 02:56:09 PM PST 24 1982628620 ps
T882 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.362492254 Jan 24 02:52:17 PM PST 24 Jan 24 02:52:23 PM PST 24 423936251 ps
T883 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1426245097 Jan 24 02:50:40 PM PST 24 Jan 24 02:50:51 PM PST 24 390946948 ps
T884 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2628124746 Jan 24 02:51:25 PM PST 24 Jan 24 02:51:39 PM PST 24 3851141130 ps
T885 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.576390886 Jan 24 02:52:02 PM PST 24 Jan 24 02:52:07 PM PST 24 402195959 ps
T886 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1178659673 Jan 24 02:51:06 PM PST 24 Jan 24 02:51:21 PM PST 24 355684652 ps
T887 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.331314167 Jan 24 02:51:32 PM PST 24 Jan 24 02:51:55 PM PST 24 3973400858 ps
T888 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3739023325 Jan 24 02:51:32 PM PST 24 Jan 24 02:51:45 PM PST 24 594900527 ps
T889 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1615412236 Jan 24 02:51:22 PM PST 24 Jan 24 02:51:41 PM PST 24 7767461422 ps
T890 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.509695835 Jan 24 02:50:39 PM PST 24 Jan 24 02:50:51 PM PST 24 679671653 ps
T891 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3350163852 Jan 24 04:50:31 PM PST 24 Jan 24 04:50:34 PM PST 24 502931779 ps
T892 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.350107171 Jan 24 02:51:48 PM PST 24 Jan 24 02:51:59 PM PST 24 4103520095 ps
T893 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1927067964 Jan 24 02:51:55 PM PST 24 Jan 24 02:52:03 PM PST 24 397957709 ps
T894 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2103872838 Jan 24 02:52:18 PM PST 24 Jan 24 02:52:25 PM PST 24 494785681 ps
T895 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.326797512 Jan 24 02:51:45 PM PST 24 Jan 24 02:51:54 PM PST 24 456355530 ps
T896 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3381836738 Jan 24 02:51:08 PM PST 24 Jan 24 02:51:24 PM PST 24 2271554802 ps
T897 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1358786060 Jan 24 02:51:10 PM PST 24 Jan 24 02:51:25 PM PST 24 372728007 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3375485569 Jan 24 02:50:49 PM PST 24 Jan 24 02:51:13 PM PST 24 8650339477 ps
T899 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3182397543 Jan 24 02:52:37 PM PST 24 Jan 24 02:52:50 PM PST 24 283767513 ps
T900 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.993675059 Jan 24 02:51:25 PM PST 24 Jan 24 02:51:37 PM PST 24 937831769 ps
T901 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1752063247 Jan 24 02:51:32 PM PST 24 Jan 24 02:51:45 PM PST 24 353153723 ps
T902 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4033733085 Jan 24 02:51:32 PM PST 24 Jan 24 02:51:45 PM PST 24 370788435 ps
T903 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.73100286 Jan 24 02:52:05 PM PST 24 Jan 24 02:52:13 PM PST 24 4803537315 ps
T904 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.44986035 Jan 24 02:51:06 PM PST 24 Jan 24 02:51:21 PM PST 24 1027295089 ps
T905 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3557393287 Jan 24 02:52:27 PM PST 24 Jan 24 02:52:40 PM PST 24 430510945 ps
T906 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3507448545 Jan 24 02:51:23 PM PST 24 Jan 24 02:51:31 PM PST 24 343770330 ps

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.964398286
Short name T5
Test name
Test status
Simulation time 530700111 ps
CPU time 1.45 seconds
Started Jan 24 02:51:19 PM PST 24
Finished Jan 24 02:51:29 PM PST 24
Peak memory 200880 kb
Host smart-500fdaf4-019b-4699-87f2-25afbdf27092
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964398286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.964398286
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.817259512
Short name T33
Test name
Test status
Simulation time 4268097349 ps
CPU time 3.97 seconds
Started Jan 24 02:51:44 PM PST 24
Finished Jan 24 02:51:57 PM PST 24
Peak memory 200800 kb
Host smart-4485f160-bd47-40ea-af1c-ba59702375b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817259512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.817259512
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1279114391
Short name T17
Test name
Test status
Simulation time 493130594374 ps
CPU time 571.84 seconds
Started Jan 24 07:35:54 PM PST 24
Finished Jan 24 07:45:29 PM PST 24
Peak memory 201188 kb
Host smart-b1491c13-6382-4129-9e08-00d8830fbbfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279114391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1279114391
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1844551532
Short name T137
Test name
Test status
Simulation time 486274165454 ps
CPU time 293.18 seconds
Started Jan 24 07:35:03 PM PST 24
Finished Jan 24 07:40:06 PM PST 24
Peak memory 201276 kb
Host smart-60b31e3d-1454-47d3-b8e8-978e26c4dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844551532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1844551532
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1130905302
Short name T13
Test name
Test status
Simulation time 331259497749 ps
CPU time 792.84 seconds
Started Jan 24 07:16:40 PM PST 24
Finished Jan 24 07:29:53 PM PST 24
Peak memory 201284 kb
Host smart-b02daa4f-6c27-42b7-85f0-aa542aece4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130905302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1130905302
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1881538402
Short name T95
Test name
Test status
Simulation time 486314845130 ps
CPU time 140.77 seconds
Started Jan 24 07:21:47 PM PST 24
Finished Jan 24 07:24:09 PM PST 24
Peak memory 201140 kb
Host smart-306beb51-f950-45fa-8c64-0e2a17c6862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881538402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1881538402
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3529109417
Short name T4
Test name
Test status
Simulation time 384288708 ps
CPU time 1.04 seconds
Started Jan 24 02:52:27 PM PST 24
Finished Jan 24 02:52:39 PM PST 24
Peak memory 200528 kb
Host smart-8322fa06-797e-4e15-beda-9c9efadf1d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529109417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3529109417
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1163072167
Short name T120
Test name
Test status
Simulation time 501089772144 ps
CPU time 1028.9 seconds
Started Jan 24 07:10:31 PM PST 24
Finished Jan 24 07:27:41 PM PST 24
Peak memory 201148 kb
Host smart-3dd06811-00a9-4529-8aa9-f3130459b209
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163072167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1163072167
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1931509109
Short name T6
Test name
Test status
Simulation time 547862983 ps
CPU time 0.93 seconds
Started Jan 24 02:51:47 PM PST 24
Finished Jan 24 02:51:55 PM PST 24
Peak memory 200476 kb
Host smart-57661197-2d70-48c3-a3cc-21ce0813b256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931509109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1931509109
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3476022042
Short name T38
Test name
Test status
Simulation time 195810377897 ps
CPU time 319.31 seconds
Started Jan 24 07:16:40 PM PST 24
Finished Jan 24 07:22:00 PM PST 24
Peak memory 209516 kb
Host smart-5ee24b1a-3a12-470b-9fd9-4b0bdd16b3df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476022042 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3476022042
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3742326902
Short name T215
Test name
Test status
Simulation time 492415256609 ps
CPU time 192.48 seconds
Started Jan 24 07:09:39 PM PST 24
Finished Jan 24 07:12:53 PM PST 24
Peak memory 201216 kb
Host smart-9b531867-64f5-4e87-81a8-5303ab22d369
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742326902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3742326902
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2782057448
Short name T133
Test name
Test status
Simulation time 503308302499 ps
CPU time 213.94 seconds
Started Jan 24 07:20:45 PM PST 24
Finished Jan 24 07:24:23 PM PST 24
Peak memory 201192 kb
Host smart-23868d72-c903-428a-993f-5e9c3284a5b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782057448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2782057448
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3814861932
Short name T174
Test name
Test status
Simulation time 847478177409 ps
CPU time 634.19 seconds
Started Jan 24 07:12:32 PM PST 24
Finished Jan 24 07:23:07 PM PST 24
Peak memory 201680 kb
Host smart-2c2f8f0b-79e3-451e-b3d6-7ba8d66c7b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814861932 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3814861932
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3860793604
Short name T103
Test name
Test status
Simulation time 492291239648 ps
CPU time 1095.45 seconds
Started Jan 24 07:28:41 PM PST 24
Finished Jan 24 07:46:58 PM PST 24
Peak memory 201064 kb
Host smart-a054a769-21c8-4945-8d55-debdb67fcf32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860793604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3860793604
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.397712502
Short name T100
Test name
Test status
Simulation time 324574023195 ps
CPU time 95.84 seconds
Started Jan 24 07:09:08 PM PST 24
Finished Jan 24 07:10:45 PM PST 24
Peak memory 201188 kb
Host smart-7d48cd75-b899-4eb4-af2d-82af1c996528
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397712502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.397712502
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3216561648
Short name T219
Test name
Test status
Simulation time 492755424134 ps
CPU time 260.35 seconds
Started Jan 24 07:22:47 PM PST 24
Finished Jan 24 07:27:12 PM PST 24
Peak memory 201172 kb
Host smart-7d1d6db6-ed43-4caf-b27e-e9901736a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216561648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3216561648
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.207065576
Short name T91
Test name
Test status
Simulation time 330021489666 ps
CPU time 70.19 seconds
Started Jan 24 07:15:39 PM PST 24
Finished Jan 24 07:16:50 PM PST 24
Peak memory 201056 kb
Host smart-0d26e8dc-0235-42b0-bf68-199955cf1d3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207065576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.207065576
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1071147433
Short name T128
Test name
Test status
Simulation time 497273843363 ps
CPU time 204.81 seconds
Started Jan 24 07:08:38 PM PST 24
Finished Jan 24 07:12:04 PM PST 24
Peak memory 201232 kb
Host smart-15c9d1ba-a0df-4d13-b587-08ede038ed7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071147433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1071147433
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.4184565563
Short name T192
Test name
Test status
Simulation time 315769063078 ps
CPU time 549.26 seconds
Started Jan 24 07:42:57 PM PST 24
Finished Jan 24 07:52:07 PM PST 24
Peak memory 210128 kb
Host smart-1591c1ff-866b-4f87-9dfd-31517acd06e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184565563 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.4184565563
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3915579047
Short name T194
Test name
Test status
Simulation time 123241352234 ps
CPU time 718.3 seconds
Started Jan 24 08:25:32 PM PST 24
Finished Jan 24 08:37:31 PM PST 24
Peak memory 201548 kb
Host smart-128eab1c-6f00-42a5-9f6b-8acd208cd834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915579047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3915579047
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3584443858
Short name T122
Test name
Test status
Simulation time 550944746375 ps
CPU time 1069.87 seconds
Started Jan 24 07:28:02 PM PST 24
Finished Jan 24 07:45:53 PM PST 24
Peak memory 201164 kb
Host smart-423711b1-c972-4111-9165-3f92aba7a16a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584443858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3584443858
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3340409042
Short name T39
Test name
Test status
Simulation time 333295320626 ps
CPU time 370.68 seconds
Started Jan 24 07:08:54 PM PST 24
Finished Jan 24 07:15:07 PM PST 24
Peak memory 201060 kb
Host smart-faf1652d-c8e9-4011-819d-383b3c4fab09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340409042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3340409042
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3647042994
Short name T252
Test name
Test status
Simulation time 483678345394 ps
CPU time 1137.39 seconds
Started Jan 24 08:01:23 PM PST 24
Finished Jan 24 08:20:21 PM PST 24
Peak memory 201188 kb
Host smart-3d080ee9-21ba-4b28-9905-9ed33c22788e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647042994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3647042994
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2712983012
Short name T29
Test name
Test status
Simulation time 26186209643 ps
CPU time 36.52 seconds
Started Jan 24 02:50:45 PM PST 24
Finished Jan 24 02:51:39 PM PST 24
Peak memory 200740 kb
Host smart-44ef7ad8-88e0-4d2b-bcee-dbed41c81d8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712983012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2712983012
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3288021527
Short name T49
Test name
Test status
Simulation time 4051532140 ps
CPU time 10.86 seconds
Started Jan 24 07:07:41 PM PST 24
Finished Jan 24 07:07:53 PM PST 24
Peak memory 216388 kb
Host smart-88f5aa1a-3bb4-4197-bb3e-c5d3598caa42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288021527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3288021527
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.130655084
Short name T126
Test name
Test status
Simulation time 499881054935 ps
CPU time 290.17 seconds
Started Jan 24 07:26:07 PM PST 24
Finished Jan 24 07:30:58 PM PST 24
Peak memory 201084 kb
Host smart-b67c0668-4370-4e9c-86f0-daab956f52ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130655084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.130655084
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3561148475
Short name T22
Test name
Test status
Simulation time 36133507282 ps
CPU time 52.32 seconds
Started Jan 24 07:21:29 PM PST 24
Finished Jan 24 07:22:22 PM PST 24
Peak memory 209796 kb
Host smart-28353120-71d3-430a-986b-14f8671090b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561148475 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3561148475
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.758880972
Short name T14
Test name
Test status
Simulation time 337522906024 ps
CPU time 109.23 seconds
Started Jan 24 07:19:31 PM PST 24
Finished Jan 24 07:21:21 PM PST 24
Peak memory 201064 kb
Host smart-556e1790-8f18-4868-a4d1-83e4a236a21d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758880972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.758880972
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1315243442
Short name T213
Test name
Test status
Simulation time 500386923907 ps
CPU time 624.67 seconds
Started Jan 24 08:24:24 PM PST 24
Finished Jan 24 08:34:53 PM PST 24
Peak memory 201276 kb
Host smart-abbc4ffc-5aa2-4fd9-bcd2-88ff84887039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315243442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1315243442
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2023938623
Short name T68
Test name
Test status
Simulation time 658596138 ps
CPU time 2.24 seconds
Started Jan 24 02:51:19 PM PST 24
Finished Jan 24 02:51:29 PM PST 24
Peak memory 200812 kb
Host smart-264ec44a-9b20-4492-a893-37ef57ec64a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023938623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2023938623
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.321432633
Short name T278
Test name
Test status
Simulation time 487739523511 ps
CPU time 324.48 seconds
Started Jan 24 07:18:50 PM PST 24
Finished Jan 24 07:24:15 PM PST 24
Peak memory 201208 kb
Host smart-cf362045-bfcd-47c9-a447-5044cacfd884
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321432633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.321432633
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.272222336
Short name T99
Test name
Test status
Simulation time 490038464775 ps
CPU time 1179.07 seconds
Started Jan 24 07:16:18 PM PST 24
Finished Jan 24 07:35:58 PM PST 24
Peak memory 201264 kb
Host smart-1843cb98-0034-498b-8232-f9bc82011d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272222336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.272222336
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4293132496
Short name T18
Test name
Test status
Simulation time 498123486121 ps
CPU time 1157.26 seconds
Started Jan 24 07:21:10 PM PST 24
Finished Jan 24 07:40:29 PM PST 24
Peak memory 201220 kb
Host smart-a24eab2e-ab39-4bf9-85b3-88069c45703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293132496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4293132496
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2532980625
Short name T209
Test name
Test status
Simulation time 179328434341 ps
CPU time 428.03 seconds
Started Jan 24 07:07:30 PM PST 24
Finished Jan 24 07:14:40 PM PST 24
Peak memory 201220 kb
Host smart-b544f6bd-c466-440c-885c-b27d1be5867e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532980625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2532980625
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1656287107
Short name T301
Test name
Test status
Simulation time 400113228297 ps
CPU time 458.49 seconds
Started Jan 24 07:45:24 PM PST 24
Finished Jan 24 07:53:10 PM PST 24
Peak memory 211640 kb
Host smart-7691a4c2-dd6b-41b7-ac33-89c8f3d468e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656287107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1656287107
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2316278848
Short name T246
Test name
Test status
Simulation time 497053929673 ps
CPU time 629.87 seconds
Started Jan 24 07:28:08 PM PST 24
Finished Jan 24 07:38:38 PM PST 24
Peak memory 201140 kb
Host smart-21c524af-7147-4ef5-9437-ace3f30a564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316278848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2316278848
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1805792524
Short name T288
Test name
Test status
Simulation time 322826506055 ps
CPU time 792.42 seconds
Started Jan 24 07:46:18 PM PST 24
Finished Jan 24 07:59:32 PM PST 24
Peak memory 201312 kb
Host smart-731fbfed-5979-43b1-b2d4-3c395a390d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805792524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1805792524
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.800323812
Short name T56
Test name
Test status
Simulation time 279449189633 ps
CPU time 236.04 seconds
Started Jan 24 07:09:30 PM PST 24
Finished Jan 24 07:13:28 PM PST 24
Peak memory 209768 kb
Host smart-cc310840-3a27-4d69-a04e-3a9e0e45f7ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800323812 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.800323812
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2946709114
Short name T257
Test name
Test status
Simulation time 336167567033 ps
CPU time 384.32 seconds
Started Jan 24 07:23:22 PM PST 24
Finished Jan 24 07:29:49 PM PST 24
Peak memory 201164 kb
Host smart-bcd8cd2c-c17a-4178-8485-28a62cb2a8a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946709114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2946709114
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.652976173
Short name T273
Test name
Test status
Simulation time 334456476926 ps
CPU time 739.48 seconds
Started Jan 24 08:29:22 PM PST 24
Finished Jan 24 08:41:43 PM PST 24
Peak memory 201208 kb
Host smart-8c428e33-a590-47b6-b060-959e48896670
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652976173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.652976173
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2037777730
Short name T286
Test name
Test status
Simulation time 506455578474 ps
CPU time 607.46 seconds
Started Jan 24 07:09:40 PM PST 24
Finished Jan 24 07:19:49 PM PST 24
Peak memory 201188 kb
Host smart-5dc0b60b-a9a2-4035-8c4f-31712d870eb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037777730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2037777730
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2662201845
Short name T329
Test name
Test status
Simulation time 494614415012 ps
CPU time 467.85 seconds
Started Jan 24 07:24:24 PM PST 24
Finished Jan 24 07:32:13 PM PST 24
Peak memory 201228 kb
Host smart-0c443568-f8ae-4b1e-a5a7-da65f8067737
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662201845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2662201845
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2859616798
Short name T104
Test name
Test status
Simulation time 493413764011 ps
CPU time 203.46 seconds
Started Jan 24 07:16:26 PM PST 24
Finished Jan 24 07:19:50 PM PST 24
Peak memory 201216 kb
Host smart-4814398b-d05b-4f58-97cd-8dee0c2f0d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859616798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2859616798
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3221127559
Short name T242
Test name
Test status
Simulation time 492103250883 ps
CPU time 154.74 seconds
Started Jan 24 07:30:52 PM PST 24
Finished Jan 24 07:33:27 PM PST 24
Peak memory 201160 kb
Host smart-a987bd00-8631-4f8e-a4f5-81f61b853664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221127559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3221127559
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3428355918
Short name T138
Test name
Test status
Simulation time 327535902166 ps
CPU time 402.7 seconds
Started Jan 24 07:39:26 PM PST 24
Finished Jan 24 07:46:10 PM PST 24
Peak memory 201268 kb
Host smart-41c1e598-091e-4a10-bb03-759654078885
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428355918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3428355918
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3208430194
Short name T114
Test name
Test status
Simulation time 172597461525 ps
CPU time 107.74 seconds
Started Jan 24 07:08:42 PM PST 24
Finished Jan 24 07:10:31 PM PST 24
Peak memory 201112 kb
Host smart-2af46545-4e23-4405-a4bc-583197558b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208430194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3208430194
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.311359772
Short name T335
Test name
Test status
Simulation time 330046448374 ps
CPU time 717.73 seconds
Started Jan 24 07:12:01 PM PST 24
Finished Jan 24 07:24:01 PM PST 24
Peak memory 201236 kb
Host smart-f84fc6f7-b68a-41c3-ab11-d25cec42713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311359772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.311359772
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3374526142
Short name T264
Test name
Test status
Simulation time 603985772461 ps
CPU time 382.85 seconds
Started Jan 24 07:21:53 PM PST 24
Finished Jan 24 07:28:16 PM PST 24
Peak memory 209820 kb
Host smart-16c5828a-e7e8-4495-9b7c-f463df45e5e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374526142 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3374526142
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3593075406
Short name T315
Test name
Test status
Simulation time 504404297721 ps
CPU time 1070.26 seconds
Started Jan 24 07:23:21 PM PST 24
Finished Jan 24 07:41:15 PM PST 24
Peak memory 201152 kb
Host smart-2d14d694-233f-4882-8639-bc93b07b5ffa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593075406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3593075406
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2693260871
Short name T307
Test name
Test status
Simulation time 241558855928 ps
CPU time 270.55 seconds
Started Jan 24 07:12:56 PM PST 24
Finished Jan 24 07:17:28 PM PST 24
Peak memory 209728 kb
Host smart-49eaa2f4-d8ac-4786-a3e0-d7ef06c4378a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693260871 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2693260871
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3578147277
Short name T212
Test name
Test status
Simulation time 250712781544 ps
CPU time 434.2 seconds
Started Jan 24 07:14:04 PM PST 24
Finished Jan 24 07:21:22 PM PST 24
Peak memory 209816 kb
Host smart-24dff51c-4c76-4996-887d-862b5dc3787d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578147277 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3578147277
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2319033070
Short name T59
Test name
Test status
Simulation time 156844503622 ps
CPU time 171.77 seconds
Started Jan 24 07:29:16 PM PST 24
Finished Jan 24 07:32:09 PM PST 24
Peak memory 210084 kb
Host smart-a7896767-d3b5-4ec5-8cd3-d68033d94a11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319033070 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2319033070
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1697286058
Short name T130
Test name
Test status
Simulation time 322693864220 ps
CPU time 690.34 seconds
Started Jan 24 07:07:05 PM PST 24
Finished Jan 24 07:18:37 PM PST 24
Peak memory 201244 kb
Host smart-1697d9d6-224c-4ca8-a944-0ba866954eb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697286058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1697286058
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.194872061
Short name T150
Test name
Test status
Simulation time 165823437088 ps
CPU time 199.99 seconds
Started Jan 24 07:11:25 PM PST 24
Finished Jan 24 07:14:54 PM PST 24
Peak memory 201160 kb
Host smart-84c6916e-e09d-43c7-8b14-ae80b0370c21
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194872061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.194872061
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2362358980
Short name T206
Test name
Test status
Simulation time 329756222005 ps
CPU time 702.07 seconds
Started Jan 24 07:07:45 PM PST 24
Finished Jan 24 07:19:29 PM PST 24
Peak memory 201240 kb
Host smart-19548e87-1986-400d-8115-88caeb755cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362358980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2362358980
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2543662445
Short name T247
Test name
Test status
Simulation time 320753824160 ps
CPU time 148.48 seconds
Started Jan 24 07:15:39 PM PST 24
Finished Jan 24 07:18:09 PM PST 24
Peak memory 209420 kb
Host smart-db0f2c0d-41f8-4280-b9c4-47898e7734c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543662445 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2543662445
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2834436271
Short name T293
Test name
Test status
Simulation time 108857934123 ps
CPU time 255.47 seconds
Started Jan 24 07:58:58 PM PST 24
Finished Jan 24 08:03:14 PM PST 24
Peak memory 209836 kb
Host smart-d507c166-f66b-4aac-82be-ecb36c3d6809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834436271 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2834436271
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4080466329
Short name T466
Test name
Test status
Simulation time 347810692 ps
CPU time 1.5 seconds
Started Jan 24 07:12:32 PM PST 24
Finished Jan 24 07:12:34 PM PST 24
Peak memory 200904 kb
Host smart-7d30eff7-d0d2-4caa-9299-06ad5ae4ccc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080466329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4080466329
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4047950708
Short name T356
Test name
Test status
Simulation time 8251490869 ps
CPU time 20.47 seconds
Started Jan 24 02:51:05 PM PST 24
Finished Jan 24 02:51:40 PM PST 24
Peak memory 200740 kb
Host smart-4e9fb2a5-6604-4018-a804-b8c54a9ebe0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047950708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4047950708
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1169744943
Short name T187
Test name
Test status
Simulation time 390060061 ps
CPU time 1.46 seconds
Started Jan 24 02:52:18 PM PST 24
Finished Jan 24 02:52:26 PM PST 24
Peak memory 200472 kb
Host smart-b5a2d40f-a21d-4348-be26-d7d346a19838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169744943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1169744943
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3846308888
Short name T231
Test name
Test status
Simulation time 325099613109 ps
CPU time 750.48 seconds
Started Jan 24 07:11:23 PM PST 24
Finished Jan 24 07:24:03 PM PST 24
Peak memory 201236 kb
Host smart-7769f4d4-04cd-4b63-a6b1-daed29c2e1ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846308888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3846308888
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.695093185
Short name T319
Test name
Test status
Simulation time 161942247383 ps
CPU time 79.46 seconds
Started Jan 24 07:07:51 PM PST 24
Finished Jan 24 07:09:12 PM PST 24
Peak memory 201088 kb
Host smart-ee210fda-60b4-4911-ac7d-16a028fceada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695093185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.695093185
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.349120092
Short name T158
Test name
Test status
Simulation time 491166714502 ps
CPU time 92.32 seconds
Started Jan 24 08:35:50 PM PST 24
Finished Jan 24 08:37:23 PM PST 24
Peak memory 201252 kb
Host smart-0a051ede-061f-4a6b-9166-9682dd9d0843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349120092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.349120092
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1421176542
Short name T144
Test name
Test status
Simulation time 486594094264 ps
CPU time 341.12 seconds
Started Jan 24 07:24:46 PM PST 24
Finished Jan 24 07:30:28 PM PST 24
Peak memory 201132 kb
Host smart-6629d1eb-f188-4ae1-b8d2-35d1470ed899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421176542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1421176542
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2249043296
Short name T277
Test name
Test status
Simulation time 302351290772 ps
CPU time 153.85 seconds
Started Jan 24 07:27:35 PM PST 24
Finished Jan 24 07:30:09 PM PST 24
Peak memory 209484 kb
Host smart-7cce088e-676d-47aa-bd44-46875a47b8d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249043296 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2249043296
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.51030307
Short name T261
Test name
Test status
Simulation time 162582345198 ps
CPU time 366.95 seconds
Started Jan 24 07:07:02 PM PST 24
Finished Jan 24 07:13:11 PM PST 24
Peak memory 201168 kb
Host smart-a6a072e6-25a9-4b3c-829e-777ba52a311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51030307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.51030307
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1418461168
Short name T300
Test name
Test status
Simulation time 500092623251 ps
CPU time 297.74 seconds
Started Jan 24 07:56:33 PM PST 24
Finished Jan 24 08:01:32 PM PST 24
Peak memory 201252 kb
Host smart-b0f810ae-6b9b-4d31-a58f-dc68f6b4e576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418461168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1418461168
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.105385421
Short name T361
Test name
Test status
Simulation time 81386640727 ps
CPU time 415.14 seconds
Started Jan 24 07:12:32 PM PST 24
Finished Jan 24 07:19:27 PM PST 24
Peak memory 201552 kb
Host smart-98476545-2d17-416f-b930-9ab5fc8a502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105385421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.105385421
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.90533672
Short name T244
Test name
Test status
Simulation time 662572210417 ps
CPU time 183.39 seconds
Started Jan 24 07:14:05 PM PST 24
Finished Jan 24 07:17:12 PM PST 24
Peak memory 201232 kb
Host smart-16866000-ac83-449d-9e6c-16007a835884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90533672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.90533672
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1643494348
Short name T237
Test name
Test status
Simulation time 485336600381 ps
CPU time 1152.57 seconds
Started Jan 24 07:15:06 PM PST 24
Finished Jan 24 07:34:20 PM PST 24
Peak memory 201208 kb
Host smart-75f7eab5-cbef-4076-931b-bcccf43b85fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643494348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1643494348
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2728016562
Short name T308
Test name
Test status
Simulation time 326138710165 ps
CPU time 378.73 seconds
Started Jan 24 07:45:16 PM PST 24
Finished Jan 24 07:51:36 PM PST 24
Peak memory 201248 kb
Host smart-4b6197eb-b26e-4b33-a247-0b2ecdb1a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728016562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2728016562
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1586188513
Short name T200
Test name
Test status
Simulation time 100415740290 ps
CPU time 571.92 seconds
Started Jan 24 07:17:22 PM PST 24
Finished Jan 24 07:26:56 PM PST 24
Peak memory 201484 kb
Host smart-a37c2fe7-6c1b-4734-836d-413b52b07d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586188513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1586188513
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1704782485
Short name T241
Test name
Test status
Simulation time 500212226734 ps
CPU time 239.28 seconds
Started Jan 24 07:19:58 PM PST 24
Finished Jan 24 07:23:59 PM PST 24
Peak memory 201104 kb
Host smart-c0be61cb-7042-4850-9ed9-8f1a7e473698
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704782485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1704782485
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2188031067
Short name T283
Test name
Test status
Simulation time 165197840903 ps
CPU time 115.91 seconds
Started Jan 24 07:19:59 PM PST 24
Finished Jan 24 07:21:57 PM PST 24
Peak memory 201224 kb
Host smart-4efb6da2-8237-47e6-be37-17d43397c4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188031067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2188031067
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3400910293
Short name T326
Test name
Test status
Simulation time 324575178969 ps
CPU time 705.02 seconds
Started Jan 24 07:20:37 PM PST 24
Finished Jan 24 07:32:28 PM PST 24
Peak memory 201204 kb
Host smart-3bef49d7-a9fd-4b88-809a-918f8529bb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400910293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3400910293
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.730463120
Short name T226
Test name
Test status
Simulation time 438471011979 ps
CPU time 500.98 seconds
Started Jan 24 07:21:24 PM PST 24
Finished Jan 24 07:29:47 PM PST 24
Peak memory 212028 kb
Host smart-e3ad1a55-598b-44d5-a103-e921b349d17a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730463120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
730463120
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3488184963
Short name T312
Test name
Test status
Simulation time 329405337916 ps
CPU time 420.76 seconds
Started Jan 24 09:09:46 PM PST 24
Finished Jan 24 09:16:50 PM PST 24
Peak memory 201208 kb
Host smart-c62a795e-3909-4701-8d57-4efb7bd1af0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488184963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3488184963
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3563943850
Short name T767
Test name
Test status
Simulation time 85673125120 ps
CPU time 210.38 seconds
Started Jan 24 07:11:32 PM PST 24
Finished Jan 24 07:15:08 PM PST 24
Peak memory 209752 kb
Host smart-a798f90c-0817-4a5d-80bf-d6e0c86d3c13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563943850 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3563943850
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1877646482
Short name T139
Test name
Test status
Simulation time 163565448577 ps
CPU time 361.01 seconds
Started Jan 24 07:12:22 PM PST 24
Finished Jan 24 07:18:24 PM PST 24
Peak memory 201168 kb
Host smart-a84ee33f-796f-4801-b8b0-8a1c1fec5165
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877646482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1877646482
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2611394017
Short name T198
Test name
Test status
Simulation time 134244424154 ps
CPU time 679.4 seconds
Started Jan 24 07:12:54 PM PST 24
Finished Jan 24 07:24:14 PM PST 24
Peak memory 201392 kb
Host smart-9b941f03-88ec-440a-8dae-ee0cd594a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611394017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2611394017
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4183463624
Short name T313
Test name
Test status
Simulation time 330614234357 ps
CPU time 455.14 seconds
Started Jan 24 07:13:20 PM PST 24
Finished Jan 24 07:20:56 PM PST 24
Peak memory 201200 kb
Host smart-da911c8e-549f-4670-83bc-5ff6eb3bde5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183463624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4183463624
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.4195661641
Short name T354
Test name
Test status
Simulation time 317802339048 ps
CPU time 267.34 seconds
Started Jan 24 07:13:19 PM PST 24
Finished Jan 24 07:17:47 PM PST 24
Peak memory 201164 kb
Host smart-7625e9e7-2676-40f8-8f11-79e684dcd6d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195661641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.4195661641
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2532978994
Short name T336
Test name
Test status
Simulation time 319415553923 ps
CPU time 737.76 seconds
Started Jan 24 07:13:57 PM PST 24
Finished Jan 24 07:26:15 PM PST 24
Peak memory 201104 kb
Host smart-c42b4ee2-5ca5-4ebf-9613-25dafe866751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532978994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2532978994
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1009465178
Short name T202
Test name
Test status
Simulation time 115447415831 ps
CPU time 389.34 seconds
Started Jan 24 07:53:09 PM PST 24
Finished Jan 24 07:59:40 PM PST 24
Peak memory 201488 kb
Host smart-f5bafad9-bffc-4cda-8c49-6e201226397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009465178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1009465178
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3778523868
Short name T291
Test name
Test status
Simulation time 333382681301 ps
CPU time 192.95 seconds
Started Jan 24 07:15:01 PM PST 24
Finished Jan 24 07:18:20 PM PST 24
Peak memory 201236 kb
Host smart-4034b3bc-5519-43b1-9887-f87f261c1e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778523868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3778523868
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3820549346
Short name T148
Test name
Test status
Simulation time 449912077394 ps
CPU time 286.52 seconds
Started Jan 24 07:36:21 PM PST 24
Finished Jan 24 07:41:09 PM PST 24
Peak memory 209864 kb
Host smart-fb828837-7eba-4092-aa85-0f6f31470546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820549346 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3820549346
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1509698628
Short name T262
Test name
Test status
Simulation time 161840872045 ps
CPU time 395.46 seconds
Started Jan 24 07:45:40 PM PST 24
Finished Jan 24 07:52:17 PM PST 24
Peak memory 201256 kb
Host smart-c770a517-3005-4a83-9280-734e0da32a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509698628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1509698628
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2757062117
Short name T368
Test name
Test status
Simulation time 114358602682 ps
CPU time 603.31 seconds
Started Jan 24 07:15:39 PM PST 24
Finished Jan 24 07:25:43 PM PST 24
Peak memory 201388 kb
Host smart-729e0ef3-b893-412e-9beb-15a3b56aa85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757062117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2757062117
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3908233929
Short name T251
Test name
Test status
Simulation time 327745590119 ps
CPU time 405.87 seconds
Started Jan 24 07:07:59 PM PST 24
Finished Jan 24 07:14:48 PM PST 24
Peak memory 201196 kb
Host smart-1f457041-38b4-4de6-ad83-04fec9a489ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908233929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3908233929
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.451024007
Short name T176
Test name
Test status
Simulation time 321522231835 ps
CPU time 353.38 seconds
Started Jan 24 07:21:33 PM PST 24
Finished Jan 24 07:27:27 PM PST 24
Peak memory 201140 kb
Host smart-5abb0dca-6a81-461e-87b3-498ab7cae575
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451024007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.451024007
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1801067584
Short name T272
Test name
Test status
Simulation time 490892334415 ps
CPU time 1067.81 seconds
Started Jan 24 08:00:34 PM PST 24
Finished Jan 24 08:18:23 PM PST 24
Peak memory 201192 kb
Host smart-229751b9-8c93-4764-b377-83f10950dd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801067584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1801067584
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.288721903
Short name T349
Test name
Test status
Simulation time 495770608011 ps
CPU time 1154.74 seconds
Started Jan 24 07:27:55 PM PST 24
Finished Jan 24 07:47:11 PM PST 24
Peak memory 201140 kb
Host smart-7ed27523-6532-4aeb-947e-4a4134941b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288721903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.288721903
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2929406902
Short name T79
Test name
Test status
Simulation time 922003117 ps
CPU time 1.74 seconds
Started Jan 24 02:50:41 PM PST 24
Finished Jan 24 02:50:53 PM PST 24
Peak memory 200672 kb
Host smart-2c9cc878-f597-41c2-bb41-64e9ccb384fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929406902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2929406902
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.773437130
Short name T73
Test name
Test status
Simulation time 26650877921 ps
CPU time 18.12 seconds
Started Jan 24 02:50:40 PM PST 24
Finished Jan 24 02:51:08 PM PST 24
Peak memory 200836 kb
Host smart-80de6819-293c-40fa-b482-41ae305a507b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773437130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.773437130
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2625776967
Short name T80
Test name
Test status
Simulation time 773763549 ps
CPU time 1.18 seconds
Started Jan 24 02:50:42 PM PST 24
Finished Jan 24 02:50:53 PM PST 24
Peak memory 200504 kb
Host smart-c74605a0-fe61-4b1e-a770-2dc9fcc517c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625776967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2625776967
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3816989923
Short name T377
Test name
Test status
Simulation time 463717081 ps
CPU time 1.02 seconds
Started Jan 24 02:50:41 PM PST 24
Finished Jan 24 02:50:52 PM PST 24
Peak memory 200640 kb
Host smart-d1aceeff-5643-4f39-886e-287ee7b7ffb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816989923 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3816989923
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1320937815
Short name T860
Test name
Test status
Simulation time 425966964 ps
CPU time 1.09 seconds
Started Jan 24 02:50:37 PM PST 24
Finished Jan 24 02:50:48 PM PST 24
Peak memory 200508 kb
Host smart-c365683a-439d-4ec5-8268-4102fbb984ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320937815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1320937815
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1426245097
Short name T883
Test name
Test status
Simulation time 390946948 ps
CPU time 0.84 seconds
Started Jan 24 02:50:40 PM PST 24
Finished Jan 24 02:50:51 PM PST 24
Peak memory 200448 kb
Host smart-9126e1de-d063-4a0c-b022-5004f16b3a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426245097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1426245097
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.181350903
Short name T408
Test name
Test status
Simulation time 4458939895 ps
CPU time 5.5 seconds
Started Jan 24 02:50:49 PM PST 24
Finished Jan 24 02:51:13 PM PST 24
Peak memory 200824 kb
Host smart-2b1df7c3-2890-4670-8183-4bee8e01f239
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181350903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.181350903
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1289577100
Short name T417
Test name
Test status
Simulation time 941624670 ps
CPU time 1.87 seconds
Started Jan 24 02:50:49 PM PST 24
Finished Jan 24 02:51:09 PM PST 24
Peak memory 200772 kb
Host smart-93535aa5-aa98-4067-8158-d0eae9956762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289577100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1289577100
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3375485569
Short name T898
Test name
Test status
Simulation time 8650339477 ps
CPU time 6.05 seconds
Started Jan 24 02:50:49 PM PST 24
Finished Jan 24 02:51:13 PM PST 24
Peak memory 200848 kb
Host smart-fde5f734-7f1d-4843-b188-38326948a3aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375485569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3375485569
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1880514621
Short name T72
Test name
Test status
Simulation time 1265384997 ps
CPU time 3.73 seconds
Started Jan 24 02:50:53 PM PST 24
Finished Jan 24 02:51:13 PM PST 24
Peak memory 200720 kb
Host smart-0a8e337e-9f0c-4e8b-a4a3-f71b6564d133
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880514621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1880514621
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.949610557
Short name T383
Test name
Test status
Simulation time 26722495635 ps
CPU time 47.37 seconds
Started Jan 24 02:50:57 PM PST 24
Finished Jan 24 02:52:00 PM PST 24
Peak memory 200728 kb
Host smart-504e1c75-7735-40df-8bbf-6c166e12905a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949610557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.949610557
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2730191990
Short name T393
Test name
Test status
Simulation time 767072996 ps
CPU time 1.5 seconds
Started Jan 24 02:51:06 PM PST 24
Finished Jan 24 02:51:21 PM PST 24
Peak memory 200524 kb
Host smart-190f16f8-3b64-4895-89a6-057eb045e412
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730191990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2730191990
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3110028300
Short name T388
Test name
Test status
Simulation time 541984294 ps
CPU time 2.02 seconds
Started Jan 24 02:50:52 PM PST 24
Finished Jan 24 02:51:11 PM PST 24
Peak memory 200516 kb
Host smart-0a27e31d-6202-47ea-b70e-6fd1085192bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110028300 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3110028300
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1178659673
Short name T886
Test name
Test status
Simulation time 355684652 ps
CPU time 1.64 seconds
Started Jan 24 02:51:06 PM PST 24
Finished Jan 24 02:51:21 PM PST 24
Peak memory 200488 kb
Host smart-ad810fb1-f97f-4342-ab09-48d786d78c47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178659673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1178659673
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3462906004
Short name T188
Test name
Test status
Simulation time 394145582 ps
CPU time 1.54 seconds
Started Jan 24 02:51:06 PM PST 24
Finished Jan 24 02:51:21 PM PST 24
Peak memory 200492 kb
Host smart-8585ce3e-950c-4827-b8d8-b2c89dda0165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462906004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3462906004
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3095789115
Short name T859
Test name
Test status
Simulation time 2127217347 ps
CPU time 5.75 seconds
Started Jan 24 02:50:57 PM PST 24
Finished Jan 24 02:51:18 PM PST 24
Peak memory 200600 kb
Host smart-0c0d6435-6573-4a68-88b8-34f901ba93ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095789115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3095789115
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.509695835
Short name T890
Test name
Test status
Simulation time 679671653 ps
CPU time 1.57 seconds
Started Jan 24 02:50:39 PM PST 24
Finished Jan 24 02:50:51 PM PST 24
Peak memory 200788 kb
Host smart-f321a84d-4d7e-4f41-abe5-273e9154852c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509695835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.509695835
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1578134369
Short name T357
Test name
Test status
Simulation time 4252419873 ps
CPU time 6.26 seconds
Started Jan 24 02:50:47 PM PST 24
Finished Jan 24 02:51:11 PM PST 24
Peak memory 200808 kb
Host smart-e15d90b8-06d1-4333-b9ce-bce15ea65a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578134369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1578134369
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4033733085
Short name T902
Test name
Test status
Simulation time 370788435 ps
CPU time 1.43 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:45 PM PST 24
Peak memory 200612 kb
Host smart-c3440a7c-95f5-4134-b4a6-7ee56bcae62d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033733085 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.4033733085
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2599682985
Short name T400
Test name
Test status
Simulation time 469906086 ps
CPU time 1.37 seconds
Started Jan 24 03:22:36 PM PST 24
Finished Jan 24 03:22:40 PM PST 24
Peak memory 200540 kb
Host smart-bd0ffad0-3acf-4af2-b48b-1a2a07966e8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599682985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2599682985
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1752063247
Short name T901
Test name
Test status
Simulation time 353153723 ps
CPU time 0.98 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:45 PM PST 24
Peak memory 200064 kb
Host smart-7d7680ee-5d39-46a8-87fd-bd92413f982d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752063247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1752063247
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2628124746
Short name T884
Test name
Test status
Simulation time 3851141130 ps
CPU time 3.96 seconds
Started Jan 24 02:51:25 PM PST 24
Finished Jan 24 02:51:39 PM PST 24
Peak memory 200856 kb
Host smart-b56470bc-12fb-4e35-9373-e62cc48eac49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628124746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2628124746
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1173037453
Short name T404
Test name
Test status
Simulation time 480769163 ps
CPU time 3.06 seconds
Started Jan 24 02:51:27 PM PST 24
Finished Jan 24 02:51:41 PM PST 24
Peak memory 200840 kb
Host smart-a383a495-d67f-4526-a100-31c265038671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173037453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1173037453
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.331314167
Short name T887
Test name
Test status
Simulation time 3973400858 ps
CPU time 10.8 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:55 PM PST 24
Peak memory 200824 kb
Host smart-9b9d9402-ce79-4867-89d3-ba580abc66e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331314167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.331314167
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1784791863
Short name T414
Test name
Test status
Simulation time 438408189 ps
CPU time 1.89 seconds
Started Jan 24 03:17:25 PM PST 24
Finished Jan 24 03:17:29 PM PST 24
Peak memory 200656 kb
Host smart-2da64081-e2d2-4d45-9db1-74a6daddb098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784791863 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1784791863
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2564026638
Short name T8
Test name
Test status
Simulation time 539805262 ps
CPU time 1.02 seconds
Started Jan 24 03:06:33 PM PST 24
Finished Jan 24 03:06:47 PM PST 24
Peak memory 200544 kb
Host smart-e3d8a879-7b88-4415-8ae1-6fea84425950
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564026638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2564026638
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2976882832
Short name T37
Test name
Test status
Simulation time 5256279351 ps
CPU time 7.24 seconds
Started Jan 24 03:28:53 PM PST 24
Finished Jan 24 03:29:01 PM PST 24
Peak memory 200872 kb
Host smart-d2f8617e-5854-413f-8521-1c24a57e1c67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976882832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2976882832
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3642078440
Short name T878
Test name
Test status
Simulation time 485131598 ps
CPU time 2.83 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:47 PM PST 24
Peak memory 200852 kb
Host smart-54bd39a3-287f-430b-b315-316bf65684a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642078440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3642078440
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4257369160
Short name T879
Test name
Test status
Simulation time 7872039785 ps
CPU time 21.81 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:52:06 PM PST 24
Peak memory 200732 kb
Host smart-8b7f2223-b0a4-46b1-9ae6-5192c6ba93cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257369160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.4257369160
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3739023325
Short name T888
Test name
Test status
Simulation time 594900527 ps
CPU time 1.18 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:45 PM PST 24
Peak memory 200644 kb
Host smart-ac6404c9-8f14-4af8-a0b2-0eca96efac2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739023325 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3739023325
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2610089251
Short name T881
Test name
Test status
Simulation time 1982628620 ps
CPU time 5.13 seconds
Started Jan 24 02:56:00 PM PST 24
Finished Jan 24 02:56:09 PM PST 24
Peak memory 200612 kb
Host smart-46346b6a-5b36-4e29-b422-11391aa6766f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610089251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2610089251
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1125731158
Short name T70
Test name
Test status
Simulation time 351043955 ps
CPU time 2.19 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:46 PM PST 24
Peak memory 200836 kb
Host smart-f9bfb496-4041-4ec1-ac44-bbbcd0695e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125731158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1125731158
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3553715926
Short name T40
Test name
Test status
Simulation time 4341406107 ps
CPU time 4.18 seconds
Started Jan 24 03:00:14 PM PST 24
Finished Jan 24 03:00:32 PM PST 24
Peak memory 200880 kb
Host smart-5b455286-d597-47c6-8526-e3d2063eff40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553715926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3553715926
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2712958532
Short name T877
Test name
Test status
Simulation time 435374859 ps
CPU time 1.69 seconds
Started Jan 24 02:51:41 PM PST 24
Finished Jan 24 02:51:54 PM PST 24
Peak memory 200644 kb
Host smart-e599f407-1e29-47c5-8d95-831f1ed85950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712958532 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2712958532
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2022880602
Short name T3
Test name
Test status
Simulation time 474763730 ps
CPU time 1.91 seconds
Started Jan 24 02:51:38 PM PST 24
Finished Jan 24 02:51:51 PM PST 24
Peak memory 200544 kb
Host smart-fd9dbb74-d6ce-4ee8-80db-691e1f13e2a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022880602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2022880602
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3855554740
Short name T871
Test name
Test status
Simulation time 516117641 ps
CPU time 1.93 seconds
Started Jan 24 02:56:35 PM PST 24
Finished Jan 24 02:56:38 PM PST 24
Peak memory 200484 kb
Host smart-05a08c41-2bd0-402b-b317-eddb39b0dbc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855554740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3855554740
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3087760233
Short name T35
Test name
Test status
Simulation time 4232403428 ps
CPU time 2.84 seconds
Started Jan 24 02:51:37 PM PST 24
Finished Jan 24 02:51:52 PM PST 24
Peak memory 200884 kb
Host smart-41791812-e334-469c-bdfe-1a385db29e8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087760233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3087760233
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2514789841
Short name T44
Test name
Test status
Simulation time 504999759 ps
CPU time 3.6 seconds
Started Jan 24 02:51:27 PM PST 24
Finished Jan 24 02:51:42 PM PST 24
Peak memory 200836 kb
Host smart-0a30b32e-910d-4ec5-ac46-26b1f19eb21c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514789841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2514789841
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4239225432
Short name T66
Test name
Test status
Simulation time 9108078576 ps
CPU time 7.42 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:52 PM PST 24
Peak memory 200772 kb
Host smart-27b82a69-0a03-469c-9526-fd34ef01b68f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239225432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.4239225432
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3462240765
Short name T418
Test name
Test status
Simulation time 388897089 ps
CPU time 1.78 seconds
Started Jan 24 02:51:48 PM PST 24
Finished Jan 24 02:51:57 PM PST 24
Peak memory 200648 kb
Host smart-ded72a26-9a76-4042-a83f-5e3764a597ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462240765 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3462240765
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1224936505
Short name T862
Test name
Test status
Simulation time 316268740 ps
CPU time 1.06 seconds
Started Jan 24 02:51:46 PM PST 24
Finished Jan 24 02:51:55 PM PST 24
Peak memory 200536 kb
Host smart-7ba4fa39-247e-4890-8983-bba052547d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224936505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1224936505
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2499002688
Short name T421
Test name
Test status
Simulation time 314847353 ps
CPU time 1.13 seconds
Started Jan 24 02:51:55 PM PST 24
Finished Jan 24 02:52:02 PM PST 24
Peak memory 200464 kb
Host smart-0ca1e682-c52f-4673-ac87-441d4f350cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499002688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2499002688
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1732441239
Short name T36
Test name
Test status
Simulation time 3607719183 ps
CPU time 3.07 seconds
Started Jan 24 02:51:52 PM PST 24
Finished Jan 24 02:52:02 PM PST 24
Peak memory 200740 kb
Host smart-6f68eb85-2a8c-44c8-9935-bc1bedcdd33f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732441239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1732441239
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1927067964
Short name T893
Test name
Test status
Simulation time 397957709 ps
CPU time 2.18 seconds
Started Jan 24 02:51:55 PM PST 24
Finished Jan 24 02:52:03 PM PST 24
Peak memory 200792 kb
Host smart-e33bdb14-4a01-4479-b163-bab4a40faef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927067964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1927067964
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1700880823
Short name T360
Test name
Test status
Simulation time 8530545895 ps
CPU time 22.86 seconds
Started Jan 24 02:51:51 PM PST 24
Finished Jan 24 02:52:22 PM PST 24
Peak memory 200804 kb
Host smart-8440f1ef-6286-4bbb-892d-b6bcd875414d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700880823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1700880823
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.326797512
Short name T895
Test name
Test status
Simulation time 456355530 ps
CPU time 1.14 seconds
Started Jan 24 02:51:45 PM PST 24
Finished Jan 24 02:51:54 PM PST 24
Peak memory 200624 kb
Host smart-958ba235-ddbb-4293-af78-fc2881dac891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326797512 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.326797512
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.759300463
Short name T867
Test name
Test status
Simulation time 507178288 ps
CPU time 1.23 seconds
Started Jan 24 02:51:47 PM PST 24
Finished Jan 24 02:51:56 PM PST 24
Peak memory 200524 kb
Host smart-4f12029b-bd2b-4192-84f0-1c7b8732ef1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759300463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.759300463
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.350107171
Short name T892
Test name
Test status
Simulation time 4103520095 ps
CPU time 3.43 seconds
Started Jan 24 02:51:48 PM PST 24
Finished Jan 24 02:51:59 PM PST 24
Peak memory 200876 kb
Host smart-ef932175-aeac-4feb-b018-59a07ed19421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350107171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.350107171
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4008182549
Short name T26
Test name
Test status
Simulation time 488457776 ps
CPU time 2.36 seconds
Started Jan 24 02:51:46 PM PST 24
Finished Jan 24 02:51:56 PM PST 24
Peak memory 200856 kb
Host smart-4c200c77-2da4-420c-ab45-2824205dafdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008182549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4008182549
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1397211105
Short name T872
Test name
Test status
Simulation time 4271259048 ps
CPU time 6.14 seconds
Started Jan 24 02:51:54 PM PST 24
Finished Jan 24 02:52:07 PM PST 24
Peak memory 200840 kb
Host smart-2678cac9-dd44-4d32-aa82-41a6440e2e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397211105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1397211105
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2113158607
Short name T863
Test name
Test status
Simulation time 590737295 ps
CPU time 1.47 seconds
Started Jan 24 02:52:02 PM PST 24
Finished Jan 24 02:52:06 PM PST 24
Peak memory 200628 kb
Host smart-e57c3172-e1db-490e-97e4-252cee3d19fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113158607 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2113158607
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2910350156
Short name T84
Test name
Test status
Simulation time 531767817 ps
CPU time 1.1 seconds
Started Jan 24 02:52:03 PM PST 24
Finished Jan 24 02:52:07 PM PST 24
Peak memory 200536 kb
Host smart-a050e666-6ffe-4388-b406-923a659f3147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910350156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2910350156
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.782920000
Short name T868
Test name
Test status
Simulation time 439068278 ps
CPU time 0.74 seconds
Started Jan 24 02:52:05 PM PST 24
Finished Jan 24 02:52:11 PM PST 24
Peak memory 200476 kb
Host smart-6f8d32e2-6331-45b9-a516-465bd01f9387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782920000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.782920000
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1491134220
Short name T71
Test name
Test status
Simulation time 3024789557 ps
CPU time 2.04 seconds
Started Jan 24 02:52:05 PM PST 24
Finished Jan 24 02:52:11 PM PST 24
Peak memory 200644 kb
Host smart-6ac2c2f3-e105-4e0d-a796-ff4ca36160f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491134220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1491134220
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3203121061
Short name T65
Test name
Test status
Simulation time 536449389 ps
CPU time 2.87 seconds
Started Jan 24 02:51:55 PM PST 24
Finished Jan 24 02:52:04 PM PST 24
Peak memory 200836 kb
Host smart-d121869e-2be2-403e-88d8-265332a6fdcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203121061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3203121061
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.576390886
Short name T885
Test name
Test status
Simulation time 402195959 ps
CPU time 1.58 seconds
Started Jan 24 02:52:02 PM PST 24
Finished Jan 24 02:52:07 PM PST 24
Peak memory 200664 kb
Host smart-61c8bcd2-5603-47c0-af50-106b0d9ed772
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576390886 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.576390886
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4046181997
Short name T77
Test name
Test status
Simulation time 584493786 ps
CPU time 1.05 seconds
Started Jan 24 02:52:01 PM PST 24
Finished Jan 24 02:52:06 PM PST 24
Peak memory 200532 kb
Host smart-14bdb776-9657-477e-8734-3822954e7407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046181997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.4046181997
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.669312535
Short name T857
Test name
Test status
Simulation time 448426114 ps
CPU time 0.9 seconds
Started Jan 24 02:52:05 PM PST 24
Finished Jan 24 02:52:10 PM PST 24
Peak memory 200472 kb
Host smart-072ebf61-2abf-429e-93d9-1aff17b8139e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669312535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.669312535
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1155310280
Short name T385
Test name
Test status
Simulation time 4775940943 ps
CPU time 20.49 seconds
Started Jan 24 02:52:02 PM PST 24
Finished Jan 24 02:52:26 PM PST 24
Peak memory 200892 kb
Host smart-0e1b39b5-b7e4-45ea-867e-f8e455e832ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155310280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1155310280
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2701249187
Short name T865
Test name
Test status
Simulation time 461986344 ps
CPU time 2.36 seconds
Started Jan 24 02:52:05 PM PST 24
Finished Jan 24 02:52:12 PM PST 24
Peak memory 200832 kb
Host smart-2c2ca9fb-3493-445b-97fc-49fba125168e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701249187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2701249187
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.73100286
Short name T903
Test name
Test status
Simulation time 4803537315 ps
CPU time 3.13 seconds
Started Jan 24 02:52:05 PM PST 24
Finished Jan 24 02:52:13 PM PST 24
Peak memory 200856 kb
Host smart-ed302849-bc0e-4c87-9198-056c84811575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73100286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_int
g_err.73100286
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3883618959
Short name T396
Test name
Test status
Simulation time 373724363 ps
CPU time 1.61 seconds
Started Jan 24 02:52:20 PM PST 24
Finished Jan 24 02:52:28 PM PST 24
Peak memory 200624 kb
Host smart-26b001cc-d88b-48f9-abd4-0052ed48bac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883618959 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3883618959
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.362492254
Short name T882
Test name
Test status
Simulation time 423936251 ps
CPU time 1.24 seconds
Started Jan 24 02:52:17 PM PST 24
Finished Jan 24 02:52:23 PM PST 24
Peak memory 200468 kb
Host smart-1a443053-5f2e-4a7f-ac75-79f5d6e74c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362492254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.362492254
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2178438197
Short name T32
Test name
Test status
Simulation time 396808772 ps
CPU time 1.1 seconds
Started Jan 24 02:52:27 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 200492 kb
Host smart-da25cc08-4050-463f-8a05-e672f9fef543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178438197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2178438197
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1886411306
Short name T180
Test name
Test status
Simulation time 2420841284 ps
CPU time 8.29 seconds
Started Jan 24 02:52:19 PM PST 24
Finished Jan 24 02:52:33 PM PST 24
Peak memory 200664 kb
Host smart-9d18069d-3e43-4fdb-ab79-4bc0b17902f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886411306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1886411306
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1013689623
Short name T64
Test name
Test status
Simulation time 395458292 ps
CPU time 2.99 seconds
Started Jan 24 02:52:02 PM PST 24
Finished Jan 24 02:52:08 PM PST 24
Peak memory 200888 kb
Host smart-5c9a96a1-dfaa-43e9-9f75-f0cd4d30b863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013689623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1013689623
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1616056209
Short name T880
Test name
Test status
Simulation time 8105022771 ps
CPU time 15.09 seconds
Started Jan 24 02:52:24 PM PST 24
Finished Jan 24 02:52:50 PM PST 24
Peak memory 200876 kb
Host smart-c28096a3-5a42-4cf9-9643-d7c809d1f832
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616056209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1616056209
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2744120138
Short name T866
Test name
Test status
Simulation time 477856671 ps
CPU time 1.06 seconds
Started Jan 24 02:52:21 PM PST 24
Finished Jan 24 02:52:29 PM PST 24
Peak memory 200696 kb
Host smart-79431214-b2a4-46fb-b9cb-6fc3ec6c92e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744120138 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2744120138
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2449851727
Short name T402
Test name
Test status
Simulation time 389889757 ps
CPU time 1.54 seconds
Started Jan 24 02:52:19 PM PST 24
Finished Jan 24 02:52:27 PM PST 24
Peak memory 200012 kb
Host smart-ef6eb945-394b-4a78-8d75-1a0f233a8870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449851727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2449851727
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2731946176
Short name T181
Test name
Test status
Simulation time 4422036568 ps
CPU time 3.52 seconds
Started Jan 24 02:52:28 PM PST 24
Finished Jan 24 02:52:43 PM PST 24
Peak memory 200868 kb
Host smart-8a69f436-689e-4398-88f1-0b905196aeba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731946176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2731946176
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1350569892
Short name T67
Test name
Test status
Simulation time 644137482 ps
CPU time 1.85 seconds
Started Jan 24 02:52:27 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 200860 kb
Host smart-b0032529-3e3a-493d-ba01-543ad8884311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350569892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1350569892
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2011534541
Short name T406
Test name
Test status
Simulation time 4355009248 ps
CPU time 3.16 seconds
Started Jan 24 02:52:26 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 200888 kb
Host smart-95be56a7-7685-4246-ac58-ff5baea70697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011534541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2011534541
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.44986035
Short name T904
Test name
Test status
Simulation time 1027295089 ps
CPU time 1.63 seconds
Started Jan 24 02:51:06 PM PST 24
Finished Jan 24 02:51:21 PM PST 24
Peak memory 200732 kb
Host smart-259c6025-5757-43aa-962d-cbc45b06140b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44986035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasi
ng.44986035
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3677913822
Short name T75
Test name
Test status
Simulation time 695288644 ps
CPU time 1.41 seconds
Started Jan 24 02:50:57 PM PST 24
Finished Jan 24 02:51:14 PM PST 24
Peak memory 200480 kb
Host smart-0a550751-dba0-4d1b-8f15-89e3ecbf5531
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677913822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3677913822
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.800649639
Short name T25
Test name
Test status
Simulation time 461484358 ps
CPU time 1.85 seconds
Started Jan 24 02:51:06 PM PST 24
Finished Jan 24 02:51:21 PM PST 24
Peak memory 200612 kb
Host smart-3155bdfe-547b-44b7-a134-66438c241ee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800649639 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.800649639
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1403485887
Short name T415
Test name
Test status
Simulation time 448629167 ps
CPU time 1.51 seconds
Started Jan 24 02:51:06 PM PST 24
Finished Jan 24 02:51:21 PM PST 24
Peak memory 200492 kb
Host smart-f9b83ab8-be4d-4e34-b896-8676e91b284a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403485887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1403485887
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4272923505
Short name T27
Test name
Test status
Simulation time 473583918 ps
CPU time 0.91 seconds
Started Jan 24 02:50:52 PM PST 24
Finished Jan 24 02:51:10 PM PST 24
Peak memory 200504 kb
Host smart-34899b5e-1038-406d-b45a-cd587d071892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272923505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4272923505
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4244117753
Short name T413
Test name
Test status
Simulation time 2844475786 ps
CPU time 6.79 seconds
Started Jan 24 02:50:52 PM PST 24
Finished Jan 24 02:51:16 PM PST 24
Peak memory 200532 kb
Host smart-bcf295a5-c0fc-4bd4-982d-fa1934500a8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244117753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.4244117753
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4193398507
Short name T69
Test name
Test status
Simulation time 1763548678 ps
CPU time 2.85 seconds
Started Jan 24 02:50:56 PM PST 24
Finished Jan 24 02:51:15 PM PST 24
Peak memory 217188 kb
Host smart-7e4d9e87-0c82-4444-ad06-bf42e528b482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193398507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4193398507
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1558578420
Short name T358
Test name
Test status
Simulation time 8752091717 ps
CPU time 7.38 seconds
Started Jan 24 02:50:50 PM PST 24
Finished Jan 24 02:51:15 PM PST 24
Peak memory 200876 kb
Host smart-6ca66f76-d757-4a73-b60d-c354aa4247e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558578420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1558578420
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3479464951
Short name T424
Test name
Test status
Simulation time 291969183 ps
CPU time 0.89 seconds
Started Jan 24 02:52:27 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 199992 kb
Host smart-4187d2a4-f202-43d5-b16a-80e08c1ccf6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479464951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3479464951
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3789231174
Short name T380
Test name
Test status
Simulation time 307784794 ps
CPU time 0.78 seconds
Started Jan 24 02:52:24 PM PST 24
Finished Jan 24 02:52:36 PM PST 24
Peak memory 200488 kb
Host smart-d6b11e6b-ae05-42c6-9fd7-540bdcc0d684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789231174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3789231174
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3557393287
Short name T905
Test name
Test status
Simulation time 430510945 ps
CPU time 1.52 seconds
Started Jan 24 02:52:27 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 200012 kb
Host smart-2d966b78-78fd-4a92-8884-8a510db5859b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557393287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3557393287
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2272191027
Short name T398
Test name
Test status
Simulation time 477442419 ps
CPU time 1.78 seconds
Started Jan 24 02:52:19 PM PST 24
Finished Jan 24 02:52:27 PM PST 24
Peak memory 200024 kb
Host smart-ff10a83b-ef54-4405-874a-5a0e652c463a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272191027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2272191027
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3749912200
Short name T399
Test name
Test status
Simulation time 427316559 ps
CPU time 0.89 seconds
Started Jan 24 02:52:20 PM PST 24
Finished Jan 24 02:52:27 PM PST 24
Peak memory 200512 kb
Host smart-931c5fa3-3f77-45d1-94dc-e24bc37efd3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749912200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3749912200
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2103872838
Short name T894
Test name
Test status
Simulation time 494785681 ps
CPU time 1.78 seconds
Started Jan 24 02:52:18 PM PST 24
Finished Jan 24 02:52:25 PM PST 24
Peak memory 200468 kb
Host smart-13a2e442-69b3-4a2f-b805-2931399f40e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103872838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2103872838
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4069427418
Short name T409
Test name
Test status
Simulation time 480431486 ps
CPU time 0.94 seconds
Started Jan 24 02:52:21 PM PST 24
Finished Jan 24 02:52:30 PM PST 24
Peak memory 200484 kb
Host smart-1352d6dd-5f2e-4447-9794-1d5e6cf074fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069427418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4069427418
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3723751187
Short name T864
Test name
Test status
Simulation time 432150318 ps
CPU time 1.61 seconds
Started Jan 24 02:52:26 PM PST 24
Finished Jan 24 02:52:39 PM PST 24
Peak memory 200516 kb
Host smart-3392ad9e-9399-4d2f-822f-040105388a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723751187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3723751187
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4071555550
Short name T378
Test name
Test status
Simulation time 306767701 ps
CPU time 1.34 seconds
Started Jan 24 02:52:19 PM PST 24
Finished Jan 24 02:52:27 PM PST 24
Peak memory 200508 kb
Host smart-062e9077-ca37-4edb-ab96-7316a3c12b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071555550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.4071555550
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2042220495
Short name T407
Test name
Test status
Simulation time 535599681 ps
CPU time 0.78 seconds
Started Jan 24 02:52:24 PM PST 24
Finished Jan 24 02:52:36 PM PST 24
Peak memory 200504 kb
Host smart-edcc5b99-08dd-44ed-9040-2f69e085761b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042220495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2042220495
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.422741227
Short name T2
Test name
Test status
Simulation time 824676003 ps
CPU time 3.82 seconds
Started Jan 24 02:51:00 PM PST 24
Finished Jan 24 02:51:18 PM PST 24
Peak memory 200692 kb
Host smart-7b0d15c1-f840-4a7e-8cf4-4f1ae8087fe4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422741227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.422741227
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1796333911
Short name T9
Test name
Test status
Simulation time 47574347819 ps
CPU time 183.05 seconds
Started Jan 24 02:50:58 PM PST 24
Finished Jan 24 02:54:17 PM PST 24
Peak memory 200784 kb
Host smart-040c4c4f-1ff5-4684-88fc-330be6efb351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796333911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1796333911
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1659526635
Short name T394
Test name
Test status
Simulation time 832946944 ps
CPU time 2.08 seconds
Started Jan 24 02:50:59 PM PST 24
Finished Jan 24 02:51:16 PM PST 24
Peak memory 200528 kb
Host smart-10655a32-1ad5-4bac-b37e-a52f9d884e22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659526635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1659526635
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.939677080
Short name T34
Test name
Test status
Simulation time 467175606 ps
CPU time 1.34 seconds
Started Jan 24 02:50:56 PM PST 24
Finished Jan 24 02:51:14 PM PST 24
Peak memory 200656 kb
Host smart-18ba26b0-b792-4a84-9b8c-3a0f171a5b3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939677080 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.939677080
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3625858808
Short name T420
Test name
Test status
Simulation time 427432091 ps
CPU time 1.2 seconds
Started Jan 24 02:50:58 PM PST 24
Finished Jan 24 02:51:14 PM PST 24
Peak memory 200528 kb
Host smart-34ba380e-9544-42bf-837b-8bb936a5fb70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625858808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3625858808
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1399031689
Short name T858
Test name
Test status
Simulation time 460190526 ps
CPU time 0.87 seconds
Started Jan 24 02:50:58 PM PST 24
Finished Jan 24 02:51:13 PM PST 24
Peak memory 200452 kb
Host smart-27d5e627-5a79-4db2-81c3-79917e01d990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399031689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1399031689
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2516925864
Short name T392
Test name
Test status
Simulation time 4997929761 ps
CPU time 10.59 seconds
Started Jan 24 02:51:02 PM PST 24
Finished Jan 24 02:51:27 PM PST 24
Peak memory 200848 kb
Host smart-e2cc415c-ad63-4e11-aa85-57ba82f7edc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516925864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2516925864
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3256762780
Short name T387
Test name
Test status
Simulation time 578378671 ps
CPU time 1.77 seconds
Started Jan 24 02:51:06 PM PST 24
Finished Jan 24 02:51:21 PM PST 24
Peak memory 200792 kb
Host smart-3bbbe752-482e-4d67-847d-52e1ab80b61c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256762780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3256762780
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3706034214
Short name T179
Test name
Test status
Simulation time 4858747500 ps
CPU time 4.58 seconds
Started Jan 24 02:50:49 PM PST 24
Finished Jan 24 02:51:12 PM PST 24
Peak memory 200860 kb
Host smart-36d5b470-500e-49e8-a72c-fa6f938541b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706034214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3706034214
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4036544913
Short name T395
Test name
Test status
Simulation time 518177152 ps
CPU time 1.76 seconds
Started Jan 24 02:52:26 PM PST 24
Finished Jan 24 02:52:39 PM PST 24
Peak memory 200516 kb
Host smart-5f5d771d-189f-4fb3-97c5-b64a623d8bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036544913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4036544913
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2282701947
Short name T391
Test name
Test status
Simulation time 535066402 ps
CPU time 0.92 seconds
Started Jan 24 02:52:26 PM PST 24
Finished Jan 24 02:52:38 PM PST 24
Peak memory 200516 kb
Host smart-76fd8aca-2d7c-4bd1-afc9-4d2ecfdb10c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282701947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2282701947
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.921911580
Short name T379
Test name
Test status
Simulation time 413105559 ps
CPU time 1.58 seconds
Started Jan 24 02:52:19 PM PST 24
Finished Jan 24 02:52:26 PM PST 24
Peak memory 200488 kb
Host smart-6d2fb830-b18a-47e5-b6cb-a2984b2f8462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921911580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.921911580
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2982981510
Short name T875
Test name
Test status
Simulation time 333490175 ps
CPU time 0.75 seconds
Started Jan 24 02:52:20 PM PST 24
Finished Jan 24 02:52:27 PM PST 24
Peak memory 200512 kb
Host smart-04395a39-f694-499b-abc6-a2ad393e4781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982981510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2982981510
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3661123665
Short name T390
Test name
Test status
Simulation time 477718834 ps
CPU time 1.7 seconds
Started Jan 24 02:52:21 PM PST 24
Finished Jan 24 02:52:30 PM PST 24
Peak memory 199988 kb
Host smart-806e7be2-08b6-4d72-b138-b6ed2cef91e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661123665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3661123665
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.788123620
Short name T386
Test name
Test status
Simulation time 288778638 ps
CPU time 0.94 seconds
Started Jan 24 02:52:19 PM PST 24
Finished Jan 24 02:52:25 PM PST 24
Peak memory 200520 kb
Host smart-a58da92b-43bf-46d1-b9c4-37ad89c35bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788123620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.788123620
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2766929423
Short name T412
Test name
Test status
Simulation time 284623014 ps
CPU time 1.37 seconds
Started Jan 24 02:52:24 PM PST 24
Finished Jan 24 02:52:36 PM PST 24
Peak memory 200504 kb
Host smart-f7a6e3f5-5cc8-46f1-a404-e38d294af2ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766929423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2766929423
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1187624393
Short name T182
Test name
Test status
Simulation time 408229564 ps
CPU time 0.89 seconds
Started Jan 24 02:52:27 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 200492 kb
Host smart-17186b4c-f2cb-4a0d-83ae-ac7db9575f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187624393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1187624393
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2545867797
Short name T422
Test name
Test status
Simulation time 491402781 ps
CPU time 1.75 seconds
Started Jan 24 02:52:27 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 200000 kb
Host smart-6e0b9c2e-6fc8-4286-911e-b871861ea857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545867797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2545867797
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3867944735
Short name T419
Test name
Test status
Simulation time 424595590 ps
CPU time 1.24 seconds
Started Jan 24 02:52:21 PM PST 24
Finished Jan 24 02:52:31 PM PST 24
Peak memory 200480 kb
Host smart-1f65a0ee-7610-45e9-bb1b-b89f9b494513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867944735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3867944735
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.663096656
Short name T81
Test name
Test status
Simulation time 1007780460 ps
CPU time 5.31 seconds
Started Jan 24 02:51:09 PM PST 24
Finished Jan 24 02:51:28 PM PST 24
Peak memory 200732 kb
Host smart-69c7a831-bedc-41ce-8d5a-4e935bb51a68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663096656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.663096656
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.904194859
Short name T873
Test name
Test status
Simulation time 2052353307 ps
CPU time 4.34 seconds
Started Jan 24 02:51:09 PM PST 24
Finished Jan 24 02:51:27 PM PST 24
Peak memory 200660 kb
Host smart-439fa22a-5686-4026-bf4b-44c9c1dd8507
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904194859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.904194859
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3018810472
Short name T423
Test name
Test status
Simulation time 864092156 ps
CPU time 1.69 seconds
Started Jan 24 02:51:09 PM PST 24
Finished Jan 24 02:51:24 PM PST 24
Peak memory 200520 kb
Host smart-0b17e6d2-cd62-43b6-875a-5b7689a28c90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018810472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3018810472
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2136121824
Short name T401
Test name
Test status
Simulation time 457068989 ps
CPU time 1.69 seconds
Started Jan 24 02:51:05 PM PST 24
Finished Jan 24 02:51:21 PM PST 24
Peak memory 200644 kb
Host smart-1b6a35dd-3831-495f-90cf-84f920387abf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136121824 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2136121824
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1358786060
Short name T897
Test name
Test status
Simulation time 372728007 ps
CPU time 0.89 seconds
Started Jan 24 02:51:10 PM PST 24
Finished Jan 24 02:51:25 PM PST 24
Peak memory 200524 kb
Host smart-ca78d44d-da95-4218-81c7-5a66250c5c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358786060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1358786060
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3156457286
Short name T28
Test name
Test status
Simulation time 443091021 ps
CPU time 1.11 seconds
Started Jan 24 02:51:09 PM PST 24
Finished Jan 24 02:51:24 PM PST 24
Peak memory 200504 kb
Host smart-63b731fd-e8cc-48f1-9f60-7eb3df8735ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156457286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3156457286
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3381836738
Short name T896
Test name
Test status
Simulation time 2271554802 ps
CPU time 1.45 seconds
Started Jan 24 02:51:08 PM PST 24
Finished Jan 24 02:51:24 PM PST 24
Peak memory 200668 kb
Host smart-05387130-9170-40f5-b0ce-38d9cb4f318e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381836738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3381836738
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2382363348
Short name T410
Test name
Test status
Simulation time 477034634 ps
CPU time 2.64 seconds
Started Jan 24 02:51:09 PM PST 24
Finished Jan 24 02:51:26 PM PST 24
Peak memory 200820 kb
Host smart-a90b2c92-3989-4f2c-a5c6-450698974316
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382363348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2382363348
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.505793574
Short name T389
Test name
Test status
Simulation time 409027092 ps
CPU time 1.6 seconds
Started Jan 24 02:52:21 PM PST 24
Finished Jan 24 02:52:29 PM PST 24
Peak memory 200524 kb
Host smart-0ab2fd74-858e-4ba9-8bcb-5171adbe0541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505793574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.505793574
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2326410970
Short name T82
Test name
Test status
Simulation time 526454043 ps
CPU time 1.97 seconds
Started Jan 24 02:54:51 PM PST 24
Finished Jan 24 02:55:07 PM PST 24
Peak memory 200512 kb
Host smart-fd0c4c2e-5845-4a1e-878e-76f9a86498ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326410970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2326410970
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2141987021
Short name T376
Test name
Test status
Simulation time 286964012 ps
CPU time 1.32 seconds
Started Jan 24 02:52:32 PM PST 24
Finished Jan 24 02:52:46 PM PST 24
Peak memory 200496 kb
Host smart-f4a52bb7-b7b5-4ede-8101-f3b5d6efe2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141987021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2141987021
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1132632879
Short name T382
Test name
Test status
Simulation time 330923805 ps
CPU time 1.43 seconds
Started Jan 24 02:52:27 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 200484 kb
Host smart-f86a20f8-d9ea-4b61-85c3-3b44f08222e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132632879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1132632879
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3350163852
Short name T891
Test name
Test status
Simulation time 502931779 ps
CPU time 1.7 seconds
Started Jan 24 04:50:31 PM PST 24
Finished Jan 24 04:50:34 PM PST 24
Peak memory 200512 kb
Host smart-ddc1fe11-cbdf-4c6b-a827-670d9cdb5339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350163852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3350163852
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4172644133
Short name T381
Test name
Test status
Simulation time 306310997 ps
CPU time 0.8 seconds
Started Jan 24 03:19:00 PM PST 24
Finished Jan 24 03:19:04 PM PST 24
Peak memory 200484 kb
Host smart-af094937-5153-447a-88cd-a25b03b572ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172644133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4172644133
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3269426463
Short name T184
Test name
Test status
Simulation time 390281620 ps
CPU time 1.61 seconds
Started Jan 24 02:52:26 PM PST 24
Finished Jan 24 02:52:39 PM PST 24
Peak memory 200024 kb
Host smart-12c3fe49-8970-4d59-ac54-ee4a1ea1bdde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269426463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3269426463
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2447270859
Short name T24
Test name
Test status
Simulation time 332137428 ps
CPU time 1.35 seconds
Started Jan 24 03:05:01 PM PST 24
Finished Jan 24 03:05:09 PM PST 24
Peak memory 200500 kb
Host smart-ec37f5f5-081e-463c-9461-6fcd7944414d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447270859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2447270859
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3182397543
Short name T899
Test name
Test status
Simulation time 283767513 ps
CPU time 1.34 seconds
Started Jan 24 02:52:37 PM PST 24
Finished Jan 24 02:52:50 PM PST 24
Peak memory 200472 kb
Host smart-d667c527-e3bf-4159-b8a0-8471ac82f795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182397543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3182397543
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1420657036
Short name T869
Test name
Test status
Simulation time 542391785 ps
CPU time 2.19 seconds
Started Jan 24 02:51:21 PM PST 24
Finished Jan 24 02:51:30 PM PST 24
Peak memory 200684 kb
Host smart-60f6ad4e-619b-47ec-8a6f-d8e911ec0297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420657036 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1420657036
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3304757022
Short name T74
Test name
Test status
Simulation time 459519728 ps
CPU time 1.72 seconds
Started Jan 24 02:51:20 PM PST 24
Finished Jan 24 02:51:29 PM PST 24
Peak memory 200524 kb
Host smart-0494e666-b976-4911-97bc-13fb3d381a04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304757022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3304757022
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3433668182
Short name T183
Test name
Test status
Simulation time 410730452 ps
CPU time 0.69 seconds
Started Jan 24 02:51:22 PM PST 24
Finished Jan 24 02:51:29 PM PST 24
Peak memory 200496 kb
Host smart-8a10704b-7be9-4c19-b617-2e1228c3fdfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433668182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3433668182
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.842694178
Short name T861
Test name
Test status
Simulation time 2847780149 ps
CPU time 1.29 seconds
Started Jan 24 02:51:19 PM PST 24
Finished Jan 24 02:51:28 PM PST 24
Peak memory 200664 kb
Host smart-455149ba-c7f4-4596-b2ac-8c44c5e9d6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842694178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.842694178
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.50502934
Short name T185
Test name
Test status
Simulation time 811568474 ps
CPU time 1.96 seconds
Started Jan 24 02:51:23 PM PST 24
Finished Jan 24 02:51:35 PM PST 24
Peak memory 200864 kb
Host smart-1f50cc6d-247a-4f51-80a2-f813989bd9dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50502934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.50502934
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.846211198
Short name T870
Test name
Test status
Simulation time 8590481833 ps
CPU time 7.87 seconds
Started Jan 24 02:51:22 PM PST 24
Finished Jan 24 02:51:37 PM PST 24
Peak memory 200848 kb
Host smart-e6babaec-cde7-4193-bf0e-0c6b4616e56d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846211198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.846211198
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.590886728
Short name T405
Test name
Test status
Simulation time 556351255 ps
CPU time 1.19 seconds
Started Jan 24 02:51:28 PM PST 24
Finished Jan 24 02:51:40 PM PST 24
Peak memory 200584 kb
Host smart-04c6d228-4577-4133-8c65-533659bff233
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590886728 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.590886728
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1037267906
Short name T876
Test name
Test status
Simulation time 478997976 ps
CPU time 0.98 seconds
Started Jan 24 02:51:20 PM PST 24
Finished Jan 24 02:51:29 PM PST 24
Peak memory 200528 kb
Host smart-9b25b397-6ee5-4b0c-9f2e-45191ebd72c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037267906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1037267906
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3799962430
Short name T31
Test name
Test status
Simulation time 369850204 ps
CPU time 1.54 seconds
Started Jan 24 02:51:22 PM PST 24
Finished Jan 24 02:51:30 PM PST 24
Peak memory 200480 kb
Host smart-f398b4a5-a185-4c1e-8e43-a423966a8c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799962430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3799962430
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1378703446
Short name T7
Test name
Test status
Simulation time 2717519435 ps
CPU time 5.27 seconds
Started Jan 24 02:51:22 PM PST 24
Finished Jan 24 02:51:34 PM PST 24
Peak memory 200688 kb
Host smart-ac0e8748-ea84-4642-a183-b98b7a60ad38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378703446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1378703446
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.993675059
Short name T900
Test name
Test status
Simulation time 937831769 ps
CPU time 2.36 seconds
Started Jan 24 02:51:25 PM PST 24
Finished Jan 24 02:51:37 PM PST 24
Peak memory 200792 kb
Host smart-8d1a19b7-e58f-4f3a-bfd2-ffbf4e49aab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993675059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.993675059
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3594648419
Short name T355
Test name
Test status
Simulation time 4723582995 ps
CPU time 7.37 seconds
Started Jan 24 02:51:20 PM PST 24
Finished Jan 24 02:51:35 PM PST 24
Peak memory 200888 kb
Host smart-4e2d323a-e91b-4afd-acbf-687ebc30722b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594648419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3594648419
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1394292394
Short name T186
Test name
Test status
Simulation time 550018351 ps
CPU time 1.12 seconds
Started Jan 24 02:51:21 PM PST 24
Finished Jan 24 02:51:30 PM PST 24
Peak memory 200632 kb
Host smart-a863e30a-2875-4231-a2d2-850db6f02483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394292394 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1394292394
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1793612254
Short name T78
Test name
Test status
Simulation time 531295970 ps
CPU time 1.37 seconds
Started Jan 24 02:51:33 PM PST 24
Finished Jan 24 02:51:46 PM PST 24
Peak memory 200492 kb
Host smart-0efef9db-d69b-4bb0-ad4e-c87ced200a6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793612254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1793612254
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2964114032
Short name T384
Test name
Test status
Simulation time 311827207 ps
CPU time 0.96 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:45 PM PST 24
Peak memory 200492 kb
Host smart-1254ec30-594a-4e8a-9607-0bc45fabb6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964114032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2964114032
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3631095510
Short name T411
Test name
Test status
Simulation time 4443136381 ps
CPU time 9.37 seconds
Started Jan 24 05:37:27 PM PST 24
Finished Jan 24 05:37:37 PM PST 24
Peak memory 200860 kb
Host smart-034dfe88-bf5d-4bae-b04f-cd696764c3ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631095510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3631095510
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2152262085
Short name T397
Test name
Test status
Simulation time 522204681 ps
CPU time 1.76 seconds
Started Jan 24 02:51:23 PM PST 24
Finished Jan 24 02:51:32 PM PST 24
Peak memory 200876 kb
Host smart-6cc7774a-7f43-45a8-82de-870aa443c538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152262085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2152262085
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.732043395
Short name T1
Test name
Test status
Simulation time 4300619017 ps
CPU time 6.71 seconds
Started Jan 24 02:51:27 PM PST 24
Finished Jan 24 02:51:45 PM PST 24
Peak memory 200804 kb
Host smart-52b3c7ef-e8d4-40e9-bed5-abd326b74b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732043395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.732043395
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3240005150
Short name T403
Test name
Test status
Simulation time 466799572 ps
CPU time 1.41 seconds
Started Jan 24 02:51:22 PM PST 24
Finished Jan 24 02:51:30 PM PST 24
Peak memory 200644 kb
Host smart-1191506f-0fe6-43ce-891d-43ec6fea7421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240005150 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3240005150
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3838137915
Short name T76
Test name
Test status
Simulation time 455903442 ps
CPU time 1.73 seconds
Started Jan 24 02:51:32 PM PST 24
Finished Jan 24 02:51:46 PM PST 24
Peak memory 200488 kb
Host smart-a113be2c-2684-46d0-ad2f-db62f68256f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838137915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3838137915
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3507448545
Short name T906
Test name
Test status
Simulation time 343770330 ps
CPU time 0.86 seconds
Started Jan 24 02:51:23 PM PST 24
Finished Jan 24 02:51:31 PM PST 24
Peak memory 200088 kb
Host smart-5e532b95-9bf0-4ecf-b18d-453cdeaac172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507448545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3507448545
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3621446425
Short name T416
Test name
Test status
Simulation time 2375934466 ps
CPU time 3.1 seconds
Started Jan 24 02:51:22 PM PST 24
Finished Jan 24 02:51:32 PM PST 24
Peak memory 200672 kb
Host smart-3bf4bc75-ac79-4345-b544-2c6209a7f0ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621446425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3621446425
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1615412236
Short name T889
Test name
Test status
Simulation time 7767461422 ps
CPU time 12.07 seconds
Started Jan 24 02:51:22 PM PST 24
Finished Jan 24 02:51:41 PM PST 24
Peak memory 200816 kb
Host smart-0d46b2eb-df9b-450b-8709-690cbacabae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615412236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1615412236
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1529143674
Short name T30
Test name
Test status
Simulation time 429559914 ps
CPU time 0.99 seconds
Started Jan 24 02:51:28 PM PST 24
Finished Jan 24 02:51:40 PM PST 24
Peak memory 200564 kb
Host smart-8cde0307-af1e-4829-a637-a9da94fb50bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529143674 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1529143674
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.883151158
Short name T83
Test name
Test status
Simulation time 554358139 ps
CPU time 2.06 seconds
Started Jan 24 02:51:22 PM PST 24
Finished Jan 24 02:51:31 PM PST 24
Peak memory 200540 kb
Host smart-5f90baaf-2545-456f-b615-fb9461cf8b4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883151158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.883151158
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3680208848
Short name T856
Test name
Test status
Simulation time 369961452 ps
CPU time 1.54 seconds
Started Jan 24 02:51:20 PM PST 24
Finished Jan 24 02:51:29 PM PST 24
Peak memory 200480 kb
Host smart-48860fdb-645f-4e28-a4ca-7f9436cf4c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680208848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3680208848
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1471095781
Short name T874
Test name
Test status
Simulation time 2246550864 ps
CPU time 3.81 seconds
Started Jan 24 02:51:24 PM PST 24
Finished Jan 24 02:51:37 PM PST 24
Peak memory 200640 kb
Host smart-ae7140aa-1f7b-45f0-b79a-40992c73ace4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471095781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1471095781
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2592191343
Short name T359
Test name
Test status
Simulation time 8590951204 ps
CPU time 7.69 seconds
Started Jan 24 02:51:24 PM PST 24
Finished Jan 24 02:51:41 PM PST 24
Peak memory 200848 kb
Host smart-4ed119be-7eb0-4bd6-be65-732c1ab8ecaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592191343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2592191343
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1148056711
Short name T730
Test name
Test status
Simulation time 308224604 ps
CPU time 1.46 seconds
Started Jan 24 07:07:27 PM PST 24
Finished Jan 24 07:07:29 PM PST 24
Peak memory 200824 kb
Host smart-9c2928fe-66b4-48d8-86ac-4985a40db7e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148056711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1148056711
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4043364594
Short name T824
Test name
Test status
Simulation time 163851492563 ps
CPU time 342.51 seconds
Started Jan 24 07:07:09 PM PST 24
Finished Jan 24 07:12:53 PM PST 24
Peak memory 201188 kb
Host smart-c5314e12-5bee-4ccd-8774-08c13080bac7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043364594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4043364594
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.57713658
Short name T112
Test name
Test status
Simulation time 325825463613 ps
CPU time 768.69 seconds
Started Jan 24 07:07:07 PM PST 24
Finished Jan 24 07:19:56 PM PST 24
Peak memory 201260 kb
Host smart-857a9779-4567-4bd2-9002-f0a5ac0929dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57713658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.57713658
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3653541355
Short name T772
Test name
Test status
Simulation time 488019376242 ps
CPU time 1066.78 seconds
Started Jan 24 07:06:59 PM PST 24
Finished Jan 24 07:24:48 PM PST 24
Peak memory 201156 kb
Host smart-ed6ec41f-5767-4125-bf03-fef559aea977
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653541355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3653541355
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.493654317
Short name T160
Test name
Test status
Simulation time 484728636156 ps
CPU time 308.48 seconds
Started Jan 24 07:28:04 PM PST 24
Finished Jan 24 07:33:13 PM PST 24
Peak memory 201196 kb
Host smart-5abb5df6-8b27-4cad-adf7-102c6e8326e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493654317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.493654317
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3703821437
Short name T527
Test name
Test status
Simulation time 159823019421 ps
CPU time 102.47 seconds
Started Jan 24 07:07:01 PM PST 24
Finished Jan 24 07:08:46 PM PST 24
Peak memory 201280 kb
Host smart-5c486b86-a680-4c13-a235-ee4eb1a1d63a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703821437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3703821437
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3192434350
Short name T542
Test name
Test status
Simulation time 491630191924 ps
CPU time 1217.25 seconds
Started Jan 24 07:15:10 PM PST 24
Finished Jan 24 07:35:29 PM PST 24
Peak memory 201228 kb
Host smart-312482d4-70b1-45db-b128-b73c3ef5f9ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192434350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3192434350
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.4246901348
Short name T199
Test name
Test status
Simulation time 111606494590 ps
CPU time 351.32 seconds
Started Jan 24 07:07:08 PM PST 24
Finished Jan 24 07:13:00 PM PST 24
Peak memory 201376 kb
Host smart-a2a939d3-13e3-44d9-b36f-c3cc722d01fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246901348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4246901348
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1265981614
Short name T494
Test name
Test status
Simulation time 43600170942 ps
CPU time 97.24 seconds
Started Jan 24 07:07:08 PM PST 24
Finished Jan 24 07:08:46 PM PST 24
Peak memory 200916 kb
Host smart-dfb55323-1efa-4c9f-96d6-cb83429cb5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265981614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1265981614
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.257356727
Short name T530
Test name
Test status
Simulation time 4756571120 ps
CPU time 11.85 seconds
Started Jan 24 08:52:46 PM PST 24
Finished Jan 24 08:53:03 PM PST 24
Peak memory 201060 kb
Host smart-ffc96a54-17d2-4571-8142-e15bcc457bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257356727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.257356727
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1179218433
Short name T50
Test name
Test status
Simulation time 7739380331 ps
CPU time 17.86 seconds
Started Jan 24 07:07:29 PM PST 24
Finished Jan 24 07:07:48 PM PST 24
Peak memory 217384 kb
Host smart-7456cfc0-8f7c-4bae-bce0-2bedea676879
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179218433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1179218433
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.166837996
Short name T605
Test name
Test status
Simulation time 5917247204 ps
CPU time 3.95 seconds
Started Jan 24 07:06:57 PM PST 24
Finished Jan 24 07:07:02 PM PST 24
Peak memory 200952 kb
Host smart-c3996d7d-ffcd-4494-9b8a-d6315087204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166837996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.166837996
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2260997743
Short name T322
Test name
Test status
Simulation time 176813103420 ps
CPU time 102.73 seconds
Started Jan 24 07:07:28 PM PST 24
Finished Jan 24 07:09:11 PM PST 24
Peak memory 209432 kb
Host smart-c1a21e16-edb9-486a-8e07-6c0bb40d8383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260997743 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2260997743
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3800929200
Short name T783
Test name
Test status
Simulation time 368803582 ps
CPU time 1.46 seconds
Started Jan 24 07:07:41 PM PST 24
Finished Jan 24 07:07:44 PM PST 24
Peak memory 200912 kb
Host smart-94e8d502-154a-4bb7-a2c3-ccd0fce3000d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800929200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3800929200
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1298376397
Short name T763
Test name
Test status
Simulation time 169896229911 ps
CPU time 410.57 seconds
Started Jan 24 07:26:05 PM PST 24
Finished Jan 24 07:32:57 PM PST 24
Peak memory 201228 kb
Host smart-93c00067-ca69-431f-abf8-0c1913f33b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298376397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1298376397
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1000674223
Short name T214
Test name
Test status
Simulation time 323801527198 ps
CPU time 750.01 seconds
Started Jan 24 09:30:25 PM PST 24
Finished Jan 24 09:42:56 PM PST 24
Peak memory 201172 kb
Host smart-0cdeb023-18a9-48d1-8875-a5a7cfb277ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000674223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1000674223
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3417988466
Short name T500
Test name
Test status
Simulation time 161631118466 ps
CPU time 379.56 seconds
Started Jan 24 10:42:54 PM PST 24
Finished Jan 24 10:49:15 PM PST 24
Peak memory 201240 kb
Host smart-5306ab66-28b7-437b-af33-4130d25926c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417988466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3417988466
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1070722606
Short name T727
Test name
Test status
Simulation time 327048722248 ps
CPU time 354.08 seconds
Started Jan 24 07:07:27 PM PST 24
Finished Jan 24 07:13:21 PM PST 24
Peak memory 201192 kb
Host smart-fc457004-6a44-4c7f-a9d1-464b2cd59a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070722606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1070722606
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.246934740
Short name T731
Test name
Test status
Simulation time 163997345363 ps
CPU time 83.51 seconds
Started Jan 24 07:31:01 PM PST 24
Finished Jan 24 07:32:28 PM PST 24
Peak memory 201232 kb
Host smart-0ab2dac7-f0ea-4cfd-9a2c-e8c851f79633
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=246934740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.246934740
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3845820181
Short name T576
Test name
Test status
Simulation time 493747182371 ps
CPU time 1158.62 seconds
Started Jan 24 07:07:31 PM PST 24
Finished Jan 24 07:26:51 PM PST 24
Peak memory 201140 kb
Host smart-11b9a2bd-3037-4c33-a2c4-9f56dd87ef20
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845820181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3845820181
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2904836135
Short name T375
Test name
Test status
Simulation time 96366409679 ps
CPU time 298.28 seconds
Started Jan 24 07:07:30 PM PST 24
Finished Jan 24 07:12:30 PM PST 24
Peak memory 201476 kb
Host smart-595e9c83-b5dd-4359-b640-42dbda4ace01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904836135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2904836135
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1067925545
Short name T468
Test name
Test status
Simulation time 25979074532 ps
CPU time 30.96 seconds
Started Jan 24 07:07:29 PM PST 24
Finished Jan 24 07:08:02 PM PST 24
Peak memory 201008 kb
Host smart-0fe7e076-f725-45f0-8855-2c3d0eb411ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067925545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1067925545
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.705918864
Short name T521
Test name
Test status
Simulation time 5974320973 ps
CPU time 15.1 seconds
Started Jan 24 07:07:29 PM PST 24
Finished Jan 24 07:07:46 PM PST 24
Peak memory 200956 kb
Host smart-b6d6f422-d376-414f-98db-a6a3e83ba782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705918864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.705918864
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3392306722
Short name T371
Test name
Test status
Simulation time 453702893736 ps
CPU time 940.03 seconds
Started Jan 24 07:07:42 PM PST 24
Finished Jan 24 07:23:23 PM PST 24
Peak memory 210732 kb
Host smart-e2fcff9e-64e1-406c-ad60-3a1d60b156f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392306722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3392306722
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2597681905
Short name T363
Test name
Test status
Simulation time 46311308191 ps
CPU time 176.71 seconds
Started Jan 24 07:07:40 PM PST 24
Finished Jan 24 07:10:39 PM PST 24
Peak memory 210940 kb
Host smart-660408ea-889d-4648-a59a-eeb7d3b43a93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597681905 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2597681905
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1494767338
Short name T519
Test name
Test status
Simulation time 509550399 ps
CPU time 1.86 seconds
Started Jan 24 07:10:51 PM PST 24
Finished Jan 24 07:10:54 PM PST 24
Peak memory 200904 kb
Host smart-0ae583d3-9a60-43f4-9287-14338ea25987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494767338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1494767338
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1137108973
Short name T831
Test name
Test status
Simulation time 164833127344 ps
CPU time 91.07 seconds
Started Jan 24 07:10:32 PM PST 24
Finished Jan 24 07:12:03 PM PST 24
Peak memory 201240 kb
Host smart-b79f3b2a-181f-40ee-b28d-466552ece910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137108973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1137108973
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1707303021
Short name T754
Test name
Test status
Simulation time 494370735891 ps
CPU time 1074.24 seconds
Started Jan 24 07:10:26 PM PST 24
Finished Jan 24 07:28:21 PM PST 24
Peak memory 201080 kb
Host smart-0e3b2463-23d5-4407-9200-431663d9e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707303021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1707303021
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2768689615
Short name T498
Test name
Test status
Simulation time 317733791520 ps
CPU time 752.8 seconds
Started Jan 24 07:18:11 PM PST 24
Finished Jan 24 07:30:45 PM PST 24
Peak memory 201192 kb
Host smart-04ba12f8-ce31-4557-9d6c-8681d98ce87f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768689615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2768689615
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3672686461
Short name T447
Test name
Test status
Simulation time 487820156349 ps
CPU time 63.91 seconds
Started Jan 24 07:10:19 PM PST 24
Finished Jan 24 07:11:23 PM PST 24
Peak memory 201064 kb
Host smart-31119529-a78d-4696-a865-351d35671190
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672686461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3672686461
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.919904672
Short name T233
Test name
Test status
Simulation time 329678355698 ps
CPU time 762.17 seconds
Started Jan 24 07:10:37 PM PST 24
Finished Jan 24 07:23:20 PM PST 24
Peak memory 201072 kb
Host smart-a7bb3c8d-c362-45bb-bb19-69121cfcfeb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919904672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.919904672
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2234358186
Short name T760
Test name
Test status
Simulation time 481924207548 ps
CPU time 597.25 seconds
Started Jan 24 07:10:33 PM PST 24
Finished Jan 24 07:20:31 PM PST 24
Peak memory 201180 kb
Host smart-5139ae4e-af0d-42d9-bb98-cb182fb4c355
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234358186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2234358186
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2195423803
Short name T473
Test name
Test status
Simulation time 126667504990 ps
CPU time 446.01 seconds
Started Jan 24 07:10:51 PM PST 24
Finished Jan 24 07:18:18 PM PST 24
Peak memory 201504 kb
Host smart-47adf8a2-2ebc-46a3-8b89-2f934bc6873d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195423803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2195423803
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.379542869
Short name T652
Test name
Test status
Simulation time 31373859934 ps
CPU time 35.72 seconds
Started Jan 24 07:10:42 PM PST 24
Finished Jan 24 07:11:18 PM PST 24
Peak memory 200924 kb
Host smart-427e3d1c-1ba8-4d60-ba0e-875242b328f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379542869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.379542869
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2374833034
Short name T492
Test name
Test status
Simulation time 5419282661 ps
CPU time 12.59 seconds
Started Jan 24 07:10:43 PM PST 24
Finished Jan 24 07:10:56 PM PST 24
Peak memory 201032 kb
Host smart-83a4de6e-324e-4240-8209-29c42ff4439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374833034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2374833034
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.340719971
Short name T707
Test name
Test status
Simulation time 5726802182 ps
CPU time 13.55 seconds
Started Jan 24 07:26:46 PM PST 24
Finished Jan 24 07:27:01 PM PST 24
Peak memory 200984 kb
Host smart-70bb70f5-e0de-49cc-b3db-c66e28994cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340719971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.340719971
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1736619292
Short name T757
Test name
Test status
Simulation time 330941653424 ps
CPU time 188.1 seconds
Started Jan 24 07:10:49 PM PST 24
Finished Jan 24 07:13:58 PM PST 24
Peak memory 201184 kb
Host smart-f7181687-b98f-4495-9727-06b9d3b643fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736619292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1736619292
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2759899425
Short name T302
Test name
Test status
Simulation time 120574438271 ps
CPU time 45.54 seconds
Started Jan 24 07:10:53 PM PST 24
Finished Jan 24 07:11:39 PM PST 24
Peak memory 209512 kb
Host smart-08d35a0e-5b18-4621-b531-6d5e3eb3dfc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759899425 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2759899425
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.827389404
Short name T491
Test name
Test status
Simulation time 363796651 ps
CPU time 1.02 seconds
Started Jan 24 07:11:12 PM PST 24
Finished Jan 24 07:11:16 PM PST 24
Peak memory 200900 kb
Host smart-47a351a9-869b-4e60-a7e6-983c8a4546ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827389404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.827389404
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.26473206
Short name T342
Test name
Test status
Simulation time 338804419848 ps
CPU time 680.49 seconds
Started Jan 24 07:11:04 PM PST 24
Finished Jan 24 07:22:26 PM PST 24
Peak memory 201168 kb
Host smart-8f0a91e1-dfb7-4100-978a-dfd6b2f3e64b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26473206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gatin
g.26473206
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.730854775
Short name T172
Test name
Test status
Simulation time 328036749899 ps
CPU time 70.68 seconds
Started Jan 24 07:37:15 PM PST 24
Finished Jan 24 07:38:26 PM PST 24
Peak memory 201284 kb
Host smart-ebf174db-fa0f-474f-96cd-1d2658e64a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730854775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.730854775
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.8053180
Short name T175
Test name
Test status
Simulation time 333440239586 ps
CPU time 193.05 seconds
Started Jan 24 09:54:06 PM PST 24
Finished Jan 24 09:57:20 PM PST 24
Peak memory 201236 kb
Host smart-a4e80f61-25fd-4085-b21c-09b02a8fe831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8053180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.8053180
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2263899165
Short name T794
Test name
Test status
Simulation time 497625653675 ps
CPU time 578.56 seconds
Started Jan 24 07:10:55 PM PST 24
Finished Jan 24 07:20:35 PM PST 24
Peak memory 201180 kb
Host smart-7c733a3e-6f26-47c3-820f-9c90c0f01ad8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263899165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2263899165
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.247933305
Short name T695
Test name
Test status
Simulation time 331038538609 ps
CPU time 406.88 seconds
Started Jan 24 07:11:00 PM PST 24
Finished Jan 24 07:17:48 PM PST 24
Peak memory 201080 kb
Host smart-f5af8058-bae0-436d-ba4a-8b9745f6b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247933305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.247933305
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.237360447
Short name T501
Test name
Test status
Simulation time 166396032980 ps
CPU time 340.84 seconds
Started Jan 24 07:11:00 PM PST 24
Finished Jan 24 07:16:41 PM PST 24
Peak memory 201128 kb
Host smart-62610483-1b2b-4319-b4d0-600e17a84d27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=237360447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.237360447
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.737968680
Short name T255
Test name
Test status
Simulation time 163942684330 ps
CPU time 99.91 seconds
Started Jan 24 07:11:07 PM PST 24
Finished Jan 24 07:12:48 PM PST 24
Peak memory 201176 kb
Host smart-ab1619bc-7905-4016-96c3-d48547ccf695
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737968680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.737968680
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2575868479
Short name T586
Test name
Test status
Simulation time 332073238431 ps
CPU time 750.88 seconds
Started Jan 24 07:11:05 PM PST 24
Finished Jan 24 07:23:38 PM PST 24
Peak memory 201220 kb
Host smart-97a0b639-413f-4f07-945c-5cac2fe47bba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575868479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2575868479
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4119391432
Short name T844
Test name
Test status
Simulation time 95632411978 ps
CPU time 420.85 seconds
Started Jan 24 07:11:07 PM PST 24
Finished Jan 24 07:18:09 PM PST 24
Peak memory 201548 kb
Host smart-822f9ca4-441f-4d92-bc92-2bd679d0bed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119391432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4119391432
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2199961905
Short name T499
Test name
Test status
Simulation time 34183308035 ps
CPU time 20.91 seconds
Started Jan 24 07:11:07 PM PST 24
Finished Jan 24 07:11:29 PM PST 24
Peak memory 201032 kb
Host smart-c46c0d40-4b91-4231-84f0-6d71b30a33c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199961905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2199961905
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3145251664
Short name T622
Test name
Test status
Simulation time 4292438967 ps
CPU time 2.68 seconds
Started Jan 24 07:11:06 PM PST 24
Finished Jan 24 07:11:10 PM PST 24
Peak memory 200924 kb
Host smart-899bbc54-9a1a-449b-9b20-ed070356433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145251664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3145251664
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3519196137
Short name T493
Test name
Test status
Simulation time 5560930355 ps
CPU time 9.01 seconds
Started Jan 24 07:10:58 PM PST 24
Finished Jan 24 07:11:08 PM PST 24
Peak memory 200992 kb
Host smart-faa7ec1c-d7e4-4436-9d5a-9d786e0695cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519196137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3519196137
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1891470457
Short name T20
Test name
Test status
Simulation time 104514694802 ps
CPU time 86.16 seconds
Started Jan 24 07:38:49 PM PST 24
Finished Jan 24 07:40:23 PM PST 24
Peak memory 201328 kb
Host smart-6bed1b3d-db42-46ee-b39a-cde5b34efa7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891470457 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1891470457
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1990538144
Short name T826
Test name
Test status
Simulation time 501769634 ps
CPU time 1.75 seconds
Started Jan 24 07:11:44 PM PST 24
Finished Jan 24 07:11:47 PM PST 24
Peak memory 200900 kb
Host smart-2c182ea2-cd4e-4dfb-8715-377877bfacb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990538144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1990538144
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3333785910
Short name T129
Test name
Test status
Simulation time 180664886469 ps
CPU time 101.38 seconds
Started Jan 24 07:11:22 PM PST 24
Finished Jan 24 07:13:13 PM PST 24
Peak memory 201260 kb
Host smart-3c6a68c8-c340-4049-9b13-55523fd5b431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333785910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3333785910
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3798396956
Short name T210
Test name
Test status
Simulation time 332356853545 ps
CPU time 190.63 seconds
Started Jan 24 09:55:05 PM PST 24
Finished Jan 24 09:58:26 PM PST 24
Peak memory 201252 kb
Host smart-dfb53f85-b7a6-4acf-8a04-81729cafdf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798396956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3798396956
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3327894031
Short name T795
Test name
Test status
Simulation time 164014183370 ps
CPU time 113.97 seconds
Started Jan 24 07:43:55 PM PST 24
Finished Jan 24 07:45:49 PM PST 24
Peak memory 201196 kb
Host smart-424e7952-2d8c-4ae9-b40e-85fba00d25f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327894031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3327894031
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1250967605
Short name T89
Test name
Test status
Simulation time 322640306842 ps
CPU time 186.98 seconds
Started Jan 24 07:11:13 PM PST 24
Finished Jan 24 07:14:23 PM PST 24
Peak memory 201284 kb
Host smart-f1c1f5d7-2c8f-4652-8f33-cc57c367a4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250967605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1250967605
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2283542472
Short name T790
Test name
Test status
Simulation time 156826611843 ps
CPU time 179.89 seconds
Started Jan 24 07:11:20 PM PST 24
Finished Jan 24 07:14:29 PM PST 24
Peak memory 201096 kb
Host smart-c671dab9-c341-4162-a960-729e7484991b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283542472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2283542472
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3201044662
Short name T328
Test name
Test status
Simulation time 497518148465 ps
CPU time 300.31 seconds
Started Jan 24 09:01:10 PM PST 24
Finished Jan 24 09:06:14 PM PST 24
Peak memory 201252 kb
Host smart-0a5b016a-7c52-4a01-8068-33e6c4bc48d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201044662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3201044662
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2165729249
Short name T372
Test name
Test status
Simulation time 84395270588 ps
CPU time 368.45 seconds
Started Jan 24 07:11:31 PM PST 24
Finished Jan 24 07:17:46 PM PST 24
Peak memory 201476 kb
Host smart-c11c236d-5fab-4d85-aeac-8e8ad250b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165729249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2165729249
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.700381358
Short name T543
Test name
Test status
Simulation time 26122494614 ps
CPU time 16.6 seconds
Started Jan 24 07:11:32 PM PST 24
Finished Jan 24 07:11:54 PM PST 24
Peak memory 201028 kb
Host smart-14d507a7-3c4f-4498-8376-c28266645cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700381358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.700381358
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.889699272
Short name T852
Test name
Test status
Simulation time 3872882242 ps
CPU time 10.31 seconds
Started Jan 24 07:11:27 PM PST 24
Finished Jan 24 07:11:45 PM PST 24
Peak memory 201024 kb
Host smart-6db50499-77f9-4a40-8922-7122f9fcb3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889699272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.889699272
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3074753276
Short name T833
Test name
Test status
Simulation time 5761667399 ps
CPU time 2.4 seconds
Started Jan 24 08:11:16 PM PST 24
Finished Jan 24 08:11:19 PM PST 24
Peak memory 201056 kb
Host smart-dc449538-f13d-4e79-a2c3-4efed9d979d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074753276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3074753276
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.316286755
Short name T629
Test name
Test status
Simulation time 546668611 ps
CPU time 0.88 seconds
Started Jan 24 07:12:10 PM PST 24
Finished Jan 24 07:12:14 PM PST 24
Peak memory 200888 kb
Host smart-b4a39f0a-cb25-479c-a770-ea4d11aa3584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316286755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.316286755
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.230297225
Short name T222
Test name
Test status
Simulation time 330218743567 ps
CPU time 221.89 seconds
Started Jan 24 07:11:56 PM PST 24
Finished Jan 24 07:15:41 PM PST 24
Peak memory 201148 kb
Host smart-0e9f030f-54dc-4aa2-82fc-be6354a306cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230297225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.230297225
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3683595805
Short name T224
Test name
Test status
Simulation time 328405577731 ps
CPU time 191.22 seconds
Started Jan 24 07:11:51 PM PST 24
Finished Jan 24 07:15:06 PM PST 24
Peak memory 201192 kb
Host smart-41002797-c99c-479b-b8f8-355cdc3b662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683595805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3683595805
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2404352965
Short name T541
Test name
Test status
Simulation time 487728212296 ps
CPU time 1089.41 seconds
Started Jan 24 07:11:49 PM PST 24
Finished Jan 24 07:30:01 PM PST 24
Peak memory 201080 kb
Host smart-8228e23f-f5e3-4ccc-99e5-25a166324d99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404352965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2404352965
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2650219487
Short name T337
Test name
Test status
Simulation time 161181197035 ps
CPU time 367.53 seconds
Started Jan 24 07:11:44 PM PST 24
Finished Jan 24 07:17:53 PM PST 24
Peak memory 201164 kb
Host smart-54b39360-ef45-44b8-a06a-edc524aa748e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650219487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2650219487
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2585878220
Short name T838
Test name
Test status
Simulation time 161834338926 ps
CPU time 92.44 seconds
Started Jan 24 07:11:41 PM PST 24
Finished Jan 24 07:13:14 PM PST 24
Peak memory 201116 kb
Host smart-c6b1563a-5c47-4ff5-9d6d-6bccbb5bafcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585878220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2585878220
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1021837799
Short name T565
Test name
Test status
Simulation time 485667317614 ps
CPU time 269.79 seconds
Started Jan 24 07:11:57 PM PST 24
Finished Jan 24 07:16:29 PM PST 24
Peak memory 201116 kb
Host smart-d137f895-35f3-4615-ae75-3ced84ab0e64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021837799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1021837799
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3560531807
Short name T464
Test name
Test status
Simulation time 325148338673 ps
CPU time 793.46 seconds
Started Jan 24 07:11:57 PM PST 24
Finished Jan 24 07:25:13 PM PST 24
Peak memory 201264 kb
Host smart-8f3c3f13-9c5a-40dc-b68a-6a30286e6710
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560531807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3560531807
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1257235357
Short name T523
Test name
Test status
Simulation time 132706648082 ps
CPU time 516.66 seconds
Started Jan 24 07:12:06 PM PST 24
Finished Jan 24 07:20:44 PM PST 24
Peak memory 201488 kb
Host smart-fef34b08-4f72-4a62-a8b9-82537d51a3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257235357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1257235357
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2497466484
Short name T643
Test name
Test status
Simulation time 25007015060 ps
CPU time 14.92 seconds
Started Jan 24 07:12:10 PM PST 24
Finished Jan 24 07:12:28 PM PST 24
Peak memory 201024 kb
Host smart-fa81b305-c66c-45f8-b6cf-d1719230435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497466484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2497466484
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.159026026
Short name T747
Test name
Test status
Simulation time 3700717948 ps
CPU time 6.49 seconds
Started Jan 24 07:34:48 PM PST 24
Finished Jan 24 07:34:57 PM PST 24
Peak memory 201060 kb
Host smart-74711156-4e34-4b5d-b00e-77a1b63736e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159026026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.159026026
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.101007167
Short name T554
Test name
Test status
Simulation time 6071213917 ps
CPU time 4.53 seconds
Started Jan 24 07:23:08 PM PST 24
Finished Jan 24 07:23:14 PM PST 24
Peak memory 200980 kb
Host smart-507775ee-81a1-422f-a03d-d8140abaf180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101007167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.101007167
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.449638074
Short name T292
Test name
Test status
Simulation time 730390230686 ps
CPU time 1424.92 seconds
Started Jan 24 07:12:10 PM PST 24
Finished Jan 24 07:35:58 PM PST 24
Peak memory 201536 kb
Host smart-ce38d623-c159-4e3b-96f2-903df3db7213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449638074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
449638074
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3861879196
Short name T815
Test name
Test status
Simulation time 358348840713 ps
CPU time 456.37 seconds
Started Jan 24 07:12:08 PM PST 24
Finished Jan 24 07:19:50 PM PST 24
Peak memory 209764 kb
Host smart-70d31fb5-822f-4f5d-9a87-80af71d0a6cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861879196 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3861879196
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3486156435
Short name T785
Test name
Test status
Simulation time 333685671431 ps
CPU time 183.24 seconds
Started Jan 24 07:12:23 PM PST 24
Finished Jan 24 07:15:27 PM PST 24
Peak memory 201184 kb
Host smart-e245bf8b-5628-495f-8c5a-1ca829ab785f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486156435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3486156435
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1267406266
Short name T143
Test name
Test status
Simulation time 323290529370 ps
CPU time 159.32 seconds
Started Jan 24 07:12:21 PM PST 24
Finished Jan 24 07:15:01 PM PST 24
Peak memory 201180 kb
Host smart-29cf2aea-c50c-42e3-9a1c-cbf22a9d8656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267406266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1267406266
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3238672747
Short name T682
Test name
Test status
Simulation time 167567478043 ps
CPU time 203.46 seconds
Started Jan 24 07:12:21 PM PST 24
Finished Jan 24 07:15:46 PM PST 24
Peak memory 201188 kb
Host smart-72216012-c260-49ba-b4f8-2edc6c1670f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238672747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3238672747
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1441506845
Short name T506
Test name
Test status
Simulation time 500359827674 ps
CPU time 1147.89 seconds
Started Jan 24 07:12:23 PM PST 24
Finished Jan 24 07:31:32 PM PST 24
Peak memory 201232 kb
Host smart-6404347f-1ab0-4f80-8fe8-4432a4be7c56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441506845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1441506845
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2299267865
Short name T604
Test name
Test status
Simulation time 157612587914 ps
CPU time 97.94 seconds
Started Jan 24 07:35:05 PM PST 24
Finished Jan 24 07:36:51 PM PST 24
Peak memory 201272 kb
Host smart-991764e8-21df-4b72-920b-ca4911add0ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299267865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2299267865
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2640780439
Short name T654
Test name
Test status
Simulation time 326850846905 ps
CPU time 195.04 seconds
Started Jan 24 07:12:22 PM PST 24
Finished Jan 24 07:15:39 PM PST 24
Peak memory 201244 kb
Host smart-89f96deb-5e92-4e80-b5ec-62a736ef5ad3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640780439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2640780439
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2569473963
Short name T140
Test name
Test status
Simulation time 31175949231 ps
CPU time 69.04 seconds
Started Jan 24 08:39:14 PM PST 24
Finished Jan 24 08:40:24 PM PST 24
Peak memory 201044 kb
Host smart-02275026-5727-46cc-8923-c7015fca39fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569473963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2569473963
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.47186194
Short name T818
Test name
Test status
Simulation time 4494072966 ps
CPU time 11.01 seconds
Started Jan 24 07:12:21 PM PST 24
Finished Jan 24 07:12:33 PM PST 24
Peak memory 200920 kb
Host smart-a6b1d9fd-b9a6-4f43-8994-717d5a2ca911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47186194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.47186194
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3488517238
Short name T553
Test name
Test status
Simulation time 5633514749 ps
CPU time 13.57 seconds
Started Jan 24 07:12:11 PM PST 24
Finished Jan 24 07:12:27 PM PST 24
Peak memory 200888 kb
Host smart-62b1d8ab-9f3f-451e-b155-243d69407dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488517238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3488517238
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3157715479
Short name T608
Test name
Test status
Simulation time 518148185991 ps
CPU time 1191.2 seconds
Started Jan 24 07:12:29 PM PST 24
Finished Jan 24 07:32:22 PM PST 24
Peak memory 201204 kb
Host smart-b61a93b0-a106-4aeb-bcd5-d14d9afe5d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157715479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3157715479
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3032474137
Short name T45
Test name
Test status
Simulation time 289596528 ps
CPU time 0.95 seconds
Started Jan 24 08:33:35 PM PST 24
Finished Jan 24 08:33:37 PM PST 24
Peak memory 200940 kb
Host smart-433770f5-79a5-4104-9b5d-f432addd9aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032474137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3032474137
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2664423812
Short name T268
Test name
Test status
Simulation time 165771336689 ps
CPU time 393.19 seconds
Started Jan 24 07:12:48 PM PST 24
Finished Jan 24 07:19:22 PM PST 24
Peak memory 201236 kb
Host smart-898a0ce1-bc10-452b-86b9-9bc8b49f9cee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664423812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2664423812
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.82690485
Short name T797
Test name
Test status
Simulation time 169154130491 ps
CPU time 413.15 seconds
Started Jan 24 07:12:48 PM PST 24
Finished Jan 24 07:19:42 PM PST 24
Peak memory 201176 kb
Host smart-f6c0c62b-e7f3-403b-b942-bb7c0976f773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82690485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.82690485
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.360376393
Short name T124
Test name
Test status
Simulation time 328929601268 ps
CPU time 747.8 seconds
Started Jan 24 07:31:48 PM PST 24
Finished Jan 24 07:44:21 PM PST 24
Peak memory 201188 kb
Host smart-28df877a-7409-4271-a973-ffb17ff79eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360376393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.360376393
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1895016177
Short name T674
Test name
Test status
Simulation time 504042327690 ps
CPU time 456.46 seconds
Started Jan 24 07:12:51 PM PST 24
Finished Jan 24 07:20:29 PM PST 24
Peak memory 201248 kb
Host smart-428d3253-02c1-4710-8368-92446ea49864
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895016177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1895016177
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1538132592
Short name T161
Test name
Test status
Simulation time 484735537392 ps
CPU time 278.82 seconds
Started Jan 24 07:12:37 PM PST 24
Finished Jan 24 07:17:17 PM PST 24
Peak memory 201260 kb
Host smart-c1723e7c-28a8-48ab-927a-0e97aae870a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538132592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1538132592
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3972660740
Short name T440
Test name
Test status
Simulation time 173300633995 ps
CPU time 94.97 seconds
Started Jan 24 07:12:37 PM PST 24
Finished Jan 24 07:14:13 PM PST 24
Peak memory 201196 kb
Host smart-04576b79-556e-42db-9385-b3c465ce8024
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972660740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3972660740
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2414773862
Short name T123
Test name
Test status
Simulation time 331071995400 ps
CPU time 182.1 seconds
Started Jan 24 07:12:48 PM PST 24
Finished Jan 24 07:15:51 PM PST 24
Peak memory 201180 kb
Host smart-130b4e9c-128b-46e0-bd70-90a511b6b113
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414773862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2414773862
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1338840585
Short name T612
Test name
Test status
Simulation time 494195866112 ps
CPU time 278.25 seconds
Started Jan 24 07:12:46 PM PST 24
Finished Jan 24 07:17:25 PM PST 24
Peak memory 201200 kb
Host smart-478980fa-dcd2-4dc1-a207-0c7dea39327e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338840585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1338840585
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1626880812
Short name T699
Test name
Test status
Simulation time 40864161771 ps
CPU time 49.06 seconds
Started Jan 24 07:12:57 PM PST 24
Finished Jan 24 07:13:46 PM PST 24
Peak memory 201024 kb
Host smart-ed3de6a7-3cca-4f80-ba84-48b449e5c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626880812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1626880812
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.13229950
Short name T602
Test name
Test status
Simulation time 4478725151 ps
CPU time 3.41 seconds
Started Jan 24 07:12:48 PM PST 24
Finished Jan 24 07:12:52 PM PST 24
Peak memory 201020 kb
Host smart-17fe2592-6fdd-4d2a-8c4e-ee94df404ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13229950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.13229950
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1848570745
Short name T804
Test name
Test status
Simulation time 5807958041 ps
CPU time 3.45 seconds
Started Jan 24 07:12:38 PM PST 24
Finished Jan 24 07:12:42 PM PST 24
Peak memory 200868 kb
Host smart-a1299643-dafb-4299-babc-30a0b46ffab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848570745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1848570745
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.206518952
Short name T134
Test name
Test status
Simulation time 367931285278 ps
CPU time 476.94 seconds
Started Jan 24 07:31:31 PM PST 24
Finished Jan 24 07:39:35 PM PST 24
Peak memory 201244 kb
Host smart-cd8e9ffb-1691-4992-946d-65282dfcbf82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206518952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
206518952
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.755383307
Short name T467
Test name
Test status
Simulation time 445710162 ps
CPU time 0.85 seconds
Started Jan 24 07:13:43 PM PST 24
Finished Jan 24 07:13:44 PM PST 24
Peak memory 200916 kb
Host smart-8f9f74e2-a701-4516-991e-169a3fb7f919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755383307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.755383307
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1711765558
Short name T230
Test name
Test status
Simulation time 163670182161 ps
CPU time 23.94 seconds
Started Jan 24 07:13:22 PM PST 24
Finished Jan 24 07:13:47 PM PST 24
Peak memory 201084 kb
Host smart-6501f14c-538e-4da9-a37b-f2c4862bf13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711765558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1711765558
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1556016822
Short name T778
Test name
Test status
Simulation time 330610709547 ps
CPU time 746.19 seconds
Started Jan 24 07:13:20 PM PST 24
Finished Jan 24 07:25:47 PM PST 24
Peak memory 201164 kb
Host smart-713d3d16-a07c-4131-b620-7110dfc3dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556016822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1556016822
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1745916357
Short name T559
Test name
Test status
Simulation time 493733958632 ps
CPU time 303.07 seconds
Started Jan 24 07:13:18 PM PST 24
Finished Jan 24 07:18:21 PM PST 24
Peak memory 201156 kb
Host smart-7da929f1-c087-4c6b-8069-9a7b982314f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745916357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1745916357
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.202309232
Short name T94
Test name
Test status
Simulation time 327074397384 ps
CPU time 422.61 seconds
Started Jan 24 09:15:02 PM PST 24
Finished Jan 24 09:22:06 PM PST 24
Peak memory 201236 kb
Host smart-4d287e20-0b0e-4fbc-98c4-fcc360edcfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202309232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.202309232
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.11007994
Short name T802
Test name
Test status
Simulation time 336290956266 ps
CPU time 688.92 seconds
Started Jan 24 07:13:10 PM PST 24
Finished Jan 24 07:24:40 PM PST 24
Peak memory 201196 kb
Host smart-f6e3b982-fa3f-460f-a3ff-b1e9fe85992c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=11007994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed
.11007994
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.4022888553
Short name T579
Test name
Test status
Simulation time 323549533810 ps
CPU time 438.8 seconds
Started Jan 24 07:13:22 PM PST 24
Finished Jan 24 07:20:41 PM PST 24
Peak memory 201080 kb
Host smart-2266e939-c5f1-4ece-9f25-8efa7ebb35d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022888553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.4022888553
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3094932152
Short name T195
Test name
Test status
Simulation time 74171961150 ps
CPU time 337.39 seconds
Started Jan 24 07:13:34 PM PST 24
Finished Jan 24 07:19:12 PM PST 24
Peak memory 201368 kb
Host smart-bae7e4de-d61a-4b84-96b0-ca3b62f00c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094932152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3094932152
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1474540932
Short name T16
Test name
Test status
Simulation time 22946763292 ps
CPU time 56.54 seconds
Started Jan 24 07:13:22 PM PST 24
Finished Jan 24 07:14:19 PM PST 24
Peak memory 200932 kb
Host smart-aedb0afa-a28f-490b-87ec-846483097a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474540932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1474540932
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2961140724
Short name T828
Test name
Test status
Simulation time 3780522940 ps
CPU time 2.99 seconds
Started Jan 24 07:13:23 PM PST 24
Finished Jan 24 07:13:27 PM PST 24
Peak memory 200992 kb
Host smart-3cc21a4d-6530-4605-8416-e82760a12381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961140724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2961140724
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2873462181
Short name T511
Test name
Test status
Simulation time 5658143312 ps
CPU time 14.07 seconds
Started Jan 24 07:13:01 PM PST 24
Finished Jan 24 07:13:16 PM PST 24
Peak memory 200976 kb
Host smart-0d14f2a4-73bc-4388-86ba-013df77d26dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873462181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2873462181
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1446793595
Short name T303
Test name
Test status
Simulation time 161457312094 ps
CPU time 125.59 seconds
Started Jan 24 07:13:32 PM PST 24
Finished Jan 24 07:15:39 PM PST 24
Peak memory 201172 kb
Host smart-2635a2d6-890f-4865-9b89-e159e7e43b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446793595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1446793595
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1492687370
Short name T306
Test name
Test status
Simulation time 130056958882 ps
CPU time 151.07 seconds
Started Jan 24 07:13:31 PM PST 24
Finished Jan 24 07:16:03 PM PST 24
Peak memory 209864 kb
Host smart-ae27fec2-136b-448a-9925-23f02db9b8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492687370 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1492687370
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1080322147
Short name T503
Test name
Test status
Simulation time 438648968 ps
CPU time 1.7 seconds
Started Jan 24 07:14:04 PM PST 24
Finished Jan 24 07:14:10 PM PST 24
Peak memory 200908 kb
Host smart-9c2cb344-8359-472b-b2e3-7b3961ba6552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080322147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1080322147
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.151906892
Short name T504
Test name
Test status
Simulation time 162572192868 ps
CPU time 353.14 seconds
Started Jan 24 07:34:22 PM PST 24
Finished Jan 24 07:40:16 PM PST 24
Peak memory 201200 kb
Host smart-753d6568-cdc7-4a17-af2b-101635a7db15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151906892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.151906892
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2212725899
Short name T295
Test name
Test status
Simulation time 165073664876 ps
CPU time 225.57 seconds
Started Jan 24 07:13:42 PM PST 24
Finished Jan 24 07:17:28 PM PST 24
Peak memory 201168 kb
Host smart-6e51a079-1694-491c-a108-7f14cbe7cae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212725899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2212725899
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.225579755
Short name T625
Test name
Test status
Simulation time 323534293288 ps
CPU time 376.29 seconds
Started Jan 24 07:13:39 PM PST 24
Finished Jan 24 07:19:57 PM PST 24
Peak memory 201156 kb
Host smart-bd11fcce-224b-4d1a-914f-7a080f4cdf2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=225579755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.225579755
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3208859350
Short name T534
Test name
Test status
Simulation time 163699182292 ps
CPU time 92.9 seconds
Started Jan 24 08:02:53 PM PST 24
Finished Jan 24 08:04:29 PM PST 24
Peak memory 201192 kb
Host smart-5c0ead05-013f-4b7a-b85b-1eb9dda83ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208859350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3208859350
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1792686432
Short name T651
Test name
Test status
Simulation time 488550994737 ps
CPU time 299.14 seconds
Started Jan 24 07:13:42 PM PST 24
Finished Jan 24 07:18:41 PM PST 24
Peak memory 201252 kb
Host smart-15d2acd2-ea7f-405a-8cbc-7975ed948052
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792686432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1792686432
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2051781261
Short name T23
Test name
Test status
Simulation time 166355696060 ps
CPU time 38.5 seconds
Started Jan 24 07:13:47 PM PST 24
Finished Jan 24 07:14:26 PM PST 24
Peak memory 201128 kb
Host smart-3f7fcbcf-1116-48bb-bdc8-5d440db75a64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051781261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2051781261
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2053874198
Short name T583
Test name
Test status
Simulation time 325919920681 ps
CPU time 762.5 seconds
Started Jan 24 07:53:56 PM PST 24
Finished Jan 24 08:06:42 PM PST 24
Peak memory 201256 kb
Host smart-af88d1af-0578-44d7-9696-1c29796e76e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053874198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2053874198
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.327737340
Short name T593
Test name
Test status
Simulation time 81964686537 ps
CPU time 279.05 seconds
Started Jan 24 07:14:06 PM PST 24
Finished Jan 24 07:18:47 PM PST 24
Peak memory 201432 kb
Host smart-a17876a9-e4fb-4533-b010-8976d9e76da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327737340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.327737340
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2292614662
Short name T835
Test name
Test status
Simulation time 23935402735 ps
CPU time 13.68 seconds
Started Jan 24 07:13:58 PM PST 24
Finished Jan 24 07:14:12 PM PST 24
Peak memory 201052 kb
Host smart-c1f0589c-c8d9-4258-973e-d633523eda22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292614662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2292614662
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1157801215
Short name T484
Test name
Test status
Simulation time 3227757898 ps
CPU time 4.05 seconds
Started Jan 24 07:14:00 PM PST 24
Finished Jan 24 07:14:05 PM PST 24
Peak memory 201044 kb
Host smart-69b44772-0107-40be-900b-c031baeb546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157801215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1157801215
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2714888852
Short name T458
Test name
Test status
Simulation time 5704198707 ps
CPU time 4.91 seconds
Started Jan 24 07:13:41 PM PST 24
Finished Jan 24 07:13:46 PM PST 24
Peak memory 201044 kb
Host smart-dbee2036-9ef0-4685-bb96-5fe6be99416b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714888852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2714888852
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.584800755
Short name T505
Test name
Test status
Simulation time 412708434 ps
CPU time 0.86 seconds
Started Jan 24 07:14:38 PM PST 24
Finished Jan 24 07:14:47 PM PST 24
Peak memory 200792 kb
Host smart-48f616a6-8611-470f-aa3a-a802e99c26e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584800755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.584800755
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2087217144
Short name T227
Test name
Test status
Simulation time 160994367039 ps
CPU time 346.12 seconds
Started Jan 24 07:14:19 PM PST 24
Finished Jan 24 07:20:07 PM PST 24
Peak memory 201272 kb
Host smart-711d04e3-f3c1-4505-a3b1-d16e53b5e59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087217144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2087217144
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1053963524
Short name T712
Test name
Test status
Simulation time 494575127175 ps
CPU time 1157.73 seconds
Started Jan 24 07:29:11 PM PST 24
Finished Jan 24 07:48:30 PM PST 24
Peak memory 201176 kb
Host smart-5a78be63-2f0f-486c-a366-1a31ce5ebab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053963524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1053963524
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.395907595
Short name T632
Test name
Test status
Simulation time 324294487416 ps
CPU time 764.12 seconds
Started Jan 24 07:14:12 PM PST 24
Finished Jan 24 07:26:58 PM PST 24
Peak memory 201064 kb
Host smart-71b4c941-7998-4959-984c-13cf6bdfb75f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=395907595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.395907595
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1894995338
Short name T536
Test name
Test status
Simulation time 489089544976 ps
CPU time 1088.29 seconds
Started Jan 24 07:14:17 PM PST 24
Finished Jan 24 07:32:26 PM PST 24
Peak memory 201212 kb
Host smart-ad4a511b-81b1-4619-9762-e9c101346f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894995338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1894995338
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3147972394
Short name T716
Test name
Test status
Simulation time 498972009891 ps
CPU time 297.89 seconds
Started Jan 24 07:14:14 PM PST 24
Finished Jan 24 07:19:13 PM PST 24
Peak memory 201236 kb
Host smart-85b4acce-cc22-443e-b794-e5e75f525049
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147972394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3147972394
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3987819731
Short name T169
Test name
Test status
Simulation time 499829930231 ps
CPU time 280.34 seconds
Started Jan 24 07:14:17 PM PST 24
Finished Jan 24 07:18:58 PM PST 24
Peak memory 201204 kb
Host smart-05e4de87-a514-44f4-bd8f-44308172adbc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987819731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3987819731
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2107625583
Short name T773
Test name
Test status
Simulation time 29246490399 ps
CPU time 18.4 seconds
Started Jan 24 07:14:38 PM PST 24
Finished Jan 24 07:15:05 PM PST 24
Peak memory 200916 kb
Host smart-9890daad-88c5-45f4-835f-766a74d911aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107625583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2107625583
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.712322173
Short name T590
Test name
Test status
Simulation time 4244413045 ps
CPU time 1.3 seconds
Started Jan 24 07:14:29 PM PST 24
Finished Jan 24 07:14:34 PM PST 24
Peak memory 201048 kb
Host smart-c18c2e78-7779-458a-89ae-6d13fff17ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712322173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.712322173
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.926391216
Short name T676
Test name
Test status
Simulation time 5608264497 ps
CPU time 4.36 seconds
Started Jan 24 07:14:03 PM PST 24
Finished Jan 24 07:14:12 PM PST 24
Peak memory 201008 kb
Host smart-ea548b8a-db26-49c4-88a6-5e88e7eb530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926391216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.926391216
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.431896087
Short name T706
Test name
Test status
Simulation time 6471012409 ps
CPU time 15.28 seconds
Started Jan 24 07:14:39 PM PST 24
Finished Jan 24 07:15:03 PM PST 24
Peak memory 201016 kb
Host smart-d2df2704-54d3-487f-aa83-183836bbe9fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431896087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
431896087
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3659900113
Short name T641
Test name
Test status
Simulation time 53875134671 ps
CPU time 36.94 seconds
Started Jan 24 07:14:38 PM PST 24
Finished Jan 24 07:15:23 PM PST 24
Peak memory 201280 kb
Host smart-b0097468-0aef-4abf-a757-24c1f8312c35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659900113 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3659900113
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3108222315
Short name T476
Test name
Test status
Simulation time 442704647 ps
CPU time 1.66 seconds
Started Jan 24 11:38:26 PM PST 24
Finished Jan 24 11:38:28 PM PST 24
Peak memory 200928 kb
Host smart-c5b4f68e-451e-4fea-be35-44c75bf3c7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108222315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3108222315
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1119901317
Short name T621
Test name
Test status
Simulation time 483998852681 ps
CPU time 263.04 seconds
Started Jan 24 07:14:59 PM PST 24
Finished Jan 24 07:19:25 PM PST 24
Peak memory 201252 kb
Host smart-ddbaa205-2a7c-4c1f-bc8e-682961f916aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119901317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1119901317
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2402667699
Short name T771
Test name
Test status
Simulation time 166854285992 ps
CPU time 105.9 seconds
Started Jan 24 07:14:51 PM PST 24
Finished Jan 24 07:16:41 PM PST 24
Peak memory 201200 kb
Host smart-933edd52-c448-4e59-9001-5ad06b15f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402667699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2402667699
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2608224654
Short name T450
Test name
Test status
Simulation time 163528128613 ps
CPU time 74.57 seconds
Started Jan 24 07:15:02 PM PST 24
Finished Jan 24 07:16:21 PM PST 24
Peak memory 201144 kb
Host smart-d0de6fe5-20ae-40a5-b62b-1083030b700c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608224654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2608224654
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1211304881
Short name T669
Test name
Test status
Simulation time 166517343240 ps
CPU time 203.61 seconds
Started Jan 24 07:14:50 PM PST 24
Finished Jan 24 07:18:19 PM PST 24
Peak memory 201236 kb
Host smart-789e801c-f318-44df-82a0-969c6c2bc237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211304881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1211304881
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1714985436
Short name T21
Test name
Test status
Simulation time 331649573210 ps
CPU time 794.77 seconds
Started Jan 24 08:42:43 PM PST 24
Finished Jan 24 08:55:58 PM PST 24
Peak memory 201280 kb
Host smart-c5a79f60-241c-4bc6-8aca-f9674874403f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714985436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1714985436
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.183532477
Short name T147
Test name
Test status
Simulation time 492271007608 ps
CPU time 109.14 seconds
Started Jan 24 08:52:35 PM PST 24
Finished Jan 24 08:54:25 PM PST 24
Peak memory 201260 kb
Host smart-a9a52e5f-cdae-4950-9efe-3a291c854e7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183532477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.183532477
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4247163726
Short name T703
Test name
Test status
Simulation time 494388530844 ps
CPU time 307.19 seconds
Started Jan 24 07:15:04 PM PST 24
Finished Jan 24 07:20:14 PM PST 24
Peak memory 201152 kb
Host smart-ba298e91-e209-4d62-a4b1-a6ef5f618b99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247163726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4247163726
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1097591008
Short name T364
Test name
Test status
Simulation time 65302815526 ps
CPU time 290.36 seconds
Started Jan 24 07:15:01 PM PST 24
Finished Jan 24 07:19:57 PM PST 24
Peak memory 201508 kb
Host smart-760cc029-164e-4726-a8fd-03e774900c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097591008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1097591008
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.392903892
Short name T748
Test name
Test status
Simulation time 29816292625 ps
CPU time 34.15 seconds
Started Jan 24 07:15:02 PM PST 24
Finished Jan 24 07:15:41 PM PST 24
Peak memory 201000 kb
Host smart-1ebfed60-a7f8-4ff5-99ce-ed385295ff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392903892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.392903892
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1344896419
Short name T153
Test name
Test status
Simulation time 3652427139 ps
CPU time 6.77 seconds
Started Jan 24 07:14:59 PM PST 24
Finished Jan 24 07:15:09 PM PST 24
Peak memory 201028 kb
Host smart-e03cc03a-4b4e-446f-977e-2a4fabb57f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344896419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1344896419
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.613286741
Short name T86
Test name
Test status
Simulation time 5783742329 ps
CPU time 13.77 seconds
Started Jan 24 07:14:44 PM PST 24
Finished Jan 24 07:15:05 PM PST 24
Peak memory 200904 kb
Host smart-21a3fad6-7c7c-43f6-b3ae-4ff32f0dbada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613286741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.613286741
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2634512123
Short name T557
Test name
Test status
Simulation time 37154360113 ps
CPU time 63.52 seconds
Started Jan 24 07:15:08 PM PST 24
Finished Jan 24 07:16:12 PM PST 24
Peak memory 209808 kb
Host smart-d0f4dd01-3bb2-4b08-acf7-0a62be767d55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634512123 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2634512123
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.416069803
Short name T812
Test name
Test status
Simulation time 529845714 ps
CPU time 1.8 seconds
Started Jan 24 07:15:47 PM PST 24
Finished Jan 24 07:15:50 PM PST 24
Peak memory 200932 kb
Host smart-1be5a5f8-9b84-4716-a6a1-d1e7c325e0b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416069803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.416069803
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.511536158
Short name T640
Test name
Test status
Simulation time 159201651549 ps
CPU time 57.04 seconds
Started Jan 24 07:19:53 PM PST 24
Finished Jan 24 07:20:51 PM PST 24
Peak memory 201152 kb
Host smart-2cc82a47-13e5-4972-94e4-9d36a7fbf563
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511536158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.511536158
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2068651233
Short name T276
Test name
Test status
Simulation time 494239187514 ps
CPU time 149.23 seconds
Started Jan 25 12:23:01 AM PST 24
Finished Jan 25 12:25:32 AM PST 24
Peak memory 201244 kb
Host smart-9d156ec6-6427-4512-a26c-c87f7de7777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068651233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2068651233
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1986959695
Short name T524
Test name
Test status
Simulation time 165884092509 ps
CPU time 358.36 seconds
Started Jan 24 07:07:39 PM PST 24
Finished Jan 24 07:13:38 PM PST 24
Peak memory 201124 kb
Host smart-360968fc-0fca-4f23-a443-f6a49fb1c2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986959695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1986959695
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.361377560
Short name T566
Test name
Test status
Simulation time 500275750355 ps
CPU time 972.56 seconds
Started Jan 24 07:07:46 PM PST 24
Finished Jan 24 07:24:00 PM PST 24
Peak memory 201160 kb
Host smart-a64cba1c-311b-4052-9c6d-455ded3f346b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=361377560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.361377560
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3945522351
Short name T836
Test name
Test status
Simulation time 159883156313 ps
CPU time 389.22 seconds
Started Jan 24 07:07:45 PM PST 24
Finished Jan 24 07:14:16 PM PST 24
Peak memory 201228 kb
Host smart-7323f823-1b52-46f7-bf0c-1fef7b30608f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945522351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3945522351
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.872441162
Short name T145
Test name
Test status
Simulation time 502549980425 ps
CPU time 152.87 seconds
Started Jan 24 07:07:42 PM PST 24
Finished Jan 24 07:10:16 PM PST 24
Peak memory 201280 kb
Host smart-f8fb2abc-30cc-4ff4-b562-054d20c72cd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872441162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.872441162
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4016870749
Short name T567
Test name
Test status
Simulation time 496020784147 ps
CPU time 1147.62 seconds
Started Jan 24 07:25:15 PM PST 24
Finished Jan 24 07:44:24 PM PST 24
Peak memory 201140 kb
Host smart-c1cbfcf1-e7fa-4cd6-a877-a862102e3bf8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016870749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.4016870749
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.84667124
Short name T42
Test name
Test status
Simulation time 79455394649 ps
CPU time 345.92 seconds
Started Jan 24 07:07:46 PM PST 24
Finished Jan 24 07:13:34 PM PST 24
Peak memory 201520 kb
Host smart-3303296e-f1f6-4324-96b9-b6ea6ddf7369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84667124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.84667124
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.338445642
Short name T167
Test name
Test status
Simulation time 39510435081 ps
CPU time 88.23 seconds
Started Jan 24 07:07:46 PM PST 24
Finished Jan 24 07:09:16 PM PST 24
Peak memory 201016 kb
Host smart-089bd8e9-3b70-434c-90c7-8131da71581a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338445642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.338445642
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2397020870
Short name T457
Test name
Test status
Simulation time 5241554742 ps
CPU time 7.14 seconds
Started Jan 24 07:07:44 PM PST 24
Finished Jan 24 07:07:52 PM PST 24
Peak memory 201008 kb
Host smart-825ba6e9-0126-4ab1-839b-754c87b8afd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397020870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2397020870
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3311885094
Short name T51
Test name
Test status
Simulation time 4247324274 ps
CPU time 3.04 seconds
Started Jan 24 07:07:49 PM PST 24
Finished Jan 24 07:07:53 PM PST 24
Peak memory 216240 kb
Host smart-08dbc2f9-b0ea-4235-9554-83d16070583f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311885094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3311885094
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3242052798
Short name T459
Test name
Test status
Simulation time 5807863964 ps
CPU time 13.96 seconds
Started Jan 24 07:07:46 PM PST 24
Finished Jan 24 07:08:02 PM PST 24
Peak memory 200912 kb
Host smart-a4a60c79-58be-4b8a-afb5-31fadeb1fdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242052798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3242052798
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.369652413
Short name T266
Test name
Test status
Simulation time 389513847552 ps
CPU time 1433.19 seconds
Started Jan 24 08:15:54 PM PST 24
Finished Jan 24 08:39:49 PM PST 24
Peak memory 201648 kb
Host smart-9b30bf0e-da51-460b-813b-9ccbed5fbf59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369652413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.369652413
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.825361302
Short name T660
Test name
Test status
Simulation time 386558764 ps
CPU time 1.19 seconds
Started Jan 24 07:15:54 PM PST 24
Finished Jan 24 07:15:56 PM PST 24
Peak memory 200212 kb
Host smart-6f3bc444-dad9-4b41-be87-0d627204a349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825361302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.825361302
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4075737073
Short name T792
Test name
Test status
Simulation time 333114589398 ps
CPU time 201.53 seconds
Started Jan 24 07:15:33 PM PST 24
Finished Jan 24 07:18:55 PM PST 24
Peak memory 201236 kb
Host smart-cfabc3a2-fac3-46b1-9655-87fc2343387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075737073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4075737073
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2266324385
Short name T742
Test name
Test status
Simulation time 504399148393 ps
CPU time 1194.38 seconds
Started Jan 24 07:15:26 PM PST 24
Finished Jan 24 07:35:22 PM PST 24
Peak memory 201172 kb
Host smart-8fb6d132-3162-4131-830f-c4905e0ef16e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266324385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2266324385
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.54522502
Short name T62
Test name
Test status
Simulation time 319807645354 ps
CPU time 467.41 seconds
Started Jan 24 07:15:14 PM PST 24
Finished Jan 24 07:23:03 PM PST 24
Peak memory 201124 kb
Host smart-629f6a69-2058-4f84-aacb-4e99dff30399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54522502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.54522502
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1898432734
Short name T811
Test name
Test status
Simulation time 164987050007 ps
CPU time 405.62 seconds
Started Jan 24 07:34:28 PM PST 24
Finished Jan 24 07:41:15 PM PST 24
Peak memory 201180 kb
Host smart-26f4fcd9-ff04-4224-81dd-22cf83fe928d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898432734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1898432734
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.943734101
Short name T245
Test name
Test status
Simulation time 165778708501 ps
CPU time 102.03 seconds
Started Jan 24 07:15:29 PM PST 24
Finished Jan 24 07:17:12 PM PST 24
Peak memory 201156 kb
Host smart-9a17955e-10c4-4a8d-8102-782305203092
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943734101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.943734101
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1332014604
Short name T532
Test name
Test status
Simulation time 333637388160 ps
CPU time 190.55 seconds
Started Jan 24 07:15:36 PM PST 24
Finished Jan 24 07:18:47 PM PST 24
Peak memory 201260 kb
Host smart-fc942fc4-1364-436f-9ad7-3524c0bf95c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332014604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1332014604
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.995765740
Short name T478
Test name
Test status
Simulation time 29086029477 ps
CPU time 62.63 seconds
Started Jan 24 07:15:35 PM PST 24
Finished Jan 24 07:16:38 PM PST 24
Peak memory 201028 kb
Host smart-8467d32f-a69e-46c7-9fda-2659ef38816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995765740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.995765740
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3297392987
Short name T800
Test name
Test status
Simulation time 4218498723 ps
CPU time 3.25 seconds
Started Jan 24 07:16:19 PM PST 24
Finished Jan 24 07:16:23 PM PST 24
Peak memory 200952 kb
Host smart-0714c7a4-94e9-4850-b7f6-86d8401766ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297392987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3297392987
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2847089329
Short name T661
Test name
Test status
Simulation time 5882434482 ps
CPU time 7.85 seconds
Started Jan 24 07:34:38 PM PST 24
Finished Jan 24 07:34:47 PM PST 24
Peak memory 201068 kb
Host smart-b521ce82-c25e-4879-8223-74d5f3b01b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847089329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2847089329
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2308318882
Short name T374
Test name
Test status
Simulation time 139236679485 ps
CPU time 390.72 seconds
Started Jan 24 07:15:41 PM PST 24
Finished Jan 24 07:22:12 PM PST 24
Peak memory 201496 kb
Host smart-2280029c-c7c2-41db-aa1f-9c855868b383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308318882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2308318882
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3874302421
Short name T446
Test name
Test status
Simulation time 315588258 ps
CPU time 1.31 seconds
Started Jan 24 07:16:16 PM PST 24
Finished Jan 24 07:16:18 PM PST 24
Peak memory 200916 kb
Host smart-8c6104ae-ddfa-46e0-af6e-b4424820332a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874302421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3874302421
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2893145114
Short name T298
Test name
Test status
Simulation time 500491393145 ps
CPU time 837.65 seconds
Started Jan 24 07:15:56 PM PST 24
Finished Jan 24 07:29:55 PM PST 24
Peak memory 201140 kb
Host smart-0f7f60b6-cf95-4c41-85b9-ddb2778ade36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893145114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2893145114
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1136606962
Short name T830
Test name
Test status
Simulation time 169367226080 ps
CPU time 97.56 seconds
Started Jan 24 07:16:00 PM PST 24
Finished Jan 24 07:17:39 PM PST 24
Peak memory 201168 kb
Host smart-ee81684b-fc23-4033-8ce9-e0aba15d8616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136606962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1136606962
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1747077452
Short name T216
Test name
Test status
Simulation time 321231992573 ps
CPU time 185.61 seconds
Started Jan 24 07:16:02 PM PST 24
Finished Jan 24 07:19:09 PM PST 24
Peak memory 201228 kb
Host smart-8c753ff6-1d93-473b-a66f-bfa245c1cbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747077452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1747077452
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1504688339
Short name T637
Test name
Test status
Simulation time 162093013530 ps
CPU time 180.41 seconds
Started Jan 24 07:16:00 PM PST 24
Finished Jan 24 07:19:02 PM PST 24
Peak memory 201140 kb
Host smart-3b0f17e5-b11e-4a38-832a-2e2c739a6656
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504688339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1504688339
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3143987728
Short name T663
Test name
Test status
Simulation time 496300946874 ps
CPU time 1152.33 seconds
Started Jan 24 07:15:48 PM PST 24
Finished Jan 24 07:35:02 PM PST 24
Peak memory 201300 kb
Host smart-8a08bde4-18c8-4690-bc6a-cd94d12008aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143987728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3143987728
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3529691038
Short name T638
Test name
Test status
Simulation time 333439504991 ps
CPU time 778.06 seconds
Started Jan 24 07:15:50 PM PST 24
Finished Jan 24 07:28:49 PM PST 24
Peak memory 201148 kb
Host smart-220cde29-0a3a-4b03-b679-5cfab5bdf240
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529691038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3529691038
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3868206404
Short name T320
Test name
Test status
Simulation time 317461922575 ps
CPU time 233.91 seconds
Started Jan 24 07:15:59 PM PST 24
Finished Jan 24 07:19:54 PM PST 24
Peak memory 201104 kb
Host smart-d88e9cdf-2acb-4ba0-9c9d-d4d4736cf373
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868206404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3868206404
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.735040344
Short name T635
Test name
Test status
Simulation time 168526058832 ps
CPU time 381.2 seconds
Started Jan 24 07:16:00 PM PST 24
Finished Jan 24 07:22:22 PM PST 24
Peak memory 201140 kb
Host smart-17e8a4b9-999e-4a29-a5bd-6c6bb5d8a0c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735040344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.735040344
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3677627679
Short name T196
Test name
Test status
Simulation time 106021324172 ps
CPU time 544.88 seconds
Started Jan 24 07:16:03 PM PST 24
Finished Jan 24 07:25:09 PM PST 24
Peak memory 201380 kb
Host smart-868511bd-6ca9-46e0-a52d-4f442552d4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677627679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3677627679
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1328569952
Short name T738
Test name
Test status
Simulation time 30207413887 ps
CPU time 68.18 seconds
Started Jan 24 07:15:59 PM PST 24
Finished Jan 24 07:17:08 PM PST 24
Peak memory 201012 kb
Host smart-33f25c44-a236-412f-83d3-da5c771e2f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328569952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1328569952
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3694996772
Short name T781
Test name
Test status
Simulation time 3746084099 ps
CPU time 2.74 seconds
Started Jan 24 07:16:02 PM PST 24
Finished Jan 24 07:16:06 PM PST 24
Peak memory 200912 kb
Host smart-08718f74-c529-493b-8555-5b58539a7ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694996772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3694996772
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1668610675
Short name T755
Test name
Test status
Simulation time 5797955170 ps
CPU time 12.61 seconds
Started Jan 24 07:15:54 PM PST 24
Finished Jan 24 07:16:07 PM PST 24
Peak memory 200212 kb
Host smart-76939088-618a-47e0-b9d3-a752ff8d073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668610675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1668610675
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2272926943
Short name T260
Test name
Test status
Simulation time 244593463051 ps
CPU time 265.88 seconds
Started Jan 24 07:16:17 PM PST 24
Finished Jan 24 07:20:43 PM PST 24
Peak memory 201508 kb
Host smart-a7f86d94-8344-4779-89c6-db2c4e8ba2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272926943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2272926943
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1382759010
Short name T225
Test name
Test status
Simulation time 77828187612 ps
CPU time 59.98 seconds
Started Jan 24 07:53:53 PM PST 24
Finished Jan 24 07:54:59 PM PST 24
Peak memory 209816 kb
Host smart-98d9f942-1a5c-47db-83d2-947131f893a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382759010 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1382759010
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.248972490
Short name T737
Test name
Test status
Simulation time 467467850 ps
CPU time 0.94 seconds
Started Jan 24 07:16:45 PM PST 24
Finished Jan 24 07:16:46 PM PST 24
Peak memory 200888 kb
Host smart-a4f2276a-1a10-467c-926c-d4c3ff1ede8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248972490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.248972490
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3866426187
Short name T254
Test name
Test status
Simulation time 159831943170 ps
CPU time 94.83 seconds
Started Jan 24 07:16:37 PM PST 24
Finished Jan 24 07:18:12 PM PST 24
Peak memory 201136 kb
Host smart-c34b3975-349d-4fce-b555-8151367197eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866426187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3866426187
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2631668675
Short name T564
Test name
Test status
Simulation time 480868528129 ps
CPU time 1116.8 seconds
Started Jan 24 07:16:29 PM PST 24
Finished Jan 24 07:35:06 PM PST 24
Peak memory 201184 kb
Host smart-8ba40a5a-b64d-4623-b72d-2b57a81f6512
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631668675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2631668675
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3708488841
Short name T547
Test name
Test status
Simulation time 499833579159 ps
CPU time 357.02 seconds
Started Jan 24 07:16:27 PM PST 24
Finished Jan 24 07:22:25 PM PST 24
Peak memory 201248 kb
Host smart-524278e0-0c56-4b68-a0dd-d84b3a57325b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708488841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3708488841
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.436797363
Short name T287
Test name
Test status
Simulation time 164836292919 ps
CPU time 93.69 seconds
Started Jan 24 07:16:28 PM PST 24
Finished Jan 24 07:18:02 PM PST 24
Peak memory 201188 kb
Host smart-9e453786-e060-4cbc-b7e2-c06bf6d4aa0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436797363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.436797363
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1175156091
Short name T119
Test name
Test status
Simulation time 166883934885 ps
CPU time 107.16 seconds
Started Jan 24 07:16:40 PM PST 24
Finished Jan 24 07:18:28 PM PST 24
Peak memory 201240 kb
Host smart-43150c58-6c6a-44cb-b468-14c4043c6b3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175156091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1175156091
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3680797694
Short name T191
Test name
Test status
Simulation time 130390726218 ps
CPU time 657.84 seconds
Started Jan 24 07:16:47 PM PST 24
Finished Jan 24 07:27:45 PM PST 24
Peak memory 201400 kb
Host smart-d32274f6-ded5-4e10-b7f6-0b1ca60c57ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680797694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3680797694
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2402524941
Short name T829
Test name
Test status
Simulation time 33311559987 ps
CPU time 8.21 seconds
Started Jan 24 07:16:40 PM PST 24
Finished Jan 24 07:16:49 PM PST 24
Peak memory 201036 kb
Host smart-cb761bc7-0572-4885-8ac4-86ab5411e098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402524941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2402524941
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3292130391
Short name T87
Test name
Test status
Simulation time 5428139903 ps
CPU time 12.76 seconds
Started Jan 24 07:16:45 PM PST 24
Finished Jan 24 07:16:58 PM PST 24
Peak memory 200916 kb
Host smart-bddcde74-e3bf-4c85-ae17-ff297b70942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292130391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3292130391
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2026640756
Short name T672
Test name
Test status
Simulation time 6012405631 ps
CPU time 14.07 seconds
Started Jan 24 07:16:12 PM PST 24
Finished Jan 24 07:16:27 PM PST 24
Peak memory 200996 kb
Host smart-510ea532-04d5-415c-9e0b-b1eda1bf73e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026640756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2026640756
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1804112277
Short name T432
Test name
Test status
Simulation time 32317843226 ps
CPU time 78.79 seconds
Started Jan 24 07:35:53 PM PST 24
Finished Jan 24 07:37:14 PM PST 24
Peak memory 201056 kb
Host smart-7b92decc-1b45-4b72-a417-edb96997a205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804112277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1804112277
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3869176618
Short name T799
Test name
Test status
Simulation time 436847492 ps
CPU time 1.69 seconds
Started Jan 24 07:17:27 PM PST 24
Finished Jan 24 07:17:30 PM PST 24
Peak memory 200900 kb
Host smart-e349497a-1221-479f-9f27-9166ad5a91af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869176618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3869176618
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.938840915
Short name T314
Test name
Test status
Simulation time 495231186102 ps
CPU time 198.04 seconds
Started Jan 24 07:17:03 PM PST 24
Finished Jan 24 07:20:22 PM PST 24
Peak memory 201200 kb
Host smart-7f9c4f5d-94db-4df7-9767-daf3041f0255
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938840915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.938840915
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3482500124
Short name T673
Test name
Test status
Simulation time 497702331040 ps
CPU time 215.38 seconds
Started Jan 24 08:11:49 PM PST 24
Finished Jan 24 08:15:29 PM PST 24
Peak memory 201236 kb
Host smart-83562c29-b486-49c3-a0aa-e456b6f3078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482500124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3482500124
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1636218607
Short name T708
Test name
Test status
Simulation time 494592965752 ps
CPU time 588.98 seconds
Started Jan 24 07:16:51 PM PST 24
Finished Jan 24 07:26:41 PM PST 24
Peak memory 201072 kb
Host smart-a7f5b454-f698-4d03-94f0-1e1c09d22512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636218607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1636218607
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1837286707
Short name T689
Test name
Test status
Simulation time 161604355030 ps
CPU time 380.72 seconds
Started Jan 24 07:16:51 PM PST 24
Finished Jan 24 07:23:13 PM PST 24
Peak memory 201140 kb
Host smart-9cbbf04b-2fbe-41a8-b7dd-a51ba498fb1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837286707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1837286707
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3437725451
Short name T734
Test name
Test status
Simulation time 165876358865 ps
CPU time 99.58 seconds
Started Jan 24 07:34:31 PM PST 24
Finished Jan 24 07:36:11 PM PST 24
Peak memory 201248 kb
Host smart-1a135e3c-27ed-43d0-b151-ab80f9989efd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437725451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3437725451
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1929598565
Short name T297
Test name
Test status
Simulation time 170025437834 ps
CPU time 368.18 seconds
Started Jan 24 07:41:02 PM PST 24
Finished Jan 24 07:47:12 PM PST 24
Peak memory 201260 kb
Host smart-d3a1a3c2-5b39-46ce-b8cc-c21493f731da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929598565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1929598565
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1556854882
Short name T481
Test name
Test status
Simulation time 491008130781 ps
CPU time 1134.09 seconds
Started Jan 24 07:16:58 PM PST 24
Finished Jan 24 07:35:54 PM PST 24
Peak memory 201140 kb
Host smart-34278637-8604-4e96-b6d4-4dad74dfc71a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556854882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1556854882
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1953868033
Short name T735
Test name
Test status
Simulation time 38012330242 ps
CPU time 78.41 seconds
Started Jan 24 07:23:13 PM PST 24
Finished Jan 24 07:24:33 PM PST 24
Peak memory 201028 kb
Host smart-7dcbba59-f248-45c0-896d-3665894ffe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953868033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1953868033
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1749265922
Short name T769
Test name
Test status
Simulation time 3346361077 ps
CPU time 2.7 seconds
Started Jan 24 07:52:04 PM PST 24
Finished Jan 24 07:52:07 PM PST 24
Peak memory 201060 kb
Host smart-ad4e662e-22a3-45c9-9055-fb7f5c0b25fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749265922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1749265922
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.70687378
Short name T451
Test name
Test status
Simulation time 5878882004 ps
CPU time 5.12 seconds
Started Jan 24 07:16:53 PM PST 24
Finished Jan 24 07:17:03 PM PST 24
Peak memory 201004 kb
Host smart-d686ca51-086a-45e8-bdba-effff8573a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70687378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.70687378
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3111855702
Short name T691
Test name
Test status
Simulation time 351907136280 ps
CPU time 235.54 seconds
Started Jan 24 07:17:15 PM PST 24
Finished Jan 24 07:21:11 PM PST 24
Peak memory 201212 kb
Host smart-d111b4d9-d61a-4472-9258-85c4a02a6fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111855702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3111855702
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1016436194
Short name T274
Test name
Test status
Simulation time 36338043990 ps
CPU time 89.7 seconds
Started Jan 24 07:17:15 PM PST 24
Finished Jan 24 07:18:45 PM PST 24
Peak memory 209516 kb
Host smart-a6abcf5d-dfbe-48fd-8a35-d90adce8d41f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016436194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1016436194
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.171558593
Short name T47
Test name
Test status
Simulation time 342852891 ps
CPU time 0.74 seconds
Started Jan 24 07:18:04 PM PST 24
Finished Jan 24 07:18:06 PM PST 24
Peak memory 200920 kb
Host smart-397589bb-b6bd-4fcb-996e-f76912c86e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171558593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.171558593
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2718557687
Short name T101
Test name
Test status
Simulation time 164303116712 ps
CPU time 334.88 seconds
Started Jan 24 07:17:42 PM PST 24
Finished Jan 24 07:23:18 PM PST 24
Peak memory 201208 kb
Host smart-f45811aa-7249-4e1d-9f3b-76896dbe13d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718557687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2718557687
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.386463618
Short name T324
Test name
Test status
Simulation time 347932307227 ps
CPU time 435.6 seconds
Started Jan 24 07:17:42 PM PST 24
Finished Jan 24 07:24:58 PM PST 24
Peak memory 201240 kb
Host smart-4c62c808-4ab6-49a7-8c9e-34315ac61c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386463618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.386463618
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.68169031
Short name T765
Test name
Test status
Simulation time 489073012775 ps
CPU time 850.99 seconds
Started Jan 24 07:17:30 PM PST 24
Finished Jan 24 07:31:46 PM PST 24
Peak memory 201140 kb
Host smart-1bd00716-1e44-4551-a4ae-ca021605061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68169031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.68169031
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3202200449
Short name T221
Test name
Test status
Simulation time 332889081236 ps
CPU time 411.72 seconds
Started Jan 24 07:35:29 PM PST 24
Finished Jan 24 07:42:24 PM PST 24
Peak memory 201164 kb
Host smart-fdcc608c-bbb3-467c-b0ca-e05af910770c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202200449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3202200449
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1233565214
Short name T823
Test name
Test status
Simulation time 332315716357 ps
CPU time 387.61 seconds
Started Jan 24 07:17:27 PM PST 24
Finished Jan 24 07:23:56 PM PST 24
Peak memory 201256 kb
Host smart-0f65d922-edc3-47c0-80b9-2874161b21b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233565214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1233565214
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1473825813
Short name T578
Test name
Test status
Simulation time 327554195648 ps
CPU time 190.84 seconds
Started Jan 24 07:56:30 PM PST 24
Finished Jan 24 07:59:41 PM PST 24
Peak memory 201264 kb
Host smart-07ca9405-e0f0-47ea-82cf-6906176ce4ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473825813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1473825813
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.540385628
Short name T125
Test name
Test status
Simulation time 493664468837 ps
CPU time 543.33 seconds
Started Jan 24 07:17:42 PM PST 24
Finished Jan 24 07:26:46 PM PST 24
Peak memory 201176 kb
Host smart-2ab8bf5f-79c7-488c-8123-ca5e85344fe3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540385628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.540385628
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1482577350
Short name T592
Test name
Test status
Simulation time 489638605895 ps
CPU time 293.04 seconds
Started Jan 24 07:17:41 PM PST 24
Finished Jan 24 07:22:35 PM PST 24
Peak memory 201056 kb
Host smart-5733e957-f8fa-4d36-b8b0-29a14e4f2ac7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482577350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1482577350
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3270560173
Short name T189
Test name
Test status
Simulation time 111984247933 ps
CPU time 468.35 seconds
Started Jan 24 07:17:58 PM PST 24
Finished Jan 24 07:25:47 PM PST 24
Peak memory 201520 kb
Host smart-88ffa04e-87b8-4ee8-975b-1e685198a0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270560173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3270560173
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.127368304
Short name T487
Test name
Test status
Simulation time 24265139986 ps
CPU time 27.52 seconds
Started Jan 24 11:38:29 PM PST 24
Finished Jan 24 11:38:58 PM PST 24
Peak memory 201056 kb
Host smart-f12f34a8-e52e-4b78-87e7-f905334459ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127368304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.127368304
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2789329895
Short name T538
Test name
Test status
Simulation time 4833982163 ps
CPU time 11.67 seconds
Started Jan 24 07:17:53 PM PST 24
Finished Jan 24 07:18:06 PM PST 24
Peak memory 201004 kb
Host smart-1a1d01a6-ade1-4663-92c4-e9bdefed11b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789329895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2789329895
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2661095040
Short name T136
Test name
Test status
Simulation time 5564698579 ps
CPU time 12.96 seconds
Started Jan 24 07:31:31 PM PST 24
Finished Jan 24 07:31:51 PM PST 24
Peak memory 201056 kb
Host smart-a0e8b91c-ced1-4be6-9264-f1037b1d3439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661095040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2661095040
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.678593150
Short name T685
Test name
Test status
Simulation time 500844520993 ps
CPU time 574.98 seconds
Started Jan 24 07:17:59 PM PST 24
Finished Jan 24 07:27:36 PM PST 24
Peak memory 201176 kb
Host smart-8fecdb19-bc48-4d5e-80b1-e561293a3ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678593150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
678593150
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3748258714
Short name T711
Test name
Test status
Simulation time 36013917877 ps
CPU time 143.4 seconds
Started Jan 24 07:18:01 PM PST 24
Finished Jan 24 07:20:27 PM PST 24
Peak memory 209880 kb
Host smart-508e3ac2-4ab8-45f3-9ffd-69a367395f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748258714 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3748258714
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.155179891
Short name T560
Test name
Test status
Simulation time 478081561 ps
CPU time 1.66 seconds
Started Jan 24 07:18:41 PM PST 24
Finished Jan 24 07:18:43 PM PST 24
Peak memory 200908 kb
Host smart-b4dc2ad8-244a-4f99-a8f6-aa4ee1cc1e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155179891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.155179891
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3535626110
Short name T725
Test name
Test status
Simulation time 331148791151 ps
CPU time 348.96 seconds
Started Jan 24 07:18:28 PM PST 24
Finished Jan 24 07:24:18 PM PST 24
Peak memory 201252 kb
Host smart-4f7c84eb-1d78-4420-abe9-63d7a6a8afd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535626110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3535626110
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2590876769
Short name T611
Test name
Test status
Simulation time 332418078276 ps
CPU time 818.64 seconds
Started Jan 24 09:02:14 PM PST 24
Finished Jan 24 09:15:54 PM PST 24
Peak memory 201276 kb
Host smart-1ea2f036-e922-466a-a4b3-63021a3873e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590876769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2590876769
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.738646506
Short name T594
Test name
Test status
Simulation time 165971854899 ps
CPU time 397.9 seconds
Started Jan 24 08:11:22 PM PST 24
Finished Jan 24 08:18:01 PM PST 24
Peak memory 201248 kb
Host smart-5d826117-4735-4897-ac04-6b2b9b8fc1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738646506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.738646506
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1458037281
Short name T854
Test name
Test status
Simulation time 160673339253 ps
CPU time 182.28 seconds
Started Jan 24 07:37:49 PM PST 24
Finished Jan 24 07:40:53 PM PST 24
Peak memory 201156 kb
Host smart-ec8081c0-d3b4-4052-bad7-b794a2ebb82e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458037281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1458037281
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.892729286
Short name T470
Test name
Test status
Simulation time 336082946920 ps
CPU time 823.36 seconds
Started Jan 24 07:18:02 PM PST 24
Finished Jan 24 07:31:48 PM PST 24
Peak memory 201156 kb
Host smart-3ffa39ea-4124-4ee2-a4d2-83ccc9020895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892729286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.892729286
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1685884975
Short name T613
Test name
Test status
Simulation time 328031920873 ps
CPU time 203.09 seconds
Started Jan 24 07:56:39 PM PST 24
Finished Jan 24 08:00:03 PM PST 24
Peak memory 201240 kb
Host smart-ebce5f3a-0287-4cd5-80a8-8569a6e32194
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685884975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1685884975
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.857771407
Short name T282
Test name
Test status
Simulation time 511403681091 ps
CPU time 311.22 seconds
Started Jan 24 07:18:18 PM PST 24
Finished Jan 24 07:23:31 PM PST 24
Peak memory 201260 kb
Host smart-037a223e-4c0f-4e27-99ac-5de08dd247d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857771407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.857771407
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2352981793
Short name T555
Test name
Test status
Simulation time 496345433609 ps
CPU time 1123.12 seconds
Started Jan 24 08:29:09 PM PST 24
Finished Jan 24 08:47:53 PM PST 24
Peak memory 201244 kb
Host smart-396b038f-7281-4979-80e9-0e36ce014d06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352981793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2352981793
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3000528133
Short name T846
Test name
Test status
Simulation time 126937898816 ps
CPU time 534.27 seconds
Started Jan 24 07:18:34 PM PST 24
Finished Jan 24 07:27:29 PM PST 24
Peak memory 201444 kb
Host smart-e0b6dd3f-2887-4bbc-98f3-1317f3fc3b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000528133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3000528133
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1913270511
Short name T550
Test name
Test status
Simulation time 26208394385 ps
CPU time 16.03 seconds
Started Jan 24 07:18:34 PM PST 24
Finished Jan 24 07:18:51 PM PST 24
Peak memory 200960 kb
Host smart-9cdfb6dc-087f-4783-a1c5-2be1d92015ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913270511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1913270511
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1556033452
Short name T454
Test name
Test status
Simulation time 3480073692 ps
CPU time 9.09 seconds
Started Jan 24 07:18:26 PM PST 24
Finished Jan 24 07:18:36 PM PST 24
Peak memory 201028 kb
Host smart-af1741fd-cc0c-4120-89a8-1653c1d0f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556033452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1556033452
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1223437600
Short name T609
Test name
Test status
Simulation time 6253770375 ps
CPU time 4.36 seconds
Started Jan 24 07:18:06 PM PST 24
Finished Jan 24 07:18:12 PM PST 24
Peak memory 200980 kb
Host smart-0da4b63a-ff2b-4bba-9578-bc123dd481e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223437600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1223437600
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1926375043
Short name T618
Test name
Test status
Simulation time 220390658837 ps
CPU time 117.13 seconds
Started Jan 24 07:18:35 PM PST 24
Finished Jan 24 07:20:34 PM PST 24
Peak memory 201188 kb
Host smart-23b9e7d9-fda0-4969-bf9a-700700253956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926375043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1926375043
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.501717560
Short name T472
Test name
Test status
Simulation time 442945431 ps
CPU time 0.69 seconds
Started Jan 24 07:19:05 PM PST 24
Finished Jan 24 07:19:07 PM PST 24
Peak memory 200864 kb
Host smart-4bd24498-6365-4006-a835-243fcc1c12ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501717560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.501717560
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1190139724
Short name T173
Test name
Test status
Simulation time 161929696491 ps
CPU time 398.94 seconds
Started Jan 24 07:18:58 PM PST 24
Finished Jan 24 07:25:37 PM PST 24
Peak memory 201172 kb
Host smart-b10ac8b5-c00d-4713-aca4-35d4390af89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190139724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1190139724
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3542994522
Short name T92
Test name
Test status
Simulation time 325652414022 ps
CPU time 55.96 seconds
Started Jan 24 07:18:41 PM PST 24
Finished Jan 24 07:19:38 PM PST 24
Peak memory 201132 kb
Host smart-30c5ce14-ff71-4b4f-ac9f-004e445bacc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542994522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3542994522
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2527205796
Short name T220
Test name
Test status
Simulation time 325866610776 ps
CPU time 381.89 seconds
Started Jan 24 07:18:40 PM PST 24
Finished Jan 24 07:25:03 PM PST 24
Peak memory 201056 kb
Host smart-4a2184fc-3138-450f-a92d-0b12679c8e13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527205796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2527205796
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2228537721
Short name T562
Test name
Test status
Simulation time 329469499846 ps
CPU time 723.14 seconds
Started Jan 24 07:18:39 PM PST 24
Finished Jan 24 07:30:43 PM PST 24
Peak memory 201108 kb
Host smart-6bac7cbe-6021-42e7-8dd5-9dd4acb08a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228537721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2228537721
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3881639206
Short name T460
Test name
Test status
Simulation time 488276966848 ps
CPU time 512.4 seconds
Started Jan 24 07:18:41 PM PST 24
Finished Jan 24 07:27:14 PM PST 24
Peak memory 201220 kb
Host smart-47e73b92-a32f-4b79-b0cd-0d5a9655e897
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881639206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3881639206
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3196078028
Short name T341
Test name
Test status
Simulation time 339447973847 ps
CPU time 820.16 seconds
Started Jan 24 07:18:44 PM PST 24
Finished Jan 24 07:32:25 PM PST 24
Peak memory 201152 kb
Host smart-82ec12e8-06a0-4277-bb96-f6abc0e6e243
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196078028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3196078028
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3512112365
Short name T701
Test name
Test status
Simulation time 325157489165 ps
CPU time 170.69 seconds
Started Jan 24 07:18:44 PM PST 24
Finished Jan 24 07:21:35 PM PST 24
Peak memory 201148 kb
Host smart-6fca7e70-7f5e-4410-b4e6-61b3583bcdc9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512112365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3512112365
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2402499128
Short name T41
Test name
Test status
Simulation time 99425039345 ps
CPU time 549.11 seconds
Started Jan 24 07:18:55 PM PST 24
Finished Jan 24 07:28:05 PM PST 24
Peak memory 201596 kb
Host smart-024cc055-812b-490f-9809-e2948c578dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402499128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2402499128
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1119218647
Short name T633
Test name
Test status
Simulation time 27826952122 ps
CPU time 68.81 seconds
Started Jan 24 07:18:55 PM PST 24
Finished Jan 24 07:20:05 PM PST 24
Peak memory 201000 kb
Host smart-8a1ab276-c560-4a62-9176-08ba28f69974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119218647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1119218647
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1941417320
Short name T688
Test name
Test status
Simulation time 3522700527 ps
CPU time 2.7 seconds
Started Jan 24 07:19:03 PM PST 24
Finished Jan 24 07:19:07 PM PST 24
Peak memory 201004 kb
Host smart-0fce46db-6166-49a8-b2c6-842f01947d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941417320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1941417320
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4219599147
Short name T648
Test name
Test status
Simulation time 5870561419 ps
CPU time 4.01 seconds
Started Jan 24 07:35:35 PM PST 24
Finished Jan 24 07:35:42 PM PST 24
Peak memory 201048 kb
Host smart-6b69c8b2-105f-4942-a5bf-23657e0bdac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219599147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4219599147
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3939287822
Short name T533
Test name
Test status
Simulation time 499311311309 ps
CPU time 185.6 seconds
Started Jan 24 07:19:02 PM PST 24
Finished Jan 24 07:22:09 PM PST 24
Peak memory 201212 kb
Host smart-f854ae35-1aa2-47f6-a81c-9537a2394573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939287822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3939287822
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1521702767
Short name T317
Test name
Test status
Simulation time 18196741026 ps
CPU time 43.85 seconds
Started Jan 24 07:18:57 PM PST 24
Finished Jan 24 07:19:41 PM PST 24
Peak memory 201188 kb
Host smart-667b9f37-8723-42d8-8dd5-5bb42ec4267d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521702767 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1521702767
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2411840685
Short name T443
Test name
Test status
Simulation time 445393488 ps
CPU time 1.6 seconds
Started Jan 24 07:47:02 PM PST 24
Finished Jan 24 07:47:07 PM PST 24
Peak memory 200924 kb
Host smart-157916eb-4dcc-4c74-bac4-2cb61daec787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411840685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2411840685
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.903117289
Short name T311
Test name
Test status
Simulation time 487998349148 ps
CPU time 450.34 seconds
Started Jan 24 07:19:10 PM PST 24
Finished Jan 24 07:26:41 PM PST 24
Peak memory 201236 kb
Host smart-cc55f410-c418-400a-a4c9-3e2db7436148
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903117289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.903117289
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1335577713
Short name T265
Test name
Test status
Simulation time 493189101908 ps
CPU time 1086.51 seconds
Started Jan 24 07:22:45 PM PST 24
Finished Jan 24 07:40:56 PM PST 24
Peak memory 201264 kb
Host smart-d5acb3f7-ed74-4dc9-9378-3ddf991f9136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335577713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1335577713
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3033390958
Short name T591
Test name
Test status
Simulation time 321490076375 ps
CPU time 776.19 seconds
Started Jan 24 07:19:07 PM PST 24
Finished Jan 24 07:32:04 PM PST 24
Peak memory 201164 kb
Host smart-d5bd9bcb-ad5f-48c8-b554-399012e13125
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033390958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3033390958
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.587739516
Short name T518
Test name
Test status
Simulation time 329458435696 ps
CPU time 733.77 seconds
Started Jan 24 07:19:04 PM PST 24
Finished Jan 24 07:31:19 PM PST 24
Peak memory 201148 kb
Host smart-4f150eab-faf8-420d-9858-313723973f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587739516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.587739516
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2455957098
Short name T717
Test name
Test status
Simulation time 163682833653 ps
CPU time 37.72 seconds
Started Jan 24 07:19:09 PM PST 24
Finished Jan 24 07:19:47 PM PST 24
Peak memory 201152 kb
Host smart-80c3f5ef-f836-4199-99fb-942fd7740a38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455957098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2455957098
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1654414940
Short name T348
Test name
Test status
Simulation time 166888125360 ps
CPU time 113.75 seconds
Started Jan 24 07:19:10 PM PST 24
Finished Jan 24 07:21:04 PM PST 24
Peak memory 201260 kb
Host smart-7a8deaa7-fd6c-4045-b778-ac238705f564
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654414940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1654414940
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1998922237
Short name T766
Test name
Test status
Simulation time 335283048877 ps
CPU time 790.81 seconds
Started Jan 24 07:19:10 PM PST 24
Finished Jan 24 07:32:21 PM PST 24
Peak memory 201172 kb
Host smart-7c81d14b-9b51-46ca-969f-60f297d52093
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998922237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1998922237
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4016156674
Short name T698
Test name
Test status
Simulation time 38869709855 ps
CPU time 22.38 seconds
Started Jan 24 07:19:21 PM PST 24
Finished Jan 24 07:19:44 PM PST 24
Peak memory 201008 kb
Host smart-1e15aacf-1e08-4cda-99b5-3c0127890ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016156674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.4016156674
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1658603009
Short name T461
Test name
Test status
Simulation time 3133193131 ps
CPU time 8.26 seconds
Started Jan 24 07:19:21 PM PST 24
Finished Jan 24 07:19:30 PM PST 24
Peak memory 201000 kb
Host smart-ab8dcb65-a9b1-479f-9da0-1df52baf7ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658603009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1658603009
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4182279157
Short name T436
Test name
Test status
Simulation time 5764009147 ps
CPU time 13.41 seconds
Started Jan 24 07:19:03 PM PST 24
Finished Jan 24 07:19:17 PM PST 24
Peak memory 200964 kb
Host smart-f886cfa2-118e-40e1-b45a-efe5ba75b66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182279157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4182279157
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2287578039
Short name T490
Test name
Test status
Simulation time 86525642262 ps
CPU time 78.65 seconds
Started Jan 24 07:19:24 PM PST 24
Finished Jan 24 07:20:44 PM PST 24
Peak memory 209448 kb
Host smart-525a4a83-4035-446e-bc92-67172879f17f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287578039 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2287578039
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.65118531
Short name T598
Test name
Test status
Simulation time 416266856 ps
CPU time 0.76 seconds
Started Jan 24 07:19:46 PM PST 24
Finished Jan 24 07:19:48 PM PST 24
Peak memory 200864 kb
Host smart-899fb99e-0bb1-4521-82bf-a335161cbce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65118531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.65118531
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1401057318
Short name T229
Test name
Test status
Simulation time 167200392464 ps
CPU time 384.47 seconds
Started Jan 24 07:19:35 PM PST 24
Finished Jan 24 07:26:01 PM PST 24
Peak memory 201200 kb
Host smart-9dce51bf-db1c-4021-99e5-b914741c7163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401057318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1401057318
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.894481127
Short name T218
Test name
Test status
Simulation time 488623043231 ps
CPU time 1223.68 seconds
Started Jan 24 07:19:36 PM PST 24
Finished Jan 24 07:40:01 PM PST 24
Peak memory 201260 kb
Host smart-ad4fa66d-9e37-44a7-b9ae-c2e7c40206b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894481127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.894481127
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.416349593
Short name T475
Test name
Test status
Simulation time 323766917974 ps
CPU time 137.16 seconds
Started Jan 24 07:19:32 PM PST 24
Finished Jan 24 07:21:50 PM PST 24
Peak memory 201096 kb
Host smart-cd61e51f-c0a1-4c74-8f8e-ae07d79bef78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=416349593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.416349593
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1673587384
Short name T290
Test name
Test status
Simulation time 160650264023 ps
CPU time 241.99 seconds
Started Jan 24 07:19:23 PM PST 24
Finished Jan 24 07:23:26 PM PST 24
Peak memory 201256 kb
Host smart-05ac48c2-1543-4eec-a66a-fd8607ee5d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673587384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1673587384
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1732569054
Short name T483
Test name
Test status
Simulation time 163040090968 ps
CPU time 188.63 seconds
Started Jan 24 07:56:09 PM PST 24
Finished Jan 24 07:59:18 PM PST 24
Peak memory 201172 kb
Host smart-50a59b39-2653-40f3-8676-3c7d1654aacf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732569054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1732569054
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1380424270
Short name T679
Test name
Test status
Simulation time 334558555860 ps
CPU time 731.76 seconds
Started Jan 24 07:19:35 PM PST 24
Finished Jan 24 07:31:48 PM PST 24
Peak memory 201176 kb
Host smart-f9db7924-9ab9-4959-8dd0-09900192e72e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380424270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1380424270
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.653696931
Short name T540
Test name
Test status
Simulation time 332857745235 ps
CPU time 780.63 seconds
Started Jan 24 07:19:34 PM PST 24
Finished Jan 24 07:32:36 PM PST 24
Peak memory 201260 kb
Host smart-2d6a1463-e9a8-477a-86a6-0e32deda3596
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653696931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.653696931
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.393213436
Short name T362
Test name
Test status
Simulation time 113109559502 ps
CPU time 483.94 seconds
Started Jan 24 08:58:57 PM PST 24
Finished Jan 24 09:07:03 PM PST 24
Peak memory 201596 kb
Host smart-d9ff204d-d418-47a9-bf14-dcaa82106823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393213436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.393213436
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3090675646
Short name T575
Test name
Test status
Simulation time 44700257043 ps
CPU time 27.65 seconds
Started Jan 24 07:19:42 PM PST 24
Finished Jan 24 07:20:14 PM PST 24
Peak memory 200956 kb
Host smart-6816f823-2340-4330-9424-8c55738a8291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090675646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3090675646
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4261664746
Short name T486
Test name
Test status
Simulation time 3189460451 ps
CPU time 8.06 seconds
Started Jan 24 07:19:40 PM PST 24
Finished Jan 24 07:19:49 PM PST 24
Peak memory 201032 kb
Host smart-791f41f7-2946-475d-a597-1e276809b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261664746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4261664746
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3624144651
Short name T471
Test name
Test status
Simulation time 6075060719 ps
CPU time 2.1 seconds
Started Jan 24 07:19:23 PM PST 24
Finished Jan 24 07:19:26 PM PST 24
Peak memory 200984 kb
Host smart-3a7d3ff6-6df8-41b4-afc8-648d3fbbf331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624144651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3624144651
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.114202029
Short name T259
Test name
Test status
Simulation time 205408857892 ps
CPU time 394.59 seconds
Started Jan 24 07:38:51 PM PST 24
Finished Jan 24 07:45:33 PM PST 24
Peak memory 201292 kb
Host smart-cc4934ee-1128-4fed-8824-f0f5ac149704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114202029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
114202029
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3395784744
Short name T786
Test name
Test status
Simulation time 241930535015 ps
CPU time 228.87 seconds
Started Jan 24 07:19:42 PM PST 24
Finished Jan 24 07:23:36 PM PST 24
Peak memory 209772 kb
Host smart-58fa9277-8612-424a-b9c8-04bde14009e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395784744 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3395784744
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.469030558
Short name T753
Test name
Test status
Simulation time 311650148 ps
CPU time 0.93 seconds
Started Jan 24 07:20:09 PM PST 24
Finished Jan 24 07:20:17 PM PST 24
Peak memory 200680 kb
Host smart-b0e3b1db-5a26-48a2-98ff-d220906295c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469030558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.469030558
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1874060361
Short name T294
Test name
Test status
Simulation time 164162920214 ps
CPU time 352.99 seconds
Started Jan 24 07:19:53 PM PST 24
Finished Jan 24 07:25:47 PM PST 24
Peak memory 201260 kb
Host smart-d54c2917-16c5-4fe9-a856-b7c9dada3e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874060361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1874060361
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1582564108
Short name T573
Test name
Test status
Simulation time 497927467666 ps
CPU time 571.45 seconds
Started Jan 24 08:26:42 PM PST 24
Finished Jan 24 08:36:14 PM PST 24
Peak memory 201180 kb
Host smart-b1db6dc9-58d8-4364-a0c9-cadbaa6f98ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582564108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1582564108
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2358754665
Short name T704
Test name
Test status
Simulation time 328962106838 ps
CPU time 723.5 seconds
Started Jan 24 07:19:52 PM PST 24
Finished Jan 24 07:31:57 PM PST 24
Peak memory 201212 kb
Host smart-9fd73e10-ff5a-4a0d-9e51-0552be16ad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358754665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2358754665
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.4202008976
Short name T556
Test name
Test status
Simulation time 332129854272 ps
CPU time 136.67 seconds
Started Jan 24 07:19:55 PM PST 24
Finished Jan 24 07:22:13 PM PST 24
Peak memory 201216 kb
Host smart-5d45e11e-4a19-481c-91a3-d4a1ebcd54a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202008976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.4202008976
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.369697444
Short name T271
Test name
Test status
Simulation time 164473522213 ps
CPU time 198.5 seconds
Started Jan 24 07:19:58 PM PST 24
Finished Jan 24 07:23:19 PM PST 24
Peak memory 201240 kb
Host smart-aa5ae0c0-5d6f-46e8-8eef-53fb576e0bd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369697444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.369697444
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.103748687
Short name T480
Test name
Test status
Simulation time 494019751808 ps
CPU time 327.26 seconds
Started Jan 24 07:19:58 PM PST 24
Finished Jan 24 07:25:27 PM PST 24
Peak memory 201176 kb
Host smart-0b1bedf0-92e1-432a-a7d4-9a30043da2e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103748687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.103748687
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.816947611
Short name T203
Test name
Test status
Simulation time 109312277649 ps
CPU time 619.28 seconds
Started Jan 24 07:20:00 PM PST 24
Finished Jan 24 07:30:22 PM PST 24
Peak memory 201504 kb
Host smart-c38c7af2-b452-48b0-b04e-3a73af5437c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816947611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.816947611
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.664847764
Short name T535
Test name
Test status
Simulation time 29306467481 ps
CPU time 29 seconds
Started Jan 24 09:09:40 PM PST 24
Finished Jan 24 09:10:10 PM PST 24
Peak memory 201048 kb
Host smart-e8979298-f6e5-4528-ba38-fe77e8159ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664847764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.664847764
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3193621605
Short name T113
Test name
Test status
Simulation time 4100766718 ps
CPU time 9.8 seconds
Started Jan 24 07:41:15 PM PST 24
Finished Jan 24 07:41:25 PM PST 24
Peak memory 201060 kb
Host smart-2f45c79a-bec7-48b5-a01f-66ec6429f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193621605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3193621605
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1006399185
Short name T427
Test name
Test status
Simulation time 5562546704 ps
CPU time 14.18 seconds
Started Jan 24 07:19:54 PM PST 24
Finished Jan 24 07:20:09 PM PST 24
Peak memory 201008 kb
Host smart-6baec0f6-4da8-4c85-be95-f678ce922d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006399185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1006399185
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3085688501
Short name T111
Test name
Test status
Simulation time 299564594188 ps
CPU time 82.52 seconds
Started Jan 24 08:08:14 PM PST 24
Finished Jan 24 08:09:38 PM PST 24
Peak memory 201448 kb
Host smart-1628d98c-3a23-44d7-b939-9ec2a157dcf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085688501 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3085688501
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3982547575
Short name T588
Test name
Test status
Simulation time 516815350 ps
CPU time 0.84 seconds
Started Jan 24 07:08:09 PM PST 24
Finished Jan 24 07:08:10 PM PST 24
Peak memory 200812 kb
Host smart-4281b26e-82e5-4b63-8ba2-2ddc8e26bedc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982547575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3982547575
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1209094225
Short name T263
Test name
Test status
Simulation time 166357425949 ps
CPU time 51.88 seconds
Started Jan 24 07:07:57 PM PST 24
Finished Jan 24 07:08:51 PM PST 24
Peak memory 201268 kb
Host smart-c368d057-83aa-4fad-ae78-9eb396fae052
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209094225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1209094225
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2930653575
Short name T690
Test name
Test status
Simulation time 324210681976 ps
CPU time 426.34 seconds
Started Jan 24 07:07:50 PM PST 24
Finished Jan 24 07:14:58 PM PST 24
Peak memory 201200 kb
Host smart-3632b130-c8b0-48be-a09b-a38025799911
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930653575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2930653575
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.462038489
Short name T63
Test name
Test status
Simulation time 160898411105 ps
CPU time 82.15 seconds
Started Jan 24 07:07:50 PM PST 24
Finished Jan 24 07:09:14 PM PST 24
Peak memory 201236 kb
Host smart-b478e172-0e7c-4424-895a-306f68deabaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462038489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.462038489
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2313896706
Short name T571
Test name
Test status
Simulation time 329652835704 ps
CPU time 178.75 seconds
Started Jan 24 07:07:49 PM PST 24
Finished Jan 24 07:10:50 PM PST 24
Peak memory 201112 kb
Host smart-d17a449e-17f6-44bd-ab5b-01c0a27fbc9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313896706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2313896706
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2057971376
Short name T232
Test name
Test status
Simulation time 166621253901 ps
CPU time 217.67 seconds
Started Jan 24 07:42:50 PM PST 24
Finished Jan 24 07:46:29 PM PST 24
Peak memory 201264 kb
Host smart-0152192d-fbc2-4fbf-80dc-55d83168a678
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057971376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2057971376
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4271926200
Short name T745
Test name
Test status
Simulation time 168805291712 ps
CPU time 195.13 seconds
Started Jan 24 07:07:57 PM PST 24
Finished Jan 24 07:11:14 PM PST 24
Peak memory 201192 kb
Host smart-7a3cdfdd-7af7-49fe-9045-309e73ccd6da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271926200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4271926200
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.122941652
Short name T729
Test name
Test status
Simulation time 86125312899 ps
CPU time 377.26 seconds
Started Jan 24 07:07:57 PM PST 24
Finished Jan 24 07:14:16 PM PST 24
Peak memory 201492 kb
Host smart-bbd6a365-5952-4260-99f7-9663b5cd9d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122941652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.122941652
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2264145308
Short name T453
Test name
Test status
Simulation time 43118799014 ps
CPU time 105.58 seconds
Started Jan 24 07:07:56 PM PST 24
Finished Jan 24 07:09:44 PM PST 24
Peak memory 201020 kb
Host smart-829492b5-e690-421a-9c51-bc048fe62287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264145308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2264145308
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1026346800
Short name T714
Test name
Test status
Simulation time 4539758359 ps
CPU time 4.52 seconds
Started Jan 24 07:07:58 PM PST 24
Finished Jan 24 07:08:04 PM PST 24
Peak memory 201048 kb
Host smart-5dfd4114-657c-452e-a103-944dc994a978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026346800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1026346800
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.941911618
Short name T48
Test name
Test status
Simulation time 8484410414 ps
CPU time 5.85 seconds
Started Jan 24 07:07:59 PM PST 24
Finished Jan 24 07:08:08 PM PST 24
Peak memory 217444 kb
Host smart-9d0f69de-748d-4f5d-860d-b747fc0a9916
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941911618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.941911618
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2826628163
Short name T441
Test name
Test status
Simulation time 5736737263 ps
CPU time 14.93 seconds
Started Jan 24 07:43:57 PM PST 24
Finished Jan 24 07:44:13 PM PST 24
Peak memory 201068 kb
Host smart-5439234d-92f7-4732-9f52-2f2f2259ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826628163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2826628163
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3624249195
Short name T768
Test name
Test status
Simulation time 329450160997 ps
CPU time 156.02 seconds
Started Jan 24 07:07:57 PM PST 24
Finished Jan 24 07:10:34 PM PST 24
Peak memory 209572 kb
Host smart-9a6dac66-a7ac-41cb-b936-7c8110e0f630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624249195 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3624249195
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.78831655
Short name T678
Test name
Test status
Simulation time 512060126 ps
CPU time 0.95 seconds
Started Jan 24 07:20:37 PM PST 24
Finished Jan 24 07:20:44 PM PST 24
Peak memory 200904 kb
Host smart-b5641324-267f-4278-a246-188a9fcadf62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78831655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.78831655
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2301149667
Short name T96
Test name
Test status
Simulation time 490503921216 ps
CPU time 342.3 seconds
Started Jan 24 07:20:18 PM PST 24
Finished Jan 24 07:26:04 PM PST 24
Peak memory 201192 kb
Host smart-697fa467-fe0f-434b-a2da-baeb033211a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301149667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2301149667
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2715057717
Short name T305
Test name
Test status
Simulation time 334989917359 ps
CPU time 254.34 seconds
Started Jan 24 07:20:17 PM PST 24
Finished Jan 24 07:24:36 PM PST 24
Peak memory 201260 kb
Host smart-80b7b4cf-c583-405e-8bb2-26dcafb4042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715057717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2715057717
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3320330711
Short name T249
Test name
Test status
Simulation time 331331055588 ps
CPU time 402.32 seconds
Started Jan 24 07:20:11 PM PST 24
Finished Jan 24 07:26:59 PM PST 24
Peak memory 201052 kb
Host smart-570e043e-cf2e-4def-93fa-1d1df1dc9ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320330711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3320330711
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2141910144
Short name T723
Test name
Test status
Simulation time 163693472923 ps
CPU time 60.46 seconds
Started Jan 24 07:20:14 PM PST 24
Finished Jan 24 07:21:21 PM PST 24
Peak memory 201180 kb
Host smart-088f58fc-6935-4dcf-86dc-524c55f349a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141910144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2141910144
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.71893958
Short name T208
Test name
Test status
Simulation time 491987117293 ps
CPU time 1071.47 seconds
Started Jan 24 07:20:15 PM PST 24
Finished Jan 24 07:38:12 PM PST 24
Peak memory 201280 kb
Host smart-0b7fcce6-6706-4f10-9ca5-0efc0bcb073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71893958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.71893958
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2821087182
Short name T810
Test name
Test status
Simulation time 486462112762 ps
CPU time 549.12 seconds
Started Jan 24 07:41:57 PM PST 24
Finished Jan 24 07:51:17 PM PST 24
Peak memory 201176 kb
Host smart-2e45ec5a-9671-4d97-969c-58a6708a4364
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821087182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2821087182
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1174882430
Short name T577
Test name
Test status
Simulation time 327738930335 ps
CPU time 125.12 seconds
Started Jan 24 07:20:11 PM PST 24
Finished Jan 24 07:22:21 PM PST 24
Peak memory 201176 kb
Host smart-ad280a12-8e90-4d15-a563-9277af73b34e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174882430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1174882430
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.485800230
Short name T561
Test name
Test status
Simulation time 489315029282 ps
CPU time 296.85 seconds
Started Jan 24 07:20:15 PM PST 24
Finished Jan 24 07:25:18 PM PST 24
Peak memory 201168 kb
Host smart-3c541155-2689-4a57-b3c6-77fb8fc08ada
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485800230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.485800230
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1357873554
Short name T680
Test name
Test status
Simulation time 89854838357 ps
CPU time 312.4 seconds
Started Jan 24 08:14:01 PM PST 24
Finished Jan 24 08:19:16 PM PST 24
Peak memory 201580 kb
Host smart-a83342b4-7597-4500-a020-6c4777c634ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357873554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1357873554
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4075600239
Short name T814
Test name
Test status
Simulation time 26478834197 ps
CPU time 16.14 seconds
Started Jan 24 07:20:28 PM PST 24
Finished Jan 24 07:20:45 PM PST 24
Peak memory 201028 kb
Host smart-c10cd91f-5c0e-4947-ac18-23e16fb0f7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075600239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4075600239
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.923731384
Short name T775
Test name
Test status
Simulation time 5016832446 ps
CPU time 6.96 seconds
Started Jan 24 07:20:24 PM PST 24
Finished Jan 24 07:20:32 PM PST 24
Peak memory 200920 kb
Host smart-97b0eef2-c23e-4f70-b5a0-6ef2356f619b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923731384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.923731384
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2899095955
Short name T825
Test name
Test status
Simulation time 5972492355 ps
CPU time 4.65 seconds
Started Jan 24 07:53:07 PM PST 24
Finished Jan 24 07:53:13 PM PST 24
Peak memory 201060 kb
Host smart-6e89b63b-2766-455b-83e3-d6e82a11c0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899095955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2899095955
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3096513330
Short name T345
Test name
Test status
Simulation time 167441806703 ps
CPU time 409.94 seconds
Started Jan 24 07:20:29 PM PST 24
Finished Jan 24 07:27:20 PM PST 24
Peak memory 201076 kb
Host smart-e7a46111-a28b-4240-a073-e8cfc81a8a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096513330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3096513330
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.4289562771
Short name T275
Test name
Test status
Simulation time 72024359991 ps
CPU time 121.41 seconds
Started Jan 24 07:36:00 PM PST 24
Finished Jan 24 07:38:10 PM PST 24
Peak memory 209940 kb
Host smart-7e6a2ab8-461c-446a-bde9-c6760b9c0671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289562771 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.4289562771
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3955670870
Short name T497
Test name
Test status
Simulation time 485412625 ps
CPU time 1.64 seconds
Started Jan 24 07:21:07 PM PST 24
Finished Jan 24 07:21:10 PM PST 24
Peak memory 200812 kb
Host smart-967384da-f23d-481c-91c2-30041a814c4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955670870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3955670870
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.144612320
Short name T545
Test name
Test status
Simulation time 167855727403 ps
CPU time 47.31 seconds
Started Jan 24 07:20:44 PM PST 24
Finished Jan 24 07:21:35 PM PST 24
Peak memory 201244 kb
Host smart-bb723ffd-bc64-4600-963a-9c91f058a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144612320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.144612320
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1589970170
Short name T479
Test name
Test status
Simulation time 487588956405 ps
CPU time 587.59 seconds
Started Jan 24 07:46:02 PM PST 24
Finished Jan 24 07:55:52 PM PST 24
Peak memory 201188 kb
Host smart-ad70ede8-0bca-4574-89dd-d21c81d11929
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589970170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1589970170
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3454688515
Short name T671
Test name
Test status
Simulation time 164687309794 ps
CPU time 357.58 seconds
Started Jan 24 07:20:36 PM PST 24
Finished Jan 24 07:26:34 PM PST 24
Peak memory 201196 kb
Host smart-c47f904d-d220-4cc3-9c28-334c83c8e862
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454688515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3454688515
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1317887981
Short name T170
Test name
Test status
Simulation time 488802591330 ps
CPU time 258.96 seconds
Started Jan 24 07:20:45 PM PST 24
Finished Jan 24 07:25:08 PM PST 24
Peak memory 201200 kb
Host smart-3bd8b6da-e3dd-4115-9367-7dbf2b0c1b37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317887981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1317887981
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1456821645
Short name T603
Test name
Test status
Simulation time 493600169163 ps
CPU time 274.2 seconds
Started Jan 24 07:20:52 PM PST 24
Finished Jan 24 07:25:28 PM PST 24
Peak memory 201096 kb
Host smart-7617726d-a7fc-4d68-8087-893eb914a64f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456821645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1456821645
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1848470723
Short name T55
Test name
Test status
Simulation time 108756329617 ps
CPU time 388.61 seconds
Started Jan 24 07:20:54 PM PST 24
Finished Jan 24 07:27:24 PM PST 24
Peak memory 201504 kb
Host smart-e4ea3235-6c77-49ce-8313-a01cf19113db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848470723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1848470723
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4110386672
Short name T19
Test name
Test status
Simulation time 26049032880 ps
CPU time 16.16 seconds
Started Jan 24 07:20:51 PM PST 24
Finished Jan 24 07:21:09 PM PST 24
Peak memory 200960 kb
Host smart-d0a4937f-6bde-4b5b-a909-46a5fa325395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110386672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4110386672
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1730716626
Short name T601
Test name
Test status
Simulation time 4596197994 ps
CPU time 10.86 seconds
Started Jan 24 07:20:46 PM PST 24
Finished Jan 24 07:21:00 PM PST 24
Peak memory 200928 kb
Host smart-970e44d1-72f7-4aa2-a896-04313513dc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730716626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1730716626
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2805238561
Short name T509
Test name
Test status
Simulation time 5575284903 ps
CPU time 4.23 seconds
Started Jan 24 09:21:37 PM PST 24
Finished Jan 24 09:21:49 PM PST 24
Peak memory 201004 kb
Host smart-532839d7-1edf-4d31-b209-b1262bc68c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805238561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2805238561
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3659029057
Short name T346
Test name
Test status
Simulation time 544570583731 ps
CPU time 239.46 seconds
Started Jan 24 09:54:55 PM PST 24
Finished Jan 24 09:58:56 PM PST 24
Peak memory 201252 kb
Host smart-875a845c-a1a1-40fd-a178-e505f367ac7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659029057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3659029057
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.763716272
Short name T367
Test name
Test status
Simulation time 66968988043 ps
CPU time 271.27 seconds
Started Jan 24 07:20:53 PM PST 24
Finished Jan 24 07:25:25 PM PST 24
Peak memory 209784 kb
Host smart-ac279fe3-726b-4a0d-8f7d-bb0e8d3c9726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763716272 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.763716272
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.247678754
Short name T462
Test name
Test status
Simulation time 427711159 ps
CPU time 1.14 seconds
Started Jan 24 07:21:29 PM PST 24
Finished Jan 24 07:21:31 PM PST 24
Peak memory 200892 kb
Host smart-1cf46ae7-1cac-478f-a2a4-1bf489a69ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247678754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.247678754
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3297752155
Short name T168
Test name
Test status
Simulation time 163859253138 ps
CPU time 109.94 seconds
Started Jan 24 07:21:16 PM PST 24
Finished Jan 24 07:23:07 PM PST 24
Peak memory 201060 kb
Host smart-0214c2dc-6aad-4200-8ac6-04bd40980057
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297752155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3297752155
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2578067815
Short name T171
Test name
Test status
Simulation time 163993111242 ps
CPU time 157.9 seconds
Started Jan 24 07:21:19 PM PST 24
Finished Jan 24 07:23:58 PM PST 24
Peak memory 201236 kb
Host smart-6159e97f-6968-4842-89c1-b96b8005971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578067815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2578067815
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3777378234
Short name T642
Test name
Test status
Simulation time 164429489209 ps
CPU time 105.3 seconds
Started Jan 24 07:21:08 PM PST 24
Finished Jan 24 07:22:56 PM PST 24
Peak memory 201244 kb
Host smart-e05bae10-d3a2-4fcf-94aa-94fe8fb952ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777378234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3777378234
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.232747349
Short name T666
Test name
Test status
Simulation time 337237534564 ps
CPU time 197.44 seconds
Started Jan 24 07:20:59 PM PST 24
Finished Jan 24 07:24:19 PM PST 24
Peak memory 201172 kb
Host smart-4d659cdd-24b3-43c6-ac64-5247c3fecc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232747349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.232747349
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3877836048
Short name T732
Test name
Test status
Simulation time 490441647401 ps
CPU time 1086.82 seconds
Started Jan 24 07:20:58 PM PST 24
Finished Jan 24 07:39:08 PM PST 24
Peak memory 201128 kb
Host smart-997b7143-4316-4ef1-94f1-1c40c1dffde5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877836048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3877836048
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.4275745370
Short name T568
Test name
Test status
Simulation time 492150703052 ps
CPU time 523.71 seconds
Started Jan 24 07:21:10 PM PST 24
Finished Jan 24 07:29:55 PM PST 24
Peak memory 201216 kb
Host smart-297f4685-0001-47a1-a49d-fd98a97aa1b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275745370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.4275745370
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1001467836
Short name T696
Test name
Test status
Simulation time 160038468793 ps
CPU time 97.17 seconds
Started Jan 24 07:21:16 PM PST 24
Finished Jan 24 07:22:55 PM PST 24
Peak memory 201172 kb
Host smart-0eb83f79-ed09-43b0-9fb8-a6ee53a26b88
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001467836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1001467836
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2594825217
Short name T430
Test name
Test status
Simulation time 100530777673 ps
CPU time 368.48 seconds
Started Jan 24 07:21:29 PM PST 24
Finished Jan 24 07:27:39 PM PST 24
Peak memory 201480 kb
Host smart-f028eddf-cb97-4393-b6ac-57676a7c4db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594825217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2594825217
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1756496153
Short name T827
Test name
Test status
Simulation time 43814957923 ps
CPU time 54.03 seconds
Started Jan 24 07:21:19 PM PST 24
Finished Jan 24 07:22:14 PM PST 24
Peak memory 201020 kb
Host smart-bacdb692-2955-479d-a2a0-5d7055ed0172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756496153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1756496153
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3468009954
Short name T526
Test name
Test status
Simulation time 3769488039 ps
CPU time 4.92 seconds
Started Jan 24 07:21:20 PM PST 24
Finished Jan 24 07:21:26 PM PST 24
Peak memory 201016 kb
Host smart-10b09d26-3fc9-45b7-a0b9-0c18408451d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468009954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3468009954
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.303822366
Short name T683
Test name
Test status
Simulation time 6151401169 ps
CPU time 8.05 seconds
Started Jan 24 07:20:58 PM PST 24
Finished Jan 24 07:21:09 PM PST 24
Peak memory 200952 kb
Host smart-e722f066-f05d-45bc-b254-6c2b7997afd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303822366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.303822366
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2309981278
Short name T687
Test name
Test status
Simulation time 416795532 ps
CPU time 0.85 seconds
Started Jan 24 07:21:58 PM PST 24
Finished Jan 24 07:21:59 PM PST 24
Peak memory 200932 kb
Host smart-e795b2f3-773a-4c13-837d-a6a3d1dd28d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309981278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2309981278
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3823734312
Short name T780
Test name
Test status
Simulation time 487193794927 ps
CPU time 1069.46 seconds
Started Jan 24 07:32:35 PM PST 24
Finished Jan 24 07:50:27 PM PST 24
Peak memory 201216 kb
Host smart-1178fd1f-5be0-438d-b3ac-878644e9c2c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823734312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3823734312
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.920584623
Short name T110
Test name
Test status
Simulation time 324170427220 ps
CPU time 714.16 seconds
Started Jan 24 07:21:32 PM PST 24
Finished Jan 24 07:33:27 PM PST 24
Peak memory 201276 kb
Host smart-64f7710d-42bc-42d9-8dff-e69bd5dacaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920584623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.920584623
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1766827858
Short name T474
Test name
Test status
Simulation time 334928784288 ps
CPU time 193.55 seconds
Started Jan 24 07:21:29 PM PST 24
Finished Jan 24 07:24:44 PM PST 24
Peak memory 201196 kb
Host smart-2d462df7-897b-4897-af3d-e0f4fc6a8114
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766827858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1766827858
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.778915875
Short name T309
Test name
Test status
Simulation time 328971659028 ps
CPU time 207.79 seconds
Started Jan 24 07:21:35 PM PST 24
Finished Jan 24 07:25:03 PM PST 24
Peak memory 201216 kb
Host smart-c269bd68-e0d1-4df4-add0-5c4df8811e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778915875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.778915875
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2301510803
Short name T718
Test name
Test status
Simulation time 326135533426 ps
CPU time 745.05 seconds
Started Jan 24 07:21:33 PM PST 24
Finished Jan 24 07:34:00 PM PST 24
Peak memory 201224 kb
Host smart-00be0c2a-c163-4f44-a749-d90f14a9c3b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301510803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2301510803
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.139120750
Short name T761
Test name
Test status
Simulation time 163902267708 ps
CPU time 94.48 seconds
Started Jan 24 07:21:37 PM PST 24
Finished Jan 24 07:23:12 PM PST 24
Peak memory 201140 kb
Host smart-384fcfd5-9fb5-49aa-985d-6878cc5ea19c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139120750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.139120750
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1630522415
Short name T201
Test name
Test status
Simulation time 96038690215 ps
CPU time 542.47 seconds
Started Jan 24 07:21:57 PM PST 24
Finished Jan 24 07:31:01 PM PST 24
Peak memory 201476 kb
Host smart-8040a84c-5acd-4495-a4da-c37b227fd628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630522415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1630522415
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1173408785
Short name T154
Test name
Test status
Simulation time 47176060950 ps
CPU time 55.52 seconds
Started Jan 24 07:21:53 PM PST 24
Finished Jan 24 07:22:49 PM PST 24
Peak memory 201052 kb
Host smart-ed19e42e-548a-4112-9e8f-4ddd7a39ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173408785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1173408785
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3905756374
Short name T558
Test name
Test status
Simulation time 4366632974 ps
CPU time 2.55 seconds
Started Jan 24 07:21:57 PM PST 24
Finished Jan 24 07:22:01 PM PST 24
Peak memory 200952 kb
Host smart-33eb62a2-d9f0-4df9-9b9e-682ecbc8079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905756374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3905756374
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1230162598
Short name T853
Test name
Test status
Simulation time 5872953430 ps
CPU time 3.62 seconds
Started Jan 24 07:21:32 PM PST 24
Finished Jan 24 07:21:37 PM PST 24
Peak memory 200988 kb
Host smart-58f1019c-b5dc-4b55-956d-435e8d97f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230162598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1230162598
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.313249506
Short name T595
Test name
Test status
Simulation time 35484225326 ps
CPU time 40.89 seconds
Started Jan 24 07:21:55 PM PST 24
Finished Jan 24 07:22:37 PM PST 24
Peak memory 201008 kb
Host smart-709d970d-e755-4829-aa0f-62ddbf43a8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313249506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
313249506
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3587011189
Short name T656
Test name
Test status
Simulation time 301091322 ps
CPU time 1.04 seconds
Started Jan 24 07:37:34 PM PST 24
Finished Jan 24 07:37:36 PM PST 24
Peak memory 200928 kb
Host smart-2225b5f4-719b-4603-8c5b-069361a4bcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587011189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3587011189
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3931766231
Short name T715
Test name
Test status
Simulation time 161502404048 ps
CPU time 362.1 seconds
Started Jan 24 07:22:25 PM PST 24
Finished Jan 24 07:28:28 PM PST 24
Peak memory 201236 kb
Host smart-87e4d049-02c0-4598-8eee-dc1f187cc7b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931766231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3931766231
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1794384861
Short name T207
Test name
Test status
Simulation time 332231997035 ps
CPU time 784.52 seconds
Started Jan 24 07:22:26 PM PST 24
Finished Jan 24 07:35:31 PM PST 24
Peak memory 201256 kb
Host smart-5e90419e-7635-4779-8672-f4135aab48b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794384861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1794384861
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3125763031
Short name T331
Test name
Test status
Simulation time 491360217947 ps
CPU time 301.68 seconds
Started Jan 24 07:22:09 PM PST 24
Finished Jan 24 07:27:11 PM PST 24
Peak memory 201188 kb
Host smart-83dbd843-510c-4987-8216-64575dcab617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125763031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3125763031
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1482413181
Short name T749
Test name
Test status
Simulation time 491546101024 ps
CPU time 1171.84 seconds
Started Jan 24 07:36:40 PM PST 24
Finished Jan 24 07:56:13 PM PST 24
Peak memory 201232 kb
Host smart-df037e52-8367-4e70-a9b4-9e9d42d6bb98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482413181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1482413181
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4039767876
Short name T127
Test name
Test status
Simulation time 327796705588 ps
CPU time 719.87 seconds
Started Jan 24 07:22:10 PM PST 24
Finished Jan 24 07:34:11 PM PST 24
Peak memory 201068 kb
Host smart-51a8fd09-388b-4cff-8f4d-6bfdd3967b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039767876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4039767876
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2944642220
Short name T596
Test name
Test status
Simulation time 321963723228 ps
CPU time 171.75 seconds
Started Jan 24 07:22:10 PM PST 24
Finished Jan 24 07:25:03 PM PST 24
Peak memory 201276 kb
Host smart-9bc45e5e-5c6e-44e2-940b-985952c4b2e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944642220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2944642220
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1469637660
Short name T235
Test name
Test status
Simulation time 484829819685 ps
CPU time 308.92 seconds
Started Jan 24 07:22:13 PM PST 24
Finished Jan 24 07:27:23 PM PST 24
Peak memory 201152 kb
Host smart-223f8aee-2437-4c71-82b9-defb7188d9b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469637660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1469637660
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.735723272
Short name T822
Test name
Test status
Simulation time 494025486033 ps
CPU time 294.56 seconds
Started Jan 24 07:22:16 PM PST 24
Finished Jan 24 07:27:11 PM PST 24
Peak memory 201232 kb
Host smart-948606a0-c5c0-4d6b-a92e-4d4a2623e193
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735723272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.735723272
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2425123560
Short name T205
Test name
Test status
Simulation time 64208710081 ps
CPU time 232.1 seconds
Started Jan 24 11:33:11 PM PST 24
Finished Jan 24 11:37:10 PM PST 24
Peak memory 201516 kb
Host smart-2d0497a4-fe0e-48e1-ba11-6c7c772f0b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425123560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2425123560
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1406337131
Short name T507
Test name
Test status
Simulation time 24283186152 ps
CPU time 14.18 seconds
Started Jan 24 07:22:30 PM PST 24
Finished Jan 24 07:22:45 PM PST 24
Peak memory 200916 kb
Host smart-3a4dec8a-3555-4da2-ae72-0d559ee9fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406337131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1406337131
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3387993641
Short name T801
Test name
Test status
Simulation time 2649744848 ps
CPU time 2 seconds
Started Jan 24 07:22:25 PM PST 24
Finished Jan 24 07:22:28 PM PST 24
Peak memory 201032 kb
Host smart-3e7ad32b-d171-4b7e-94e3-e935391805c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387993641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3387993641
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.176749940
Short name T782
Test name
Test status
Simulation time 6191001227 ps
CPU time 4.55 seconds
Started Jan 24 07:22:02 PM PST 24
Finished Jan 24 07:22:07 PM PST 24
Peak memory 200968 kb
Host smart-667a2555-35dd-43c2-8d2c-f79330656968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176749940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.176749940
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1318178082
Short name T310
Test name
Test status
Simulation time 336519630301 ps
CPU time 416.37 seconds
Started Jan 24 07:22:37 PM PST 24
Finished Jan 24 07:29:34 PM PST 24
Peak memory 201172 kb
Host smart-274da0af-a356-4653-9b83-c5b00add812c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318178082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1318178082
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3345762367
Short name T636
Test name
Test status
Simulation time 37507087235 ps
CPU time 24.29 seconds
Started Jan 24 07:59:47 PM PST 24
Finished Jan 24 08:00:14 PM PST 24
Peak memory 209464 kb
Host smart-cc104c75-2240-43d3-969f-a3a2d4e38b85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345762367 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3345762367
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2358898970
Short name T653
Test name
Test status
Simulation time 416338860 ps
CPU time 1.07 seconds
Started Jan 24 07:23:15 PM PST 24
Finished Jan 24 07:23:17 PM PST 24
Peak memory 200892 kb
Host smart-71d6a63d-b5ed-42dd-88c5-17cf3dcef1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358898970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2358898970
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2077876293
Short name T842
Test name
Test status
Simulation time 168889651104 ps
CPU time 380.41 seconds
Started Jan 24 07:22:58 PM PST 24
Finished Jan 24 07:29:20 PM PST 24
Peak memory 201228 kb
Host smart-afda5e29-ca10-49e0-9c97-9c5505e9ddcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077876293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2077876293
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3041425367
Short name T157
Test name
Test status
Simulation time 495381968424 ps
CPU time 235.03 seconds
Started Jan 24 07:22:58 PM PST 24
Finished Jan 24 07:26:54 PM PST 24
Peak memory 201260 kb
Host smart-5c8303c5-69ac-467a-972d-a65108e9de8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041425367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3041425367
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.266326745
Short name T549
Test name
Test status
Simulation time 325301434536 ps
CPU time 105.11 seconds
Started Jan 24 07:22:47 PM PST 24
Finished Jan 24 07:24:37 PM PST 24
Peak memory 201184 kb
Host smart-90bb7ff8-ee4d-45d1-a11b-e23f7ca89d6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=266326745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.266326745
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1562324976
Short name T628
Test name
Test status
Simulation time 168186043074 ps
CPU time 99.87 seconds
Started Jan 24 07:22:45 PM PST 24
Finished Jan 24 07:24:29 PM PST 24
Peak memory 201168 kb
Host smart-6496fcfc-a567-4d13-9a8d-df0ae005c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562324976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1562324976
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4003866205
Short name T803
Test name
Test status
Simulation time 164154730572 ps
CPU time 91.43 seconds
Started Jan 24 07:22:46 PM PST 24
Finished Jan 24 07:24:21 PM PST 24
Peak memory 201236 kb
Host smart-a20f99ec-75ca-4324-8a98-9f2d98694993
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003866205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4003866205
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2916410182
Short name T296
Test name
Test status
Simulation time 331837667217 ps
CPU time 208.42 seconds
Started Jan 24 07:22:59 PM PST 24
Finished Jan 24 07:26:29 PM PST 24
Peak memory 201228 kb
Host smart-c9615c4a-284d-4495-b5fa-fbb16e436f90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916410182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2916410182
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2487254962
Short name T544
Test name
Test status
Simulation time 328696697581 ps
CPU time 67.65 seconds
Started Jan 24 07:22:59 PM PST 24
Finished Jan 24 07:24:08 PM PST 24
Peak memory 201228 kb
Host smart-442eb986-6d19-4bed-a777-c79c8339c581
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487254962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2487254962
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.572272708
Short name T548
Test name
Test status
Simulation time 109795568575 ps
CPU time 530.83 seconds
Started Jan 24 07:23:08 PM PST 24
Finished Jan 24 07:32:01 PM PST 24
Peak memory 201504 kb
Host smart-f1dc13e7-a828-4183-8806-14517b2fbcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572272708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.572272708
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.726391933
Short name T463
Test name
Test status
Simulation time 40092268051 ps
CPU time 22.5 seconds
Started Jan 24 11:20:16 PM PST 24
Finished Jan 24 11:20:39 PM PST 24
Peak memory 201052 kb
Host smart-84126f0b-5f38-4863-9ba1-af65c109306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726391933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.726391933
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2392773436
Short name T791
Test name
Test status
Simulation time 4111601849 ps
CPU time 5.71 seconds
Started Jan 24 07:23:00 PM PST 24
Finished Jan 24 07:23:07 PM PST 24
Peak memory 201036 kb
Host smart-92251893-ff76-450a-b6a7-058fc74d9936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392773436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2392773436
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2101935713
Short name T165
Test name
Test status
Simulation time 5592435420 ps
CPU time 14.1 seconds
Started Jan 24 07:22:36 PM PST 24
Finished Jan 24 07:22:52 PM PST 24
Peak memory 200964 kb
Host smart-2231e5ef-1253-4e23-a7fa-bf00ba3d7efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101935713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2101935713
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3479964803
Short name T279
Test name
Test status
Simulation time 289064034222 ps
CPU time 555.17 seconds
Started Jan 24 07:23:14 PM PST 24
Finished Jan 24 07:32:30 PM PST 24
Peak memory 209812 kb
Host smart-d98cf780-7ca5-444f-aeea-e4ba75c722e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479964803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3479964803
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.35798247
Short name T724
Test name
Test status
Simulation time 24463896175 ps
CPU time 56.2 seconds
Started Jan 24 07:23:12 PM PST 24
Finished Jan 24 07:24:10 PM PST 24
Peak memory 209472 kb
Host smart-861190bf-94eb-4005-a6b9-f092f1ca6e37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35798247 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.35798247
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4107402644
Short name T644
Test name
Test status
Simulation time 466970607 ps
CPU time 1.03 seconds
Started Jan 24 07:23:41 PM PST 24
Finished Jan 24 07:23:43 PM PST 24
Peak memory 200824 kb
Host smart-415e3dc7-b68e-48ec-a035-eefe540a4744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107402644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4107402644
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2336689290
Short name T658
Test name
Test status
Simulation time 166448223252 ps
CPU time 82.3 seconds
Started Jan 24 07:23:25 PM PST 24
Finished Jan 24 07:24:50 PM PST 24
Peak memory 201220 kb
Host smart-69229d4d-7875-4094-a817-eb2deaad42bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336689290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2336689290
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3725874825
Short name T334
Test name
Test status
Simulation time 494991475228 ps
CPU time 609.87 seconds
Started Jan 24 07:23:22 PM PST 24
Finished Jan 24 07:33:34 PM PST 24
Peak memory 201172 kb
Host smart-3981112a-907c-4e52-97ce-bb8970d6847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725874825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3725874825
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1362910116
Short name T736
Test name
Test status
Simulation time 489987496689 ps
CPU time 329.56 seconds
Started Jan 24 07:30:54 PM PST 24
Finished Jan 24 07:36:25 PM PST 24
Peak memory 201236 kb
Host smart-6bfa66cc-bd29-4a03-8e46-07d0d1ce3315
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362910116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1362910116
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3987724788
Short name T97
Test name
Test status
Simulation time 323956815518 ps
CPU time 729.62 seconds
Started Jan 24 07:23:11 PM PST 24
Finished Jan 24 07:35:23 PM PST 24
Peak memory 201244 kb
Host smart-d47520ea-5adc-4937-886c-f99963bfa55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987724788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3987724788
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1308790659
Short name T15
Test name
Test status
Simulation time 170799112385 ps
CPU time 97.4 seconds
Started Jan 24 07:23:22 PM PST 24
Finished Jan 24 07:25:02 PM PST 24
Peak memory 201216 kb
Host smart-d0d14a55-770c-49fc-852f-bf45875670fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308790659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1308790659
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3492089746
Short name T373
Test name
Test status
Simulation time 139486547958 ps
CPU time 697.93 seconds
Started Jan 24 07:23:33 PM PST 24
Finished Jan 24 07:35:12 PM PST 24
Peak memory 201504 kb
Host smart-706a3650-1f5a-4c9f-8982-76d66db23241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492089746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3492089746
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1625088171
Short name T806
Test name
Test status
Simulation time 22625085451 ps
CPU time 55.38 seconds
Started Jan 24 07:23:27 PM PST 24
Finished Jan 24 07:24:24 PM PST 24
Peak memory 201052 kb
Host smart-c96048ec-389c-4550-bc3b-a2b1e076cba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625088171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1625088171
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.587871686
Short name T817
Test name
Test status
Simulation time 3878923402 ps
CPU time 3.03 seconds
Started Jan 24 07:23:27 PM PST 24
Finished Jan 24 07:23:31 PM PST 24
Peak memory 201012 kb
Host smart-9ea51663-6113-4c17-a053-8eddc99f2f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587871686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.587871686
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1674935978
Short name T513
Test name
Test status
Simulation time 5995712638 ps
CPU time 4.48 seconds
Started Jan 24 07:23:10 PM PST 24
Finished Jan 24 07:23:17 PM PST 24
Peak memory 201004 kb
Host smart-3f43579b-e55f-4996-8465-33828b24a2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674935978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1674935978
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3932368690
Short name T743
Test name
Test status
Simulation time 199239159962 ps
CPU time 125.48 seconds
Started Jan 24 07:23:43 PM PST 24
Finished Jan 24 07:25:49 PM PST 24
Peak memory 201180 kb
Host smart-c5214e7b-bf86-45a0-b6a1-f98528289a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932368690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3932368690
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.439347767
Short name T238
Test name
Test status
Simulation time 120195698600 ps
CPU time 159.38 seconds
Started Jan 24 08:47:10 PM PST 24
Finished Jan 24 08:49:50 PM PST 24
Peak memory 209896 kb
Host smart-fa03b4bc-2180-416b-b501-b8ac66ad6ac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439347767 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.439347767
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.864099568
Short name T845
Test name
Test status
Simulation time 313213301 ps
CPU time 1.37 seconds
Started Jan 24 08:01:26 PM PST 24
Finished Jan 24 08:01:28 PM PST 24
Peak memory 200932 kb
Host smart-3a28aa1b-8378-4d77-b740-6de8e6b1e2a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864099568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.864099568
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2949986614
Short name T645
Test name
Test status
Simulation time 330003794594 ps
CPU time 102.21 seconds
Started Jan 24 08:36:10 PM PST 24
Finished Jan 24 08:37:54 PM PST 24
Peak memory 201204 kb
Host smart-53566ada-0e06-4ef4-8e75-70064d7cbc5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949986614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2949986614
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2733292102
Short name T321
Test name
Test status
Simulation time 328004672252 ps
CPU time 732.45 seconds
Started Jan 24 07:24:04 PM PST 24
Finished Jan 24 07:36:17 PM PST 24
Peak memory 201152 kb
Host smart-5c0c5a0f-740e-46b7-b901-bc442ad3cbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733292102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2733292102
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3814902
Short name T107
Test name
Test status
Simulation time 328791703151 ps
CPU time 256.76 seconds
Started Jan 24 07:23:55 PM PST 24
Finished Jan 24 07:28:12 PM PST 24
Peak memory 201132 kb
Host smart-71f05c12-6d26-4adb-bd02-1cb83f82c2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3814902
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.687028609
Short name T444
Test name
Test status
Simulation time 320464495837 ps
CPU time 398.99 seconds
Started Jan 24 07:23:55 PM PST 24
Finished Jan 24 07:30:35 PM PST 24
Peak memory 201116 kb
Host smart-bee7ce2a-8440-443d-a19e-cdc305c582d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=687028609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.687028609
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1834245828
Short name T539
Test name
Test status
Simulation time 169439919121 ps
CPU time 56.79 seconds
Started Jan 24 07:23:41 PM PST 24
Finished Jan 24 07:24:38 PM PST 24
Peak memory 201172 kb
Host smart-6fefa227-b20a-440e-a3d9-b0d0b9861d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834245828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1834245828
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3129475306
Short name T584
Test name
Test status
Simulation time 164514642683 ps
CPU time 96.94 seconds
Started Jan 24 07:23:42 PM PST 24
Finished Jan 24 07:25:20 PM PST 24
Peak memory 201240 kb
Host smart-74d237b6-35b8-4c20-bae7-18d8326bf7da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129475306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3129475306
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1225766346
Short name T333
Test name
Test status
Simulation time 160342766566 ps
CPU time 184.74 seconds
Started Jan 24 07:24:00 PM PST 24
Finished Jan 24 07:27:06 PM PST 24
Peak memory 201232 kb
Host smart-177cd705-6bda-4d02-83f3-f60c62c9d2c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225766346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1225766346
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2138212403
Short name T614
Test name
Test status
Simulation time 490061361233 ps
CPU time 1019.79 seconds
Started Jan 24 07:23:57 PM PST 24
Finished Jan 24 07:40:57 PM PST 24
Peak memory 201240 kb
Host smart-9a17a93b-fa29-4add-9922-e6beedbd1932
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138212403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2138212403
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.316700747
Short name T190
Test name
Test status
Simulation time 71554060767 ps
CPU time 231.21 seconds
Started Jan 24 07:24:07 PM PST 24
Finished Jan 24 07:27:58 PM PST 24
Peak memory 201500 kb
Host smart-8fa26d99-eefa-410e-b08f-19ed3f751e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316700747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.316700747
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1993816317
Short name T149
Test name
Test status
Simulation time 25744382811 ps
CPU time 30.81 seconds
Started Jan 24 08:33:21 PM PST 24
Finished Jan 24 08:33:52 PM PST 24
Peak memory 201060 kb
Host smart-6ca115e3-fd0f-4301-a0bd-e25f3abee4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993816317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1993816317
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4098733744
Short name T813
Test name
Test status
Simulation time 3642989817 ps
CPU time 9.56 seconds
Started Jan 24 08:55:14 PM PST 24
Finished Jan 24 08:55:24 PM PST 24
Peak memory 201056 kb
Host smart-d20a2686-78f8-4ab7-8566-032ada710cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098733744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4098733744
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.883177580
Short name T693
Test name
Test status
Simulation time 5933594887 ps
CPU time 15.67 seconds
Started Jan 24 08:17:18 PM PST 24
Finished Jan 24 08:17:34 PM PST 24
Peak memory 201004 kb
Host smart-af0dfc27-9349-4608-8b9f-2252a741daae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883177580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.883177580
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.663143617
Short name T512
Test name
Test status
Simulation time 82623725789 ps
CPU time 254.27 seconds
Started Jan 24 07:24:10 PM PST 24
Finished Jan 24 07:28:25 PM PST 24
Peak memory 201488 kb
Host smart-d8a05d73-f07d-4c56-bda1-9f692ef9eb76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663143617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
663143617
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1409147216
Short name T686
Test name
Test status
Simulation time 450989681630 ps
CPU time 391.46 seconds
Started Jan 24 07:24:09 PM PST 24
Finished Jan 24 07:30:41 PM PST 24
Peak memory 209820 kb
Host smart-7664082a-cadb-41f8-bddc-3ea2640c5b8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409147216 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1409147216
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.76340719
Short name T552
Test name
Test status
Simulation time 332190134 ps
CPU time 1.39 seconds
Started Jan 24 07:24:48 PM PST 24
Finished Jan 24 07:24:50 PM PST 24
Peak memory 200928 kb
Host smart-5a3a20df-9f14-4ae5-9fc0-00d1670aaafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76340719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.76340719
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1505584595
Short name T304
Test name
Test status
Simulation time 506972117826 ps
CPU time 595.34 seconds
Started Jan 24 07:24:25 PM PST 24
Finished Jan 24 07:34:21 PM PST 24
Peak memory 201276 kb
Host smart-29b4bdfc-a36d-44ef-ab46-96dac732c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505584595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1505584595
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2029604328
Short name T159
Test name
Test status
Simulation time 328996044650 ps
CPU time 123.48 seconds
Started Jan 24 07:24:17 PM PST 24
Finished Jan 24 07:26:21 PM PST 24
Peak memory 201124 kb
Host smart-5a25b22e-6385-46ba-a8bf-4d55d3364872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029604328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2029604328
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2346606783
Short name T627
Test name
Test status
Simulation time 490755460747 ps
CPU time 1095.44 seconds
Started Jan 24 07:24:18 PM PST 24
Finished Jan 24 07:42:34 PM PST 24
Peak memory 201056 kb
Host smart-836aa6a5-8cb3-439f-b9d9-a5a1aab0d87c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346606783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2346606783
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2611232347
Short name T211
Test name
Test status
Simulation time 166801770903 ps
CPU time 366.1 seconds
Started Jan 24 07:24:09 PM PST 24
Finished Jan 24 07:30:16 PM PST 24
Peak memory 201180 kb
Host smart-e50ff819-84ed-4cb8-8a1a-88ca4c579227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611232347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2611232347
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2633157656
Short name T495
Test name
Test status
Simulation time 328514408333 ps
CPU time 214.57 seconds
Started Jan 24 07:24:16 PM PST 24
Finished Jan 24 07:27:51 PM PST 24
Peak memory 201256 kb
Host smart-388670af-0688-495d-9b9a-18e61651f112
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633157656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2633157656
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2208545371
Short name T796
Test name
Test status
Simulation time 170899627662 ps
CPU time 372.88 seconds
Started Jan 24 07:24:16 PM PST 24
Finished Jan 24 07:30:30 PM PST 24
Peak memory 201148 kb
Host smart-153b9ec9-335d-4169-9bec-32eec135331f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208545371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2208545371
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.801717341
Short name T61
Test name
Test status
Simulation time 336627332614 ps
CPU time 759.96 seconds
Started Jan 24 07:24:15 PM PST 24
Finished Jan 24 07:36:56 PM PST 24
Peak memory 201292 kb
Host smart-7abea231-5b46-497e-ad6b-2020d3811f12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801717341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.801717341
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1807057368
Short name T370
Test name
Test status
Simulation time 71875638908 ps
CPU time 350.72 seconds
Started Jan 24 07:24:39 PM PST 24
Finished Jan 24 07:30:31 PM PST 24
Peak memory 201484 kb
Host smart-a109f9b8-1fdd-494e-9a1f-89e1283ee027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807057368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1807057368
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2723301615
Short name T152
Test name
Test status
Simulation time 26167530221 ps
CPU time 58.96 seconds
Started Jan 24 07:24:32 PM PST 24
Finished Jan 24 07:25:32 PM PST 24
Peak memory 200960 kb
Host smart-d372b2fa-68aa-4190-90b8-5bcd76e33791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723301615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2723301615
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3425283627
Short name T445
Test name
Test status
Simulation time 4984120232 ps
CPU time 6.71 seconds
Started Jan 24 07:24:22 PM PST 24
Finished Jan 24 07:24:30 PM PST 24
Peak memory 200996 kb
Host smart-0e78040c-26e4-4cee-8c52-a72b111b4d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425283627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3425283627
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.847551525
Short name T438
Test name
Test status
Simulation time 5809849670 ps
CPU time 4.25 seconds
Started Jan 24 07:24:07 PM PST 24
Finished Jan 24 07:24:12 PM PST 24
Peak memory 200888 kb
Host smart-743f9392-924a-41af-93d1-affcdacd79bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847551525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.847551525
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2678563262
Short name T759
Test name
Test status
Simulation time 650599416791 ps
CPU time 1120.13 seconds
Started Jan 24 07:24:51 PM PST 24
Finished Jan 24 07:43:33 PM PST 24
Peak memory 201616 kb
Host smart-7307f40e-5c46-40a5-9d2e-df3242ecf5ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678563262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2678563262
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3335494622
Short name T740
Test name
Test status
Simulation time 20823111958 ps
CPU time 50.49 seconds
Started Jan 24 07:24:39 PM PST 24
Finished Jan 24 07:25:30 PM PST 24
Peak memory 201012 kb
Host smart-da5c3d31-1dc6-444c-94a0-c8918a8e3fee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335494622 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3335494622
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.555625219
Short name T837
Test name
Test status
Simulation time 366332116 ps
CPU time 1.47 seconds
Started Jan 24 07:25:15 PM PST 24
Finished Jan 24 07:25:17 PM PST 24
Peak memory 200864 kb
Host smart-9aa6995a-c5cc-4409-a7ab-39b95b27f65c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555625219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.555625219
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.854395992
Short name T851
Test name
Test status
Simulation time 167204993613 ps
CPU time 92.95 seconds
Started Jan 24 07:34:03 PM PST 24
Finished Jan 24 07:35:38 PM PST 24
Peak memory 201252 kb
Host smart-96464b18-5a58-45c2-bae9-fbeb896c3d5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854395992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.854395992
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3470403152
Short name T339
Test name
Test status
Simulation time 165118854842 ps
CPU time 93.18 seconds
Started Jan 24 07:24:48 PM PST 24
Finished Jan 24 07:26:22 PM PST 24
Peak memory 201176 kb
Host smart-fb49d5be-3cbc-4c1a-8b15-49373918b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470403152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3470403152
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1767561521
Short name T662
Test name
Test status
Simulation time 170695091953 ps
CPU time 116.89 seconds
Started Jan 24 07:35:53 PM PST 24
Finished Jan 24 07:37:52 PM PST 24
Peak memory 201180 kb
Host smart-e1b81ff9-082e-45b1-b347-54222fff9879
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767561521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1767561521
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.297973604
Short name T581
Test name
Test status
Simulation time 494212386685 ps
CPU time 1143.24 seconds
Started Jan 24 07:24:47 PM PST 24
Finished Jan 24 07:43:51 PM PST 24
Peak memory 201256 kb
Host smart-10ccf77a-2104-4846-b8a7-5f622def5c7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=297973604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.297973604
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.4248279267
Short name T250
Test name
Test status
Simulation time 167088548347 ps
CPU time 182.43 seconds
Started Jan 24 07:24:48 PM PST 24
Finished Jan 24 07:27:52 PM PST 24
Peak memory 201176 kb
Host smart-eef81fba-fc18-43cb-936f-aa9d743d2f35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248279267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.4248279267
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.528811412
Short name T452
Test name
Test status
Simulation time 168575767029 ps
CPU time 388.73 seconds
Started Jan 24 07:24:51 PM PST 24
Finished Jan 24 07:31:21 PM PST 24
Peak memory 201164 kb
Host smart-7a7d7d3a-2064-452c-9688-d5a995b2c21f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528811412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.528811412
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.270778649
Short name T115
Test name
Test status
Simulation time 67364003732 ps
CPU time 363.21 seconds
Started Jan 24 07:25:03 PM PST 24
Finished Jan 24 07:31:07 PM PST 24
Peak memory 201488 kb
Host smart-967cd893-ccc4-4889-bbaf-71ce144a1b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270778649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.270778649
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2208988012
Short name T710
Test name
Test status
Simulation time 42475549181 ps
CPU time 24.55 seconds
Started Jan 24 07:24:55 PM PST 24
Finished Jan 24 07:25:20 PM PST 24
Peak memory 200936 kb
Host smart-6919712a-4c87-4758-b8c5-6b6e9e91938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208988012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2208988012
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3115971485
Short name T426
Test name
Test status
Simulation time 2688251216 ps
CPU time 6.62 seconds
Started Jan 24 07:24:57 PM PST 24
Finished Jan 24 07:25:05 PM PST 24
Peak memory 200956 kb
Host smart-8f6afc83-8bd4-4993-bcfa-548033677709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115971485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3115971485
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3086135956
Short name T720
Test name
Test status
Simulation time 5691092755 ps
CPU time 3.75 seconds
Started Jan 24 07:24:49 PM PST 24
Finished Jan 24 07:24:54 PM PST 24
Peak memory 200996 kb
Host smart-917d1800-b30f-49d8-84cb-eb15d900cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086135956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3086135956
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.4265160914
Short name T248
Test name
Test status
Simulation time 294802219992 ps
CPU time 818.15 seconds
Started Jan 24 07:25:04 PM PST 24
Finished Jan 24 07:38:43 PM PST 24
Peak memory 211700 kb
Host smart-c73b59d0-d175-4120-9417-844f53e53a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265160914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.4265160914
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3589806239
Short name T344
Test name
Test status
Simulation time 59407423562 ps
CPU time 129.93 seconds
Started Jan 24 08:06:30 PM PST 24
Finished Jan 24 08:08:42 PM PST 24
Peak memory 209524 kb
Host smart-5f044a6e-2493-476e-9a2d-b17c8689c476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589806239 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3589806239
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.826999730
Short name T551
Test name
Test status
Simulation time 526652376 ps
CPU time 1.69 seconds
Started Jan 24 07:08:30 PM PST 24
Finished Jan 24 07:08:34 PM PST 24
Peak memory 200924 kb
Host smart-aa6397fd-2421-4f50-a2df-d845273ec208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826999730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.826999730
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1921797056
Short name T285
Test name
Test status
Simulation time 498424162299 ps
CPU time 571.93 seconds
Started Jan 24 07:08:19 PM PST 24
Finished Jan 24 07:17:53 PM PST 24
Peak memory 201180 kb
Host smart-3015cb80-4695-4aa2-afcc-c2e7971fa864
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921797056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1921797056
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.407370152
Short name T758
Test name
Test status
Simulation time 489950949783 ps
CPU time 1146.86 seconds
Started Jan 24 07:08:15 PM PST 24
Finished Jan 24 07:27:23 PM PST 24
Peak memory 201192 kb
Host smart-d7b95854-a2f2-423e-8c66-7f2faa7e0bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407370152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.407370152
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2909028820
Short name T700
Test name
Test status
Simulation time 321879117130 ps
CPU time 397.52 seconds
Started Jan 24 07:08:09 PM PST 24
Finished Jan 24 07:14:49 PM PST 24
Peak memory 201228 kb
Host smart-35b1d51b-e2c1-41c8-8968-0006f531de5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909028820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2909028820
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1525885975
Short name T582
Test name
Test status
Simulation time 328884150861 ps
CPU time 815.98 seconds
Started Jan 24 09:31:54 PM PST 24
Finished Jan 24 09:45:30 PM PST 24
Peak memory 201200 kb
Host smart-b28ab516-b71f-40df-9b1c-f0af7f08aee4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525885975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1525885975
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1598910499
Short name T751
Test name
Test status
Simulation time 323021515239 ps
CPU time 470.36 seconds
Started Jan 24 07:08:05 PM PST 24
Finished Jan 24 07:15:57 PM PST 24
Peak memory 201148 kb
Host smart-5a78b591-a0a4-413f-8969-51f1eba332b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598910499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1598910499
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.4066611629
Short name T752
Test name
Test status
Simulation time 330751156440 ps
CPU time 180.47 seconds
Started Jan 24 07:08:08 PM PST 24
Finished Jan 24 07:11:09 PM PST 24
Peak memory 201252 kb
Host smart-50a79be3-ad5a-4bd4-8c51-eee1718b9e48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066611629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.4066611629
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4097634480
Short name T135
Test name
Test status
Simulation time 486159682911 ps
CPU time 281.35 seconds
Started Jan 24 07:08:14 PM PST 24
Finished Jan 24 07:12:56 PM PST 24
Peak memory 201204 kb
Host smart-9e74f522-7dad-491c-9518-0b2854d747a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097634480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4097634480
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3962766855
Short name T520
Test name
Test status
Simulation time 171942620614 ps
CPU time 197.82 seconds
Started Jan 24 07:08:12 PM PST 24
Finished Jan 24 07:11:31 PM PST 24
Peak memory 201168 kb
Host smart-3846f4b0-3cae-4e1c-968d-106c9b6964a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962766855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3962766855
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3642182714
Short name T204
Test name
Test status
Simulation time 111449848455 ps
CPU time 370.33 seconds
Started Jan 24 08:18:39 PM PST 24
Finished Jan 24 08:24:52 PM PST 24
Peak memory 201624 kb
Host smart-72a12440-90b7-4dd0-9aaa-7a313aa4b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642182714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3642182714
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4166997179
Short name T178
Test name
Test status
Simulation time 33423206450 ps
CPU time 76.17 seconds
Started Jan 24 09:55:02 PM PST 24
Finished Jan 24 09:56:20 PM PST 24
Peak memory 201024 kb
Host smart-e180db59-d3e5-4c22-94cf-f90c3ee8ead8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166997179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4166997179
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.4281931454
Short name T756
Test name
Test status
Simulation time 3950396044 ps
CPU time 2.96 seconds
Started Jan 24 07:08:13 PM PST 24
Finished Jan 24 07:08:17 PM PST 24
Peak memory 200916 kb
Host smart-c84f36d3-5f1b-44e1-bcd0-41ffd299bfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281931454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.4281931454
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2428415880
Short name T52
Test name
Test status
Simulation time 8363913468 ps
CPU time 3.88 seconds
Started Jan 24 07:08:34 PM PST 24
Finished Jan 24 07:08:42 PM PST 24
Peak memory 217512 kb
Host smart-307f947d-7dd5-4f9b-bc76-7914f6d2f69d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428415880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2428415880
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.231332120
Short name T439
Test name
Test status
Simulation time 5967279309 ps
CPU time 4.32 seconds
Started Jan 24 07:08:07 PM PST 24
Finished Jan 24 07:08:13 PM PST 24
Peak memory 201044 kb
Host smart-a35f61ca-219d-49c3-85ac-6ace85886469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231332120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.231332120
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4243584087
Short name T151
Test name
Test status
Simulation time 168754975070 ps
CPU time 116.92 seconds
Started Jan 24 07:08:16 PM PST 24
Finished Jan 24 07:10:14 PM PST 24
Peak memory 201152 kb
Host smart-d019837f-97ff-47d3-9e12-06cd77e34b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243584087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4243584087
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.412555664
Short name T163
Test name
Test status
Simulation time 23744156548 ps
CPU time 29.06 seconds
Started Jan 24 07:28:24 PM PST 24
Finished Jan 24 07:28:56 PM PST 24
Peak memory 209508 kb
Host smart-3fb4f430-cbbd-4019-b3b3-634c6ef04ce1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412555664 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.412555664
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2658091721
Short name T477
Test name
Test status
Simulation time 326202060 ps
CPU time 1.35 seconds
Started Jan 24 07:53:09 PM PST 24
Finished Jan 24 07:53:12 PM PST 24
Peak memory 200904 kb
Host smart-2a644461-cf35-4182-b1a2-f1ce0edb0a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658091721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2658091721
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1003180204
Short name T131
Test name
Test status
Simulation time 334949037638 ps
CPU time 201.07 seconds
Started Jan 24 07:37:40 PM PST 24
Finished Jan 24 07:41:02 PM PST 24
Peak memory 201304 kb
Host smart-693eea36-3272-45ea-90b1-f3fabe425c32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003180204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1003180204
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3776010791
Short name T269
Test name
Test status
Simulation time 331837263321 ps
CPU time 239.05 seconds
Started Jan 24 09:18:58 PM PST 24
Finished Jan 24 09:22:59 PM PST 24
Peak memory 201244 kb
Host smart-475981e8-35c3-41c1-a3f7-c3987ff2e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776010791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3776010791
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2091037016
Short name T709
Test name
Test status
Simulation time 326591447436 ps
CPU time 708.62 seconds
Started Jan 24 09:35:22 PM PST 24
Finished Jan 24 09:47:13 PM PST 24
Peak memory 201180 kb
Host smart-3317254e-8fc2-4799-8d04-28714bf5620c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091037016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2091037016
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1904261666
Short name T132
Test name
Test status
Simulation time 493254668575 ps
CPU time 172.9 seconds
Started Jan 24 07:46:54 PM PST 24
Finished Jan 24 07:49:48 PM PST 24
Peak memory 201232 kb
Host smart-6cb7a2df-a9d8-4010-948e-0f77291c35ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904261666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1904261666
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4034473886
Short name T10
Test name
Test status
Simulation time 329288339552 ps
CPU time 196.45 seconds
Started Jan 24 07:25:16 PM PST 24
Finished Jan 24 07:28:33 PM PST 24
Peak memory 201224 kb
Host smart-6fb05bdf-8deb-4475-b0ec-7afd33e0c072
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034473886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4034473886
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3400057615
Short name T570
Test name
Test status
Simulation time 502349169217 ps
CPU time 1129.72 seconds
Started Jan 24 07:25:21 PM PST 24
Finished Jan 24 07:44:17 PM PST 24
Peak memory 201092 kb
Host smart-21b5b8cb-cc5f-4e2a-bdd7-9fca3a7e9dca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400057615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3400057615
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2764681391
Short name T448
Test name
Test status
Simulation time 324956215221 ps
CPU time 172.23 seconds
Started Jan 24 07:25:20 PM PST 24
Finished Jan 24 07:28:18 PM PST 24
Peak memory 201056 kb
Host smart-080c8ffd-ab99-4312-bbba-683f06fca88b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764681391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2764681391
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.99511524
Short name T366
Test name
Test status
Simulation time 80915369890 ps
CPU time 343.59 seconds
Started Jan 24 07:25:29 PM PST 24
Finished Jan 24 07:31:16 PM PST 24
Peak memory 201456 kb
Host smart-6060bb3a-e806-42a9-b262-39a4151d4f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99511524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.99511524
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.976275649
Short name T647
Test name
Test status
Simulation time 36160686289 ps
CPU time 77.12 seconds
Started Jan 24 07:25:27 PM PST 24
Finished Jan 24 07:26:47 PM PST 24
Peak memory 201004 kb
Host smart-12f70f2e-05f4-44db-9361-5661d7012271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976275649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.976275649
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2629808909
Short name T834
Test name
Test status
Simulation time 2973752609 ps
CPU time 8.72 seconds
Started Jan 24 07:25:22 PM PST 24
Finished Jan 24 07:25:37 PM PST 24
Peak memory 201048 kb
Host smart-798d46a0-5359-47f0-b31c-92514777c974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629808909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2629808909
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2967108098
Short name T665
Test name
Test status
Simulation time 6015542797 ps
CPU time 14.36 seconds
Started Jan 24 09:20:08 PM PST 24
Finished Jan 24 09:20:23 PM PST 24
Peak memory 201016 kb
Host smart-f77cc0e9-a150-427f-988d-04c44575539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967108098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2967108098
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2090172715
Short name T338
Test name
Test status
Simulation time 326328175935 ps
CPU time 688.36 seconds
Started Jan 24 07:25:30 PM PST 24
Finished Jan 24 07:37:01 PM PST 24
Peak memory 201168 kb
Host smart-a73431ab-acd9-4094-85be-18600e0ff91e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090172715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2090172715
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.510523332
Short name T239
Test name
Test status
Simulation time 19491775312 ps
CPU time 44.78 seconds
Started Jan 24 07:25:29 PM PST 24
Finished Jan 24 07:26:18 PM PST 24
Peak memory 209888 kb
Host smart-f738423b-dea3-42c0-a6b7-cd8dabd8d021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510523332 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.510523332
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1562695006
Short name T434
Test name
Test status
Simulation time 500079731 ps
CPU time 0.76 seconds
Started Jan 24 08:07:21 PM PST 24
Finished Jan 24 08:07:25 PM PST 24
Peak memory 200912 kb
Host smart-4c7ee02d-96f2-4ed1-8a5b-2b65065e680e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562695006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1562695006
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3320495299
Short name T332
Test name
Test status
Simulation time 497015128926 ps
CPU time 209.72 seconds
Started Jan 24 07:25:48 PM PST 24
Finished Jan 24 07:29:19 PM PST 24
Peak memory 201240 kb
Host smart-5439dd31-6396-4f63-a4ab-baabd219524c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320495299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3320495299
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2292456823
Short name T258
Test name
Test status
Simulation time 335244762067 ps
CPU time 406.14 seconds
Started Jan 24 09:13:05 PM PST 24
Finished Jan 24 09:19:58 PM PST 24
Peak memory 201248 kb
Host smart-6a732105-0f64-4ffa-be7d-055f0e60b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292456823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2292456823
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2134960555
Short name T146
Test name
Test status
Simulation time 331880777896 ps
CPU time 209.05 seconds
Started Jan 24 07:25:37 PM PST 24
Finished Jan 24 07:29:08 PM PST 24
Peak memory 201188 kb
Host smart-041297eb-0d85-4975-9b11-e2f0aa5bf09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134960555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2134960555
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2977085851
Short name T744
Test name
Test status
Simulation time 161655289118 ps
CPU time 91.45 seconds
Started Jan 24 07:25:37 PM PST 24
Finished Jan 24 07:27:11 PM PST 24
Peak memory 201164 kb
Host smart-8024784b-8765-4c20-bf58-885a4622582f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977085851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2977085851
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.297352886
Short name T798
Test name
Test status
Simulation time 158796055575 ps
CPU time 97.75 seconds
Started Jan 24 07:25:40 PM PST 24
Finished Jan 24 07:27:23 PM PST 24
Peak memory 201252 kb
Host smart-7f146b94-202d-4378-a78b-26d501dd004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297352886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.297352886
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3452900369
Short name T681
Test name
Test status
Simulation time 325548306682 ps
CPU time 736.86 seconds
Started Jan 24 07:25:37 PM PST 24
Finished Jan 24 07:37:56 PM PST 24
Peak memory 201136 kb
Host smart-6c8c2908-62a1-4806-a8a9-e13bfd43ed47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452900369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3452900369
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2331638138
Short name T234
Test name
Test status
Simulation time 327626227380 ps
CPU time 731.69 seconds
Started Jan 24 07:25:54 PM PST 24
Finished Jan 24 07:38:08 PM PST 24
Peak memory 201252 kb
Host smart-ea75396f-33b5-44da-bcb6-912994087c81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331638138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2331638138
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.263833467
Short name T675
Test name
Test status
Simulation time 155787638360 ps
CPU time 39.44 seconds
Started Jan 24 07:25:50 PM PST 24
Finished Jan 24 07:26:31 PM PST 24
Peak memory 201116 kb
Host smart-c79f6895-6afb-4826-8ad9-0522b6adb272
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263833467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.263833467
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3231786885
Short name T713
Test name
Test status
Simulation time 65314712293 ps
CPU time 221.91 seconds
Started Jan 24 07:25:59 PM PST 24
Finished Jan 24 07:29:44 PM PST 24
Peak memory 201536 kb
Host smart-0d0cd4ec-1288-4372-9e1f-02dbc0d71dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231786885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3231786885
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2534222987
Short name T572
Test name
Test status
Simulation time 47543872195 ps
CPU time 6.58 seconds
Started Jan 24 07:38:00 PM PST 24
Finished Jan 24 07:38:08 PM PST 24
Peak memory 201036 kb
Host smart-14b13439-01f2-4a4e-9749-26108a4036f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534222987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2534222987
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2220098505
Short name T762
Test name
Test status
Simulation time 5192108823 ps
CPU time 14.06 seconds
Started Jan 24 07:34:06 PM PST 24
Finished Jan 24 07:34:21 PM PST 24
Peak memory 201056 kb
Host smart-e8db1d60-2d91-41cd-b2b7-233239c4c61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220098505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2220098505
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2940625380
Short name T433
Test name
Test status
Simulation time 5972800682 ps
CPU time 14.98 seconds
Started Jan 24 07:25:39 PM PST 24
Finished Jan 24 07:26:00 PM PST 24
Peak memory 201048 kb
Host smart-55b1d190-bad4-46e3-a31f-550fcf782649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940625380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2940625380
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.990513610
Short name T449
Test name
Test status
Simulation time 302264079 ps
CPU time 0.82 seconds
Started Jan 24 08:02:53 PM PST 24
Finished Jan 24 08:02:57 PM PST 24
Peak memory 200912 kb
Host smart-c9f12d5e-a62c-416c-ac5f-42f90db83f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990513610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.990513610
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2118589136
Short name T223
Test name
Test status
Simulation time 211367651817 ps
CPU time 461.72 seconds
Started Jan 24 10:22:33 PM PST 24
Finished Jan 24 10:30:16 PM PST 24
Peak memory 201216 kb
Host smart-c558f5a4-8cb4-43d1-adf7-ea6843086dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118589136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2118589136
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1864422294
Short name T340
Test name
Test status
Simulation time 329130356867 ps
CPU time 361.93 seconds
Started Jan 24 07:26:06 PM PST 24
Finished Jan 24 07:32:09 PM PST 24
Peak memory 201156 kb
Host smart-8d231117-1026-47be-9289-41ce9bac19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864422294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1864422294
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.229952488
Short name T694
Test name
Test status
Simulation time 326777937502 ps
CPU time 202.22 seconds
Started Jan 24 07:26:06 PM PST 24
Finished Jan 24 07:29:30 PM PST 24
Peak memory 201160 kb
Host smart-97119e40-aabb-4502-82f1-011928385a26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=229952488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.229952488
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1271159941
Short name T102
Test name
Test status
Simulation time 488154285241 ps
CPU time 194.62 seconds
Started Jan 24 07:54:53 PM PST 24
Finished Jan 24 07:58:14 PM PST 24
Peak memory 201216 kb
Host smart-bc5c33aa-7b19-417a-be53-ea1497875ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271159941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1271159941
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3169843179
Short name T847
Test name
Test status
Simulation time 334558069090 ps
CPU time 88.11 seconds
Started Jan 24 07:55:10 PM PST 24
Finished Jan 24 07:56:39 PM PST 24
Peak memory 201244 kb
Host smart-e2e2e4a7-ba6b-4bf7-8c82-17cb49b6d93e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169843179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3169843179
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.163585897
Short name T106
Test name
Test status
Simulation time 168136149087 ps
CPU time 380.18 seconds
Started Jan 24 08:22:36 PM PST 24
Finished Jan 24 08:29:04 PM PST 24
Peak memory 201260 kb
Host smart-a859dd67-0a81-42f0-a711-0c07c88e59ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163585897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.163585897
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2160391834
Short name T442
Test name
Test status
Simulation time 162313226243 ps
CPU time 44.4 seconds
Started Jan 24 07:40:33 PM PST 24
Finished Jan 24 07:41:19 PM PST 24
Peak memory 201284 kb
Host smart-d04ffaa2-405e-4a97-8020-0837de0e4057
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160391834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2160391834
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2344389702
Short name T631
Test name
Test status
Simulation time 108483831976 ps
CPU time 395.7 seconds
Started Jan 24 08:51:57 PM PST 24
Finished Jan 24 08:58:39 PM PST 24
Peak memory 201492 kb
Host smart-a2f1c0f8-a4a6-43b1-b31c-824589c76d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344389702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2344389702
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2884070790
Short name T779
Test name
Test status
Simulation time 35499007541 ps
CPU time 78.69 seconds
Started Jan 24 07:26:12 PM PST 24
Finished Jan 24 07:27:32 PM PST 24
Peak memory 200960 kb
Host smart-f7d61f26-99ea-4091-9623-19842ff446a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884070790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2884070790
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1370509254
Short name T607
Test name
Test status
Simulation time 4644304711 ps
CPU time 5.88 seconds
Started Jan 24 10:31:53 PM PST 24
Finished Jan 24 10:32:02 PM PST 24
Peak memory 201040 kb
Host smart-05c4b886-18c9-4f62-928b-77674763c149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370509254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1370509254
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3347855159
Short name T12
Test name
Test status
Simulation time 5711996495 ps
CPU time 7.86 seconds
Started Jan 24 07:25:56 PM PST 24
Finished Jan 24 07:26:10 PM PST 24
Peak memory 200912 kb
Host smart-2a70348d-1fde-4299-8db5-cc498850659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347855159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3347855159
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3510772511
Short name T85
Test name
Test status
Simulation time 97309951880 ps
CPU time 242.7 seconds
Started Jan 24 07:26:22 PM PST 24
Finished Jan 24 07:30:26 PM PST 24
Peak memory 201608 kb
Host smart-7a37f77b-5526-41af-a74a-de17704c4cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510772511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3510772511
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1225097966
Short name T118
Test name
Test status
Simulation time 286864417970 ps
CPU time 168.77 seconds
Started Jan 24 07:53:53 PM PST 24
Finished Jan 24 07:56:48 PM PST 24
Peak memory 209552 kb
Host smart-ced58990-6931-4d52-bd59-058efa1ddbbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225097966 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1225097966
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4076567002
Short name T162
Test name
Test status
Simulation time 339688111 ps
CPU time 1.36 seconds
Started Jan 24 07:27:09 PM PST 24
Finished Jan 24 07:27:11 PM PST 24
Peak memory 200896 kb
Host smart-b1dde252-8004-4e97-bd08-5473b8dc8f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076567002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4076567002
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2483788068
Short name T514
Test name
Test status
Simulation time 324115207592 ps
CPU time 437.52 seconds
Started Jan 24 07:26:42 PM PST 24
Finished Jan 24 07:34:00 PM PST 24
Peak memory 201264 kb
Host smart-d456797f-1b13-4b5b-85ac-a8d4922ae0cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483788068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2483788068
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2597276110
Short name T330
Test name
Test status
Simulation time 170274328364 ps
CPU time 366.72 seconds
Started Jan 24 07:26:41 PM PST 24
Finished Jan 24 07:32:49 PM PST 24
Peak memory 201244 kb
Host smart-34bd5cf8-785b-43eb-aa33-82eda43e0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597276110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2597276110
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3945840650
Short name T243
Test name
Test status
Simulation time 488154635706 ps
CPU time 1158.34 seconds
Started Jan 24 07:26:34 PM PST 24
Finished Jan 24 07:45:54 PM PST 24
Peak memory 201244 kb
Host smart-e2baad74-090e-4fe5-b897-0e33b1b8800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945840650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3945840650
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1214480969
Short name T510
Test name
Test status
Simulation time 493274810014 ps
CPU time 1115.1 seconds
Started Jan 24 07:26:34 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 201068 kb
Host smart-3017bd87-e486-46e4-b051-22262aa52696
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214480969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1214480969
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1300122815
Short name T587
Test name
Test status
Simulation time 163432672459 ps
CPU time 52.73 seconds
Started Jan 24 07:26:35 PM PST 24
Finished Jan 24 07:27:30 PM PST 24
Peak memory 201244 kb
Host smart-8cde41f7-7e40-40b9-aa40-b2af636ac1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300122815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1300122815
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2707427234
Short name T502
Test name
Test status
Simulation time 328401789689 ps
CPU time 390.57 seconds
Started Jan 24 07:26:35 PM PST 24
Finished Jan 24 07:33:06 PM PST 24
Peak memory 201220 kb
Host smart-9fd9ce41-949e-40c5-9482-83cae0ef273b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707427234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2707427234
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.923045716
Short name T615
Test name
Test status
Simulation time 159878651819 ps
CPU time 102.32 seconds
Started Jan 24 07:26:37 PM PST 24
Finished Jan 24 07:28:20 PM PST 24
Peak memory 201256 kb
Host smart-fc28ae49-9595-4f67-b6c7-b0782a4b4689
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923045716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.923045716
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3586367808
Short name T820
Test name
Test status
Simulation time 329997268347 ps
CPU time 749.36 seconds
Started Jan 24 07:26:35 PM PST 24
Finished Jan 24 07:39:06 PM PST 24
Peak memory 201272 kb
Host smart-6012410d-6c22-4327-924b-248e8acf6efd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586367808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3586367808
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2260662185
Short name T668
Test name
Test status
Simulation time 97270739783 ps
CPU time 325.37 seconds
Started Jan 24 07:31:56 PM PST 24
Finished Jan 24 07:37:29 PM PST 24
Peak memory 201520 kb
Host smart-aa9185ab-9e80-4778-8753-aecce5fe2b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260662185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2260662185
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3917419917
Short name T482
Test name
Test status
Simulation time 32486851810 ps
CPU time 75.51 seconds
Started Jan 24 07:26:51 PM PST 24
Finished Jan 24 07:28:07 PM PST 24
Peak memory 201000 kb
Host smart-ce959423-a265-4ece-be11-086cfd6ceb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917419917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3917419917
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3020586391
Short name T455
Test name
Test status
Simulation time 2886729123 ps
CPU time 6.85 seconds
Started Jan 24 07:26:53 PM PST 24
Finished Jan 24 07:27:01 PM PST 24
Peak memory 201048 kb
Host smart-ab2800e1-e5f8-4003-bf91-9a79fa29aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020586391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3020586391
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1006146655
Short name T425
Test name
Test status
Simulation time 5579655015 ps
CPU time 3.12 seconds
Started Jan 24 08:47:16 PM PST 24
Finished Jan 24 08:47:21 PM PST 24
Peak memory 201064 kb
Host smart-f721cd6a-601d-46d8-8b3e-dc2739c44116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006146655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1006146655
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3948674197
Short name T325
Test name
Test status
Simulation time 235873500750 ps
CPU time 153.4 seconds
Started Jan 24 07:26:50 PM PST 24
Finished Jan 24 07:29:25 PM PST 24
Peak memory 209920 kb
Host smart-6c468f7f-0af1-4b8e-ac91-e68cecb923de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948674197 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3948674197
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2795975596
Short name T787
Test name
Test status
Simulation time 300917378 ps
CPU time 0.93 seconds
Started Jan 24 09:29:33 PM PST 24
Finished Jan 24 09:29:35 PM PST 24
Peak memory 200932 kb
Host smart-5322cbf1-a0e2-488a-ad96-88c292cdf213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795975596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2795975596
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3044790510
Short name T351
Test name
Test status
Simulation time 495041215378 ps
CPU time 382.12 seconds
Started Jan 24 07:27:15 PM PST 24
Finished Jan 24 07:33:37 PM PST 24
Peak memory 201164 kb
Host smart-fddd2362-16d6-4e90-a7a8-df1f1df95f09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044790510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3044790510
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3810023995
Short name T624
Test name
Test status
Simulation time 161117379693 ps
CPU time 93.67 seconds
Started Jan 24 07:27:18 PM PST 24
Finished Jan 24 07:28:52 PM PST 24
Peak memory 201204 kb
Host smart-e5f728b8-7425-4248-b8b6-3054b54951cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810023995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3810023995
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2722381222
Short name T353
Test name
Test status
Simulation time 162974959979 ps
CPU time 393.92 seconds
Started Jan 24 08:08:14 PM PST 24
Finished Jan 24 08:14:50 PM PST 24
Peak memory 201212 kb
Host smart-37d64a85-13b0-4a6e-b28c-a00c93a2dea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722381222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2722381222
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.4034115976
Short name T142
Test name
Test status
Simulation time 162988129879 ps
CPU time 99.14 seconds
Started Jan 24 07:27:10 PM PST 24
Finished Jan 24 07:28:50 PM PST 24
Peak memory 201068 kb
Host smart-d5f1c7bb-7490-4133-9447-dce6801184eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034115976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.4034115976
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2271927600
Short name T256
Test name
Test status
Simulation time 489416467419 ps
CPU time 1130.97 seconds
Started Jan 24 08:47:40 PM PST 24
Finished Jan 24 09:06:32 PM PST 24
Peak memory 201288 kb
Host smart-7c8d35d5-8573-4df4-a7bc-63c74003437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271927600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2271927600
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1784267137
Short name T515
Test name
Test status
Simulation time 496989542554 ps
CPU time 290.34 seconds
Started Jan 24 07:27:08 PM PST 24
Finished Jan 24 07:31:59 PM PST 24
Peak memory 201140 kb
Host smart-6234a724-fd23-4d21-9d9b-eb361e637295
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784267137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1784267137
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3637785297
Short name T517
Test name
Test status
Simulation time 334687081240 ps
CPU time 216.79 seconds
Started Jan 24 07:27:15 PM PST 24
Finished Jan 24 07:30:52 PM PST 24
Peak memory 201164 kb
Host smart-0b148ed6-02d7-4df3-9e4d-8e91d8970dab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637785297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3637785297
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1894454208
Short name T777
Test name
Test status
Simulation time 74704101227 ps
CPU time 257.52 seconds
Started Jan 24 07:27:24 PM PST 24
Finished Jan 24 07:31:42 PM PST 24
Peak memory 201520 kb
Host smart-903aa478-469a-4219-9ca1-6d0315328196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894454208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1894454208
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2678159733
Short name T841
Test name
Test status
Simulation time 43549060291 ps
CPU time 31.43 seconds
Started Jan 24 07:27:23 PM PST 24
Finished Jan 24 07:27:55 PM PST 24
Peak memory 201024 kb
Host smart-fa540acc-fade-4f06-be51-2b1d20c5c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678159733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2678159733
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2865681219
Short name T719
Test name
Test status
Simulation time 3452280926 ps
CPU time 4.63 seconds
Started Jan 24 07:27:15 PM PST 24
Finished Jan 24 07:27:21 PM PST 24
Peak memory 201036 kb
Host smart-0167b217-536f-4444-8d4c-41f58b63db9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865681219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2865681219
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3070469220
Short name T739
Test name
Test status
Simulation time 6133997863 ps
CPU time 7.39 seconds
Started Jan 24 08:06:27 PM PST 24
Finished Jan 24 08:06:38 PM PST 24
Peak memory 200996 kb
Host smart-407e9766-c533-4d7b-a102-abd5740d8bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070469220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3070469220
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.757103330
Short name T365
Test name
Test status
Simulation time 299332601101 ps
CPU time 522.1 seconds
Started Jan 24 07:27:34 PM PST 24
Finished Jan 24 07:36:16 PM PST 24
Peak memory 217900 kb
Host smart-2f0085b2-fcd9-4906-908f-371f8cd62660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757103330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
757103330
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3032073111
Short name T617
Test name
Test status
Simulation time 441174996 ps
CPU time 1.7 seconds
Started Jan 24 07:27:45 PM PST 24
Finished Jan 24 07:27:47 PM PST 24
Peak memory 200888 kb
Host smart-d7932acc-0d3c-4782-b470-e1fd8ee27417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032073111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3032073111
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.563254557
Short name T60
Test name
Test status
Simulation time 168662995904 ps
CPU time 66.42 seconds
Started Jan 24 08:43:29 PM PST 24
Finished Jan 24 08:45:00 PM PST 24
Peak memory 201280 kb
Host smart-1a641511-2d48-48aa-bbe8-c0836ad3ae93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563254557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.563254557
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1852155880
Short name T236
Test name
Test status
Simulation time 496156032318 ps
CPU time 152.34 seconds
Started Jan 24 07:27:37 PM PST 24
Finished Jan 24 07:30:10 PM PST 24
Peak memory 201176 kb
Host smart-b76686f0-2b12-4690-8815-79af139ff5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852155880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1852155880
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2820562601
Short name T650
Test name
Test status
Simulation time 162457680861 ps
CPU time 204.97 seconds
Started Jan 24 07:27:34 PM PST 24
Finished Jan 24 07:31:00 PM PST 24
Peak memory 201132 kb
Host smart-a5092dc7-4832-4f12-8484-489c001de2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820562601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2820562601
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3798409885
Short name T677
Test name
Test status
Simulation time 490300008845 ps
CPU time 586.29 seconds
Started Jan 24 07:27:32 PM PST 24
Finished Jan 24 07:37:19 PM PST 24
Peak memory 201068 kb
Host smart-c57504e2-a887-4ccc-8b96-adef58867791
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798409885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3798409885
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3902995537
Short name T793
Test name
Test status
Simulation time 162320031918 ps
CPU time 123.06 seconds
Started Jan 24 09:04:05 PM PST 24
Finished Jan 24 09:06:20 PM PST 24
Peak memory 201208 kb
Host smart-f165346d-d607-4551-94fc-fe011787ee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902995537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3902995537
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2408797846
Short name T589
Test name
Test status
Simulation time 495933723175 ps
CPU time 79.17 seconds
Started Jan 24 08:02:10 PM PST 24
Finished Jan 24 08:03:32 PM PST 24
Peak memory 201220 kb
Host smart-e203caa6-d95a-4b2f-87e7-008a80af660e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408797846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2408797846
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.654710785
Short name T705
Test name
Test status
Simulation time 331059903077 ps
CPU time 133.56 seconds
Started Jan 24 08:10:58 PM PST 24
Finished Jan 24 08:13:12 PM PST 24
Peak memory 201268 kb
Host smart-d3c414fa-d2f6-40e3-9fcd-4298cfbc45ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654710785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.654710785
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1668862986
Short name T508
Test name
Test status
Simulation time 489343343101 ps
CPU time 290.98 seconds
Started Jan 24 07:50:40 PM PST 24
Finished Jan 24 07:55:32 PM PST 24
Peak memory 201252 kb
Host smart-484ca668-7301-4c31-9b5a-99bf855b4e2b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668862986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1668862986
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.391162278
Short name T670
Test name
Test status
Simulation time 97654087946 ps
CPU time 388.92 seconds
Started Jan 24 08:56:51 PM PST 24
Finished Jan 24 09:03:22 PM PST 24
Peak memory 201552 kb
Host smart-c4d5d3d3-5385-43ab-9efb-7c602f858dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391162278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.391162278
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2722614986
Short name T630
Test name
Test status
Simulation time 24595998326 ps
CPU time 58.6 seconds
Started Jan 24 07:48:00 PM PST 24
Finished Jan 24 07:49:03 PM PST 24
Peak memory 201036 kb
Host smart-ca7db5bf-494c-4b35-8e42-889d3b0d30dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722614986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2722614986
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3759724276
Short name T620
Test name
Test status
Simulation time 2945125218 ps
CPU time 7.28 seconds
Started Jan 24 07:27:45 PM PST 24
Finished Jan 24 07:27:53 PM PST 24
Peak memory 200916 kb
Host smart-b7afd220-d491-4b6e-863a-61f8d35366b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759724276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3759724276
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.251494605
Short name T655
Test name
Test status
Simulation time 5760575088 ps
CPU time 7.51 seconds
Started Jan 24 07:27:33 PM PST 24
Finished Jan 24 07:27:41 PM PST 24
Peak memory 200980 kb
Host smart-6ec9c39e-ee6f-4b6c-9119-d3353ff48ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251494605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.251494605
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1150318120
Short name T784
Test name
Test status
Simulation time 370841971851 ps
CPU time 220.71 seconds
Started Jan 24 07:27:46 PM PST 24
Finished Jan 24 07:31:28 PM PST 24
Peak memory 201132 kb
Host smart-96b31d97-288b-430c-94b4-d3f983795c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150318120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1150318120
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2416587272
Short name T318
Test name
Test status
Simulation time 524986936296 ps
CPU time 516.32 seconds
Started Jan 24 07:27:47 PM PST 24
Finished Jan 24 07:36:24 PM PST 24
Peak memory 209932 kb
Host smart-44bda47c-678a-4952-9ed1-d7314824ce18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416587272 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2416587272
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3171870519
Short name T46
Test name
Test status
Simulation time 303989634 ps
CPU time 0.93 seconds
Started Jan 24 07:28:10 PM PST 24
Finished Jan 24 07:28:12 PM PST 24
Peak memory 200816 kb
Host smart-44f62006-776d-4138-8a61-40b8dec1eee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171870519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3171870519
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2358826832
Short name T284
Test name
Test status
Simulation time 163112130760 ps
CPU time 194.9 seconds
Started Jan 24 07:28:01 PM PST 24
Finished Jan 24 07:31:18 PM PST 24
Peak memory 201180 kb
Host smart-3aab1ac6-8a50-4d46-905e-07d7ec2b95ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358826832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2358826832
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.237923126
Short name T117
Test name
Test status
Simulation time 161684404072 ps
CPU time 70.69 seconds
Started Jan 24 07:28:03 PM PST 24
Finished Jan 24 07:29:15 PM PST 24
Peak memory 201176 kb
Host smart-f1955bec-d9f7-4da0-9a57-fa22589b9930
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=237923126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.237923126
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2364888626
Short name T289
Test name
Test status
Simulation time 329599725581 ps
CPU time 791.52 seconds
Started Jan 24 07:27:54 PM PST 24
Finished Jan 24 07:41:06 PM PST 24
Peak memory 201232 kb
Host smart-dd20d0d1-123f-4533-b40b-f2dfdabb7403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364888626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2364888626
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2800570133
Short name T764
Test name
Test status
Simulation time 330071251137 ps
CPU time 733.95 seconds
Started Jan 24 07:27:53 PM PST 24
Finished Jan 24 07:40:08 PM PST 24
Peak memory 201224 kb
Host smart-b47c8108-d1ea-4633-a1ba-f93b43ca3dd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800570133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2800570133
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.340890105
Short name T98
Test name
Test status
Simulation time 330397483798 ps
CPU time 201.24 seconds
Started Jan 24 07:28:02 PM PST 24
Finished Jan 24 07:31:24 PM PST 24
Peak memory 201240 kb
Host smart-8659446a-a74c-4fb5-b085-2ea0bc8d040b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340890105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.340890105
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1874479480
Short name T270
Test name
Test status
Simulation time 167630764595 ps
CPU time 365.9 seconds
Started Jan 24 07:28:02 PM PST 24
Finished Jan 24 07:34:09 PM PST 24
Peak memory 201168 kb
Host smart-9366d4bd-1c60-4cde-9eae-f606431a49e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874479480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1874479480
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2229258668
Short name T619
Test name
Test status
Simulation time 67801765302 ps
CPU time 328.51 seconds
Started Jan 24 07:28:02 PM PST 24
Finished Jan 24 07:33:31 PM PST 24
Peak memory 201464 kb
Host smart-9fa4f300-5386-4afc-914b-dd1838b26d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229258668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2229258668
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.639905965
Short name T850
Test name
Test status
Simulation time 37413618043 ps
CPU time 19 seconds
Started Jan 24 07:28:02 PM PST 24
Finished Jan 24 07:28:22 PM PST 24
Peak memory 201020 kb
Host smart-38489019-380e-4e1d-bfcf-bf1b9e79c419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639905965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.639905965
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1686377847
Short name T11
Test name
Test status
Simulation time 4178643731 ps
CPU time 3.53 seconds
Started Jan 24 07:28:08 PM PST 24
Finished Jan 24 07:28:12 PM PST 24
Peak memory 200956 kb
Host smart-588c58b2-1bfc-43d3-ad1a-73675758847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686377847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1686377847
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3074150651
Short name T488
Test name
Test status
Simulation time 5735445208 ps
CPU time 7.65 seconds
Started Jan 24 07:27:54 PM PST 24
Finished Jan 24 07:28:02 PM PST 24
Peak memory 200976 kb
Host smart-b51c2947-76d1-4188-ab7d-b2557c818272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074150651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3074150651
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2739871565
Short name T217
Test name
Test status
Simulation time 258379981952 ps
CPU time 296.19 seconds
Started Jan 24 07:28:08 PM PST 24
Finished Jan 24 07:33:05 PM PST 24
Peak memory 201152 kb
Host smart-1ff6d148-9d6b-48ad-a666-fce0dcac9a91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739871565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2739871565
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3243729875
Short name T750
Test name
Test status
Simulation time 51220112129 ps
CPU time 106.78 seconds
Started Jan 24 07:28:03 PM PST 24
Finished Jan 24 07:29:50 PM PST 24
Peak memory 201316 kb
Host smart-23339d41-af98-41f9-b8aa-e3f723a567f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243729875 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3243729875
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3796046996
Short name T728
Test name
Test status
Simulation time 436838548 ps
CPU time 0.88 seconds
Started Jan 24 08:43:49 PM PST 24
Finished Jan 24 08:44:02 PM PST 24
Peak memory 200928 kb
Host smart-70e2b830-3eda-4178-9ecd-686ff84a9e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796046996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3796046996
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.708134200
Short name T343
Test name
Test status
Simulation time 162644932751 ps
CPU time 185.02 seconds
Started Jan 24 07:28:17 PM PST 24
Finished Jan 24 07:31:23 PM PST 24
Peak memory 201164 kb
Host smart-65556ce3-bfb9-438d-b575-56bb8b0210c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708134200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.708134200
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2982120565
Short name T253
Test name
Test status
Simulation time 322683209451 ps
CPU time 181.61 seconds
Started Jan 24 07:28:18 PM PST 24
Finished Jan 24 07:31:20 PM PST 24
Peak memory 201176 kb
Host smart-5de169be-d866-44a4-adeb-11af99939ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982120565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2982120565
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3955034496
Short name T437
Test name
Test status
Simulation time 162261161882 ps
CPU time 181.24 seconds
Started Jan 24 07:28:10 PM PST 24
Finished Jan 24 07:31:13 PM PST 24
Peak memory 201100 kb
Host smart-40cf01a5-bc00-4338-9b43-3cc32f754366
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955034496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3955034496
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3293632400
Short name T839
Test name
Test status
Simulation time 328951774017 ps
CPU time 377.83 seconds
Started Jan 24 07:28:10 PM PST 24
Finished Jan 24 07:34:29 PM PST 24
Peak memory 201092 kb
Host smart-716edb36-ed09-4aa1-a9d2-c18ed04d7fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293632400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3293632400
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4215263836
Short name T788
Test name
Test status
Simulation time 166339250547 ps
CPU time 22.82 seconds
Started Jan 24 07:28:07 PM PST 24
Finished Jan 24 07:28:30 PM PST 24
Peak memory 201252 kb
Host smart-88172346-084a-4dc8-85a7-32eba7bca415
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215263836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4215263836
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.162604511
Short name T347
Test name
Test status
Simulation time 181905001413 ps
CPU time 106.98 seconds
Started Jan 24 07:28:18 PM PST 24
Finished Jan 24 07:30:06 PM PST 24
Peak memory 201208 kb
Host smart-5a3fa6f5-fcb4-4d03-bef5-150aaa21786d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162604511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.162604511
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1003709741
Short name T456
Test name
Test status
Simulation time 163307007351 ps
CPU time 375.3 seconds
Started Jan 24 07:42:04 PM PST 24
Finished Jan 24 07:48:26 PM PST 24
Peak memory 201160 kb
Host smart-738ceec7-d7ad-4163-b03a-78979d31bc78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003709741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1003709741
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.418156082
Short name T721
Test name
Test status
Simulation time 81529320929 ps
CPU time 326.66 seconds
Started Jan 24 07:28:28 PM PST 24
Finished Jan 24 07:34:02 PM PST 24
Peak memory 201500 kb
Host smart-95c3bb52-7e30-4f20-9f22-7455fbcf6d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418156082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.418156082
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3401707843
Short name T816
Test name
Test status
Simulation time 23891466935 ps
CPU time 14.46 seconds
Started Jan 24 07:43:54 PM PST 24
Finished Jan 24 07:44:09 PM PST 24
Peak memory 201040 kb
Host smart-83f2b70d-f66f-47e8-bf6f-2a0d2f742397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401707843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3401707843
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1280165044
Short name T429
Test name
Test status
Simulation time 4774556016 ps
CPU time 3.04 seconds
Started Jan 24 08:09:40 PM PST 24
Finished Jan 24 08:09:45 PM PST 24
Peak memory 201056 kb
Host smart-43e060da-60a2-43ea-83c5-43f95457eeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280165044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1280165044
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.757264458
Short name T741
Test name
Test status
Simulation time 5854846084 ps
CPU time 4.57 seconds
Started Jan 24 07:28:09 PM PST 24
Finished Jan 24 07:28:15 PM PST 24
Peak memory 201044 kb
Host smart-01f02e8f-864f-4149-a073-83c21084ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757264458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.757264458
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1157949695
Short name T197
Test name
Test status
Simulation time 467826655295 ps
CPU time 625.14 seconds
Started Jan 24 07:28:28 PM PST 24
Finished Jan 24 07:39:01 PM PST 24
Peak memory 209728 kb
Host smart-72a72cd7-5d64-4acb-95f3-26a68d3b46d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157949695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1157949695
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.317202209
Short name T809
Test name
Test status
Simulation time 327314291 ps
CPU time 0.81 seconds
Started Jan 24 07:28:57 PM PST 24
Finished Jan 24 07:29:05 PM PST 24
Peak memory 200800 kb
Host smart-22d80b72-fdeb-466b-b047-2c9c7ca9cb2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317202209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.317202209
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.996290755
Short name T53
Test name
Test status
Simulation time 333581469970 ps
CPU time 466.1 seconds
Started Jan 24 07:28:41 PM PST 24
Finished Jan 24 07:36:28 PM PST 24
Peak memory 201240 kb
Host smart-48f58ee1-9266-4ef8-a6aa-30a8ac249dd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996290755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.996290755
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2232212524
Short name T108
Test name
Test status
Simulation time 526801146072 ps
CPU time 326.39 seconds
Started Jan 24 07:28:41 PM PST 24
Finished Jan 24 07:34:08 PM PST 24
Peak memory 201260 kb
Host smart-aa7b394c-84e7-428a-ba91-58ec2e0ea104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232212524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2232212524
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.957365341
Short name T109
Test name
Test status
Simulation time 474739488481 ps
CPU time 298.17 seconds
Started Jan 24 07:28:38 PM PST 24
Finished Jan 24 07:33:39 PM PST 24
Peak memory 201232 kb
Host smart-59c99d77-3831-413b-8078-4bd1cca6fa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957365341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.957365341
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.45175790
Short name T546
Test name
Test status
Simulation time 492717660976 ps
CPU time 591.77 seconds
Started Jan 24 07:28:38 PM PST 24
Finished Jan 24 07:38:33 PM PST 24
Peak memory 201096 kb
Host smart-b32000df-7a5d-47ec-a2a2-ad90ac5adbf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=45175790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt
_fixed.45175790
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2542457733
Short name T280
Test name
Test status
Simulation time 333947968614 ps
CPU time 134.73 seconds
Started Jan 24 07:28:29 PM PST 24
Finished Jan 24 07:30:52 PM PST 24
Peak memory 201236 kb
Host smart-3cf44745-6697-4753-b6a0-4222ee1dcefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542457733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2542457733
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2223601274
Short name T431
Test name
Test status
Simulation time 498257887648 ps
CPU time 1206.18 seconds
Started Jan 24 07:28:37 PM PST 24
Finished Jan 24 07:48:46 PM PST 24
Peak memory 201072 kb
Host smart-cc80ba1c-b2f6-4e52-aca7-166517bc146e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223601274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2223601274
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3766759921
Short name T626
Test name
Test status
Simulation time 492010774017 ps
CPU time 1039.92 seconds
Started Jan 24 07:28:41 PM PST 24
Finished Jan 24 07:46:03 PM PST 24
Peak memory 201224 kb
Host smart-24f55777-2d63-4af1-b164-f01ff65c0d19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766759921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3766759921
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2216893672
Short name T855
Test name
Test status
Simulation time 94860506562 ps
CPU time 355.37 seconds
Started Jan 24 07:28:47 PM PST 24
Finished Jan 24 07:34:49 PM PST 24
Peak memory 201500 kb
Host smart-13ae7213-bf6d-4ea0-b739-9ddebbbddf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216893672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2216893672
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3342521281
Short name T702
Test name
Test status
Simulation time 29205229390 ps
CPU time 4.88 seconds
Started Jan 24 07:28:47 PM PST 24
Finished Jan 24 07:28:58 PM PST 24
Peak memory 201052 kb
Host smart-ac0c625b-b7c6-49b3-93c1-5842bb9a1df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342521281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3342521281
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2877265607
Short name T529
Test name
Test status
Simulation time 4177194331 ps
CPU time 10.2 seconds
Started Jan 24 07:28:42 PM PST 24
Finished Jan 24 07:28:53 PM PST 24
Peak memory 201000 kb
Host smart-9c40bb38-c301-4a05-afd2-ae5b8dcf446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877265607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2877265607
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2302201183
Short name T848
Test name
Test status
Simulation time 5816581632 ps
CPU time 16.15 seconds
Started Jan 24 08:09:00 PM PST 24
Finished Jan 24 08:09:17 PM PST 24
Peak memory 201048 kb
Host smart-1a7c52ee-4964-4e59-895b-9c12cc263619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302201183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2302201183
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3270369550
Short name T299
Test name
Test status
Simulation time 330210949525 ps
CPU time 175.19 seconds
Started Jan 24 07:28:54 PM PST 24
Finished Jan 24 07:31:57 PM PST 24
Peak memory 201204 kb
Host smart-e52409c9-c163-4419-b791-b4fc186c9d75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270369550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3270369550
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3371840765
Short name T350
Test name
Test status
Simulation time 68429659842 ps
CPU time 130.17 seconds
Started Jan 24 07:28:56 PM PST 24
Finished Jan 24 07:31:14 PM PST 24
Peak memory 209892 kb
Host smart-b1354b64-5a50-4b89-8c15-b0b76b181155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371840765 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3371840765
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1500103876
Short name T805
Test name
Test status
Simulation time 590526000 ps
CPU time 0.71 seconds
Started Jan 24 07:29:17 PM PST 24
Finished Jan 24 07:29:18 PM PST 24
Peak memory 200916 kb
Host smart-a4eda973-29a2-44b7-9252-8bff5b9cb60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500103876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1500103876
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.564873186
Short name T156
Test name
Test status
Simulation time 324689492244 ps
CPU time 121.47 seconds
Started Jan 24 07:29:12 PM PST 24
Finished Jan 24 07:31:15 PM PST 24
Peak memory 201176 kb
Host smart-ad24192d-c0cc-4e03-9cc1-7332a30beea8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564873186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.564873186
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2803175884
Short name T684
Test name
Test status
Simulation time 326514736348 ps
CPU time 841.35 seconds
Started Jan 24 07:29:09 PM PST 24
Finished Jan 24 07:43:13 PM PST 24
Peak memory 201124 kb
Host smart-ce95856e-228f-4669-97d5-df9fa4704c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803175884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2803175884
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1814399855
Short name T316
Test name
Test status
Simulation time 494743119893 ps
CPU time 1159.91 seconds
Started Jan 24 07:29:05 PM PST 24
Finished Jan 24 07:48:29 PM PST 24
Peak memory 201128 kb
Host smart-58c00a05-84f7-490a-b27a-393d1c5d7cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814399855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1814399855
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1675387499
Short name T692
Test name
Test status
Simulation time 487673863182 ps
CPU time 541.43 seconds
Started Jan 24 07:29:02 PM PST 24
Finished Jan 24 07:38:07 PM PST 24
Peak memory 201180 kb
Host smart-52633967-3ad9-44f3-a356-a73be6c41ca4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675387499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1675387499
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3142154950
Short name T733
Test name
Test status
Simulation time 166997721453 ps
CPU time 357.75 seconds
Started Jan 24 07:29:03 PM PST 24
Finished Jan 24 07:35:06 PM PST 24
Peak memory 201196 kb
Host smart-64f2e6f9-65dc-4754-8058-aa7d33336eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142154950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3142154950
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2180834229
Short name T528
Test name
Test status
Simulation time 331833023309 ps
CPU time 101.53 seconds
Started Jan 24 07:29:06 PM PST 24
Finished Jan 24 07:30:51 PM PST 24
Peak memory 201072 kb
Host smart-395c3bc5-edd5-4654-8904-322a64ebf9c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180834229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2180834229
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1675743893
Short name T659
Test name
Test status
Simulation time 345241231327 ps
CPU time 198.1 seconds
Started Jan 24 07:29:07 PM PST 24
Finished Jan 24 07:32:28 PM PST 24
Peak memory 201204 kb
Host smart-5c52c7c2-f920-4308-8e8e-a58e69d064c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675743893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1675743893
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3987968122
Short name T746
Test name
Test status
Simulation time 161682425077 ps
CPU time 395.85 seconds
Started Jan 24 07:29:10 PM PST 24
Finished Jan 24 07:35:48 PM PST 24
Peak memory 201224 kb
Host smart-8866ccd0-507b-494a-959d-1e8201b7e9cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987968122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3987968122
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2458074225
Short name T141
Test name
Test status
Simulation time 89743205725 ps
CPU time 285.32 seconds
Started Jan 24 07:29:10 PM PST 24
Finished Jan 24 07:33:57 PM PST 24
Peak memory 201488 kb
Host smart-0b6a7c20-3120-4f2c-96b1-e2ff18333f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458074225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2458074225
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3336818836
Short name T54
Test name
Test status
Simulation time 31157569822 ps
CPU time 30.96 seconds
Started Jan 24 09:33:45 PM PST 24
Finished Jan 24 09:34:16 PM PST 24
Peak memory 201056 kb
Host smart-2b34bdf0-a28d-4d36-adaf-682099e16c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336818836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3336818836
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2018274380
Short name T525
Test name
Test status
Simulation time 3216793912 ps
CPU time 2.76 seconds
Started Jan 24 07:29:16 PM PST 24
Finished Jan 24 07:29:20 PM PST 24
Peak memory 201020 kb
Host smart-5f52d146-2127-45c2-af6b-d6df9a7d76c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018274380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2018274380
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1425392037
Short name T489
Test name
Test status
Simulation time 6143064858 ps
CPU time 14.84 seconds
Started Jan 24 07:28:55 PM PST 24
Finished Jan 24 07:29:18 PM PST 24
Peak memory 200988 kb
Host smart-cfd707fb-a6d2-4aa1-9e16-1690a46f15b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425392037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1425392037
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3690614315
Short name T369
Test name
Test status
Simulation time 612970218578 ps
CPU time 647.34 seconds
Started Jan 24 07:29:11 PM PST 24
Finished Jan 24 07:40:00 PM PST 24
Peak memory 209852 kb
Host smart-6e247069-b172-44f8-afaf-98c200bf0dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690614315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3690614315
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1955760491
Short name T667
Test name
Test status
Simulation time 497566624 ps
CPU time 1.17 seconds
Started Jan 24 07:08:44 PM PST 24
Finished Jan 24 07:08:46 PM PST 24
Peak memory 200896 kb
Host smart-ca8997f4-ecc9-45a6-84a0-150d0155fb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955760491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1955760491
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2590268652
Short name T240
Test name
Test status
Simulation time 160533853687 ps
CPU time 135.72 seconds
Started Jan 24 07:08:37 PM PST 24
Finished Jan 24 07:10:54 PM PST 24
Peak memory 201168 kb
Host smart-666b992b-54c9-4fbe-b6e8-79028df70d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590268652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2590268652
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3747980834
Short name T840
Test name
Test status
Simulation time 165915469696 ps
CPU time 83.4 seconds
Started Jan 24 07:36:43 PM PST 24
Finished Jan 24 07:38:07 PM PST 24
Peak memory 201252 kb
Host smart-9956e871-6bc3-4b74-9036-8b7c8a1e145f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747980834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3747980834
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.98836818
Short name T352
Test name
Test status
Simulation time 496057255046 ps
CPU time 1183.57 seconds
Started Jan 24 07:08:39 PM PST 24
Finished Jan 24 07:28:24 PM PST 24
Peak memory 201240 kb
Host smart-b7a3abe4-7911-4f94-8132-2dd419be89af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98836818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.98836818
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.312717350
Short name T465
Test name
Test status
Simulation time 488484990549 ps
CPU time 582.69 seconds
Started Jan 24 07:08:39 PM PST 24
Finished Jan 24 07:18:23 PM PST 24
Peak memory 201096 kb
Host smart-718f6fc5-3d7c-47f2-8207-7d0042c487c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=312717350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.312717350
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1257977901
Short name T228
Test name
Test status
Simulation time 162492678415 ps
CPU time 28.47 seconds
Started Jan 24 07:18:45 PM PST 24
Finished Jan 24 07:19:14 PM PST 24
Peak memory 201220 kb
Host smart-39be9e7d-0367-4067-9808-2de2e521817a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257977901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1257977901
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3635819926
Short name T599
Test name
Test status
Simulation time 321507872702 ps
CPU time 195.65 seconds
Started Jan 24 07:27:39 PM PST 24
Finished Jan 24 07:30:56 PM PST 24
Peak memory 201252 kb
Host smart-f3e121e1-9fa8-46f1-b829-3af9019f54d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635819926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3635819926
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.128563171
Short name T164
Test name
Test status
Simulation time 88297823255 ps
CPU time 309.59 seconds
Started Jan 24 10:08:33 PM PST 24
Finished Jan 24 10:13:43 PM PST 24
Peak memory 201604 kb
Host smart-b3d93741-5cf5-4976-aa5d-cbb91b01b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128563171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.128563171
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1717055121
Short name T776
Test name
Test status
Simulation time 44977056219 ps
CPU time 38.97 seconds
Started Jan 24 08:06:48 PM PST 24
Finished Jan 24 08:07:28 PM PST 24
Peak memory 201060 kb
Host smart-adf742f9-8f2b-4a33-8597-9a7c3cf04cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717055121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1717055121
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2079661308
Short name T580
Test name
Test status
Simulation time 2866499535 ps
CPU time 6.49 seconds
Started Jan 24 07:08:42 PM PST 24
Finished Jan 24 07:08:50 PM PST 24
Peak memory 200948 kb
Host smart-5f998afc-2ddc-464b-aa37-e06a33f0a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079661308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2079661308
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3158038962
Short name T808
Test name
Test status
Simulation time 5704574002 ps
CPU time 13.61 seconds
Started Jan 24 07:08:34 PM PST 24
Finished Jan 24 07:08:52 PM PST 24
Peak memory 201052 kb
Host smart-7bd5c594-0c6f-48db-b571-def5931b4cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158038962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3158038962
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2404791690
Short name T43
Test name
Test status
Simulation time 24523122162 ps
CPU time 113.64 seconds
Started Jan 24 07:08:44 PM PST 24
Finished Jan 24 07:10:39 PM PST 24
Peak memory 209764 kb
Host smart-005fdccf-42b3-4dbd-8144-07932b7963b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404791690 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2404791690
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2000096255
Short name T722
Test name
Test status
Simulation time 281878785 ps
CPU time 1.25 seconds
Started Jan 24 07:09:04 PM PST 24
Finished Jan 24 07:09:06 PM PST 24
Peak memory 200900 kb
Host smart-5b26bef7-a258-46da-9750-9df38f55071b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000096255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2000096255
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1486504382
Short name T57
Test name
Test status
Simulation time 165888128709 ps
CPU time 77.61 seconds
Started Jan 24 07:08:56 PM PST 24
Finished Jan 24 07:10:15 PM PST 24
Peak memory 201108 kb
Host smart-1e25bd3c-150e-429f-aabd-ecd6876ff87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486504382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1486504382
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3941251771
Short name T327
Test name
Test status
Simulation time 328613705328 ps
CPU time 763.27 seconds
Started Jan 24 07:08:48 PM PST 24
Finished Jan 24 07:21:33 PM PST 24
Peak memory 201252 kb
Host smart-e77c0b5b-e424-49bd-8213-f1abe15756a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941251771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3941251771
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.313255554
Short name T121
Test name
Test status
Simulation time 168585655868 ps
CPU time 97.68 seconds
Started Jan 24 07:08:56 PM PST 24
Finished Jan 24 07:10:35 PM PST 24
Peak memory 201160 kb
Host smart-4cda25e1-a779-4284-a0d0-27b6415a6c86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=313255554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.313255554
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.643678674
Short name T849
Test name
Test status
Simulation time 163967402352 ps
CPU time 201.29 seconds
Started Jan 24 09:00:48 PM PST 24
Finished Jan 24 09:04:10 PM PST 24
Peak memory 201212 kb
Host smart-08223724-1c31-41e7-8eac-b2b4256d1121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643678674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.643678674
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.158076620
Short name T697
Test name
Test status
Simulation time 322971110439 ps
CPU time 367.63 seconds
Started Jan 24 07:08:43 PM PST 24
Finished Jan 24 07:14:52 PM PST 24
Peak memory 201180 kb
Host smart-bd38d444-c2be-49f0-b212-df1980545370
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=158076620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.158076620
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.548546493
Short name T93
Test name
Test status
Simulation time 489797893202 ps
CPU time 568.64 seconds
Started Jan 24 07:08:50 PM PST 24
Finished Jan 24 07:18:22 PM PST 24
Peak memory 201204 kb
Host smart-5ab9415a-3016-4133-ab8a-4b4318c0790c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548546493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.548546493
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1744966384
Short name T789
Test name
Test status
Simulation time 160977138987 ps
CPU time 355.44 seconds
Started Jan 24 07:08:54 PM PST 24
Finished Jan 24 07:14:52 PM PST 24
Peak memory 201140 kb
Host smart-c1bb67d6-73b4-4769-bd8b-2bfbfb23a62a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744966384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1744966384
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1984553001
Short name T193
Test name
Test status
Simulation time 89886348144 ps
CPU time 255.05 seconds
Started Jan 24 07:08:55 PM PST 24
Finished Jan 24 07:13:12 PM PST 24
Peak memory 201512 kb
Host smart-73f1941a-dfb4-408a-9c3a-a1636bf5d28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984553001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1984553001
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3817944384
Short name T435
Test name
Test status
Simulation time 25583756432 ps
CPU time 61.54 seconds
Started Jan 24 07:09:04 PM PST 24
Finished Jan 24 07:10:06 PM PST 24
Peak memory 201012 kb
Host smart-9830c0f3-939c-496b-a53f-b3376ba2a174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817944384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3817944384
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2208850467
Short name T726
Test name
Test status
Simulation time 5227293573 ps
CPU time 3.97 seconds
Started Jan 24 07:08:55 PM PST 24
Finished Jan 24 07:09:01 PM PST 24
Peak memory 201008 kb
Host smart-947cb241-bec1-4448-88f4-47e123ff9efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208850467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2208850467
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.840320906
Short name T88
Test name
Test status
Simulation time 5839105591 ps
CPU time 14.64 seconds
Started Jan 24 07:08:41 PM PST 24
Finished Jan 24 07:08:56 PM PST 24
Peak memory 201000 kb
Host smart-179c1954-0189-41a5-98b9-cda4ab4abe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840320906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.840320906
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.689719564
Short name T843
Test name
Test status
Simulation time 329029430253 ps
CPU time 1198.66 seconds
Started Jan 24 07:08:59 PM PST 24
Finished Jan 24 07:28:59 PM PST 24
Peak memory 217844 kb
Host smart-17287f84-c9f9-4cf0-b20b-3ddce6b5d1aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689719564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.689719564
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1312919881
Short name T155
Test name
Test status
Simulation time 55281754133 ps
CPU time 21.11 seconds
Started Jan 24 07:08:54 PM PST 24
Finished Jan 24 07:09:18 PM PST 24
Peak memory 201312 kb
Host smart-8e3c3e34-75e3-43b2-8104-833ca5273520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312919881 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1312919881
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2720406374
Short name T597
Test name
Test status
Simulation time 522270583 ps
CPU time 0.88 seconds
Started Jan 24 07:09:31 PM PST 24
Finished Jan 24 07:09:34 PM PST 24
Peak memory 200896 kb
Host smart-a5157ef9-5b49-48dd-9892-0ab1c2977be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720406374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2720406374
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.450267470
Short name T616
Test name
Test status
Simulation time 324945397290 ps
CPU time 205.61 seconds
Started Jan 24 07:09:13 PM PST 24
Finished Jan 24 07:12:40 PM PST 24
Peak memory 201120 kb
Host smart-fa2d97bb-f667-4e4c-b97c-fe71c081f9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450267470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.450267470
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3608231003
Short name T819
Test name
Test status
Simulation time 487274413260 ps
CPU time 609.87 seconds
Started Jan 24 07:09:08 PM PST 24
Finished Jan 24 07:19:18 PM PST 24
Peak memory 201172 kb
Host smart-cbc07f6d-c48f-44f3-b59b-a2de4109ec67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608231003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3608231003
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3098723064
Short name T664
Test name
Test status
Simulation time 164875457258 ps
CPU time 407.41 seconds
Started Jan 24 07:15:45 PM PST 24
Finished Jan 24 07:22:33 PM PST 24
Peak memory 201228 kb
Host smart-21c3626b-b7c7-4dcf-a790-3d3b771f22f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098723064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3098723064
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.988851505
Short name T516
Test name
Test status
Simulation time 329174715289 ps
CPU time 412.33 seconds
Started Jan 24 07:09:00 PM PST 24
Finished Jan 24 07:15:53 PM PST 24
Peak memory 201032 kb
Host smart-3fe8dcc4-332d-4c33-a6f9-bd45f34c2f78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=988851505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.988851505
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.4047934930
Short name T600
Test name
Test status
Simulation time 163485591180 ps
CPU time 100.65 seconds
Started Jan 24 07:09:08 PM PST 24
Finished Jan 24 07:10:49 PM PST 24
Peak memory 201164 kb
Host smart-8f8f0af6-841c-4e2b-8148-f6f9c0245ae7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047934930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.4047934930
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.893687508
Short name T574
Test name
Test status
Simulation time 495227422433 ps
CPU time 247.38 seconds
Started Jan 24 08:34:06 PM PST 24
Finished Jan 24 08:38:15 PM PST 24
Peak memory 201212 kb
Host smart-e8630ebd-e84b-42d0-834b-ad01ea35e1f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893687508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.893687508
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1231871773
Short name T563
Test name
Test status
Simulation time 82557969424 ps
CPU time 288.85 seconds
Started Jan 24 07:09:21 PM PST 24
Finished Jan 24 07:14:10 PM PST 24
Peak memory 201476 kb
Host smart-a732b14c-6ea7-44fa-8055-8a4a95fc69e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231871773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1231871773
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.253719324
Short name T177
Test name
Test status
Simulation time 25155710934 ps
CPU time 59.13 seconds
Started Jan 24 07:42:48 PM PST 24
Finished Jan 24 07:43:49 PM PST 24
Peak memory 201044 kb
Host smart-ca6a2655-d899-4168-af88-81bcd97fdcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253719324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.253719324
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.51564086
Short name T531
Test name
Test status
Simulation time 4945484351 ps
CPU time 1.47 seconds
Started Jan 24 07:09:28 PM PST 24
Finished Jan 24 07:09:32 PM PST 24
Peak memory 201024 kb
Host smart-f138b728-a3fc-4563-86e6-dc7d19adaf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51564086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.51564086
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3340828425
Short name T770
Test name
Test status
Simulation time 6112410686 ps
CPU time 15.4 seconds
Started Jan 24 07:08:58 PM PST 24
Finished Jan 24 07:09:14 PM PST 24
Peak memory 201000 kb
Host smart-e56be95e-0f92-4931-92a3-99b09a87c2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340828425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3340828425
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2080792318
Short name T569
Test name
Test status
Simulation time 9209004230 ps
CPU time 11.8 seconds
Started Jan 24 07:09:30 PM PST 24
Finished Jan 24 07:09:44 PM PST 24
Peak memory 200936 kb
Host smart-49deb833-b461-4548-8f2b-01fbf2843de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080792318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2080792318
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.505903298
Short name T606
Test name
Test status
Simulation time 503641219 ps
CPU time 0.71 seconds
Started Jan 24 07:10:02 PM PST 24
Finished Jan 24 07:10:04 PM PST 24
Peak memory 200812 kb
Host smart-622df766-af62-4961-abfd-b385ef1edcab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505903298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.505903298
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1487822208
Short name T267
Test name
Test status
Simulation time 327223582531 ps
CPU time 482.78 seconds
Started Jan 24 07:09:41 PM PST 24
Finished Jan 24 07:17:46 PM PST 24
Peak memory 201236 kb
Host smart-4f4de913-726c-447f-aba2-3ae3ada194ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487822208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1487822208
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.606857152
Short name T774
Test name
Test status
Simulation time 481230435283 ps
CPU time 1028.64 seconds
Started Jan 24 07:09:36 PM PST 24
Finished Jan 24 07:26:46 PM PST 24
Peak memory 201132 kb
Host smart-14200530-3f31-4225-84b2-add409f7da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606857152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.606857152
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1330951390
Short name T58
Test name
Test status
Simulation time 159667588633 ps
CPU time 100 seconds
Started Jan 24 07:09:40 PM PST 24
Finished Jan 24 07:11:22 PM PST 24
Peak memory 201224 kb
Host smart-b2a498f8-ce59-47c3-a57a-9676d047d2be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330951390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1330951390
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.132634710
Short name T166
Test name
Test status
Simulation time 333520511220 ps
CPU time 396.53 seconds
Started Jan 24 07:09:31 PM PST 24
Finished Jan 24 07:16:09 PM PST 24
Peak memory 201248 kb
Host smart-66fe660d-8f49-4f11-acdd-58aea1939c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132634710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.132634710
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2009464209
Short name T116
Test name
Test status
Simulation time 486342750311 ps
CPU time 296.17 seconds
Started Jan 24 07:09:38 PM PST 24
Finished Jan 24 07:14:35 PM PST 24
Peak memory 201228 kb
Host smart-546c3bc8-88e6-4d74-9b26-efbc6d09d1da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009464209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2009464209
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1569880390
Short name T469
Test name
Test status
Simulation time 333840911640 ps
CPU time 147.93 seconds
Started Jan 24 07:09:36 PM PST 24
Finished Jan 24 07:12:05 PM PST 24
Peak memory 201156 kb
Host smart-1ff851d7-b9c8-46ee-bc85-ba921d18bcd4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569880390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1569880390
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2957518859
Short name T623
Test name
Test status
Simulation time 118819036314 ps
CPU time 473.2 seconds
Started Jan 24 07:09:58 PM PST 24
Finished Jan 24 07:17:52 PM PST 24
Peak memory 201492 kb
Host smart-b92897dd-9792-4bca-b616-9a5945ea5e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957518859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2957518859
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2180259282
Short name T585
Test name
Test status
Simulation time 40038034245 ps
CPU time 24.04 seconds
Started Jan 24 07:09:49 PM PST 24
Finished Jan 24 07:10:14 PM PST 24
Peak memory 200932 kb
Host smart-cf17af24-33d7-4f2b-8a61-3f6a3f0f2549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180259282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2180259282
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2364442065
Short name T428
Test name
Test status
Simulation time 3078580409 ps
CPU time 2.65 seconds
Started Jan 24 07:09:49 PM PST 24
Finished Jan 24 07:09:52 PM PST 24
Peak memory 201028 kb
Host smart-50f98f5e-e2d9-4dca-a1f9-2d0d620cab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364442065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2364442065
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3435048183
Short name T496
Test name
Test status
Simulation time 5718662126 ps
CPU time 14.36 seconds
Started Jan 24 07:09:31 PM PST 24
Finished Jan 24 07:09:46 PM PST 24
Peak memory 201056 kb
Host smart-77f88255-7f86-4268-be9f-5206e00d7954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435048183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3435048183
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2346426415
Short name T281
Test name
Test status
Simulation time 202068770157 ps
CPU time 123.26 seconds
Started Jan 24 07:09:57 PM PST 24
Finished Jan 24 07:12:01 PM PST 24
Peak memory 201180 kb
Host smart-9acd43a6-bdfa-48ca-848f-23a7072b1593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346426415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2346426415
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1178183410
Short name T522
Test name
Test status
Simulation time 143102175177 ps
CPU time 48.06 seconds
Started Jan 24 07:09:58 PM PST 24
Finished Jan 24 07:10:47 PM PST 24
Peak memory 201232 kb
Host smart-b24e05ba-a667-4fa5-bbc8-790224bef329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178183410 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1178183410
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.587174408
Short name T657
Test name
Test status
Simulation time 343733640 ps
CPU time 1.37 seconds
Started Jan 24 07:10:16 PM PST 24
Finished Jan 24 07:10:18 PM PST 24
Peak memory 200900 kb
Host smart-2a5f8088-38a5-432c-9bbe-d3394fcb1a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587174408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.587174408
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.570644526
Short name T807
Test name
Test status
Simulation time 164976203800 ps
CPU time 53.46 seconds
Started Jan 24 10:43:02 PM PST 24
Finished Jan 24 10:43:56 PM PST 24
Peak memory 201264 kb
Host smart-633e9eda-85b5-4c3d-b43a-99e18f4c434f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570644526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.570644526
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3028643240
Short name T832
Test name
Test status
Simulation time 518018249919 ps
CPU time 331.35 seconds
Started Jan 24 07:10:12 PM PST 24
Finished Jan 24 07:15:44 PM PST 24
Peak memory 201124 kb
Host smart-d59f15e9-5172-4d3f-9616-b3285e09411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028643240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3028643240
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3265115005
Short name T105
Test name
Test status
Simulation time 492122292787 ps
CPU time 1213.18 seconds
Started Jan 24 07:09:57 PM PST 24
Finished Jan 24 07:30:10 PM PST 24
Peak memory 201084 kb
Host smart-395ef728-7dab-4da3-a2c1-2b349d6e8b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265115005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3265115005
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4269130408
Short name T649
Test name
Test status
Simulation time 485087813384 ps
CPU time 602.83 seconds
Started Jan 24 07:10:09 PM PST 24
Finished Jan 24 07:20:13 PM PST 24
Peak memory 201068 kb
Host smart-e5cf3587-de8d-4d44-a2f6-3e457f4a7a00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269130408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4269130408
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2412341093
Short name T90
Test name
Test status
Simulation time 322944085394 ps
CPU time 720.15 seconds
Started Jan 24 07:09:59 PM PST 24
Finished Jan 24 07:22:01 PM PST 24
Peak memory 201192 kb
Host smart-71999d12-2917-41a7-af0c-918388d864cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412341093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2412341093
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3254185765
Short name T646
Test name
Test status
Simulation time 328983020696 ps
CPU time 207.48 seconds
Started Jan 24 07:09:59 PM PST 24
Finished Jan 24 07:13:28 PM PST 24
Peak memory 201172 kb
Host smart-de2fe495-6c88-44b2-9320-14f27efe09e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254185765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3254185765
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.209569594
Short name T323
Test name
Test status
Simulation time 324635969441 ps
CPU time 786.13 seconds
Started Jan 24 07:20:19 PM PST 24
Finished Jan 24 07:33:28 PM PST 24
Peak memory 201164 kb
Host smart-de78572a-4cda-4444-bf40-1e249bc9466e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209569594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.209569594
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1280496277
Short name T639
Test name
Test status
Simulation time 504103681398 ps
CPU time 104.82 seconds
Started Jan 24 07:19:20 PM PST 24
Finished Jan 24 07:21:06 PM PST 24
Peak memory 201192 kb
Host smart-64aa4dc6-ca2b-4ba1-ad2e-b8ac599a5d23
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280496277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1280496277
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.459252658
Short name T537
Test name
Test status
Simulation time 113060169289 ps
CPU time 606.12 seconds
Started Jan 24 07:10:09 PM PST 24
Finished Jan 24 07:20:15 PM PST 24
Peak memory 201540 kb
Host smart-435debae-fc35-4600-80f2-61b6f1d6fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459252658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.459252658
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3745339812
Short name T634
Test name
Test status
Simulation time 34426830448 ps
CPU time 8.24 seconds
Started Jan 24 07:43:21 PM PST 24
Finished Jan 24 07:43:30 PM PST 24
Peak memory 201036 kb
Host smart-bb3ff909-8ef3-4c2f-abf2-6ae5ac9ecffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745339812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3745339812
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2118878316
Short name T821
Test name
Test status
Simulation time 2823335238 ps
CPU time 6.82 seconds
Started Jan 24 07:10:08 PM PST 24
Finished Jan 24 07:10:15 PM PST 24
Peak memory 201020 kb
Host smart-72252baa-369e-4c39-97db-1cba156a3259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118878316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2118878316
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3294525656
Short name T485
Test name
Test status
Simulation time 6026742606 ps
CPU time 7.46 seconds
Started Jan 24 07:09:59 PM PST 24
Finished Jan 24 07:10:08 PM PST 24
Peak memory 200992 kb
Host smart-bd20020f-21a5-44c0-b506-cfffd9583f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294525656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3294525656
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1408753846
Short name T610
Test name
Test status
Simulation time 26101922813 ps
CPU time 75.26 seconds
Started Jan 24 07:10:18 PM PST 24
Finished Jan 24 07:11:34 PM PST 24
Peak memory 209916 kb
Host smart-848d6361-6a64-4047-9a6a-4157fd162512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408753846 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1408753846
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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