Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6791	1			T15	60		T16	10		T18	57
testmodes[AdcCtrlTestmodeNormal]	5367	1			T12	2		T14	1		T15	61
testmodes[AdcCtrlTestmodeLowpower]	5863	1			T13	1		T15	75		T18	61
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3688	1			T15	21		T16	3		T18	20
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1601	1			T15	13		T16	6		T18	25
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1389	1			T15	25		T18	12		T24	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1707	1			T15	17		T16	6		T18	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1989	1			T12	1		T15	20		T16	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1333	1			T15	24		T18	22		T24	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1281	1			T15	22		T18	16		T24	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1440	1			T15	28		T18	19		T24	6
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2899	1			T15	25		T18	26		T19	1