Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20050

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

4969

1

T12

2

T13

6

T17

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20001

1

T6

2

T26

1

T41

1

auto[1]

5018

1

T12

2

T13

6

T17

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T213	1		-	-		-	-
values[0]	4	1			T21	1		T214	1		T215	1
values[1]	777	1			T19	27		T20	10		T21	1
values[2]	588	1			T34	2		T109	22		T178	1
values[3]	500	1			T93	23		T34	9		T99	1
values[4]	675	1			T97	1		T121	1		T91	15
values[5]	686	1			T34	11		T100	14		T142	31
values[6]	485	1			T155	1		T114	1		T125	1
values[7]	584	1			T19	16		T21	1		T97	1
values[8]	458	1			T99	34		T216	24		T155	5
values[9]	3110	1			T12	2		T13	6		T14	12
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	980	1			T19	27		T20	10		T21	2
values[1]	2579	1			T12	2		T13	6		T17	2
values[2]	572	1			T93	23		T34	9		T99	1
values[3]	691	1			T97	1		T121	1		T91	15
values[4]	627	1			T34	11		T101	5		T142	31
values[5]	454	1			T155	1		T114	1		T125	1
values[6]	569	1			T19	16		T21	1		T97	1
values[7]	545	1			T99	34		T155	5		T103	20
values[8]	707	1			T14	12		T20	13		T97	1
values[9]	123	1			T98	11		T108	1		T102	10
minimum	17172	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T19	14		T20	8		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T21	1		T24	7		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T109	3		T178	1		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1277	1			T12	2		T13	6		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T93	11		T99	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T34	9		T144	1		T217	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T121	1		T91	10		T99	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T97	1		T178	1		T125	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	9		T101	1		T142	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T142	13		T114	1		T111	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T167	1		T218	2		T219	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T155	1		T114	1		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T35	6		T100	8		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T19	5		T21	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T99	16		T186	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T155	5		T103	11		T220	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	1		T97	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	13		T121	1		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T98	11		T108	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T102	1		T48	4		T213	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T15	196		T16	19		T18	186
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T19	13		T20	2		T109	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T24	1		T113	23		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T109	2		T222	9		T198	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1031	1			T104	14		T105	15		T223	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T93	12		T144	2		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T144	3		T217	8		T186	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T91	5		T99	6		T100	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T125	10		T138	12		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	2		T101	4		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	15		T111	5		T187	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T218	4		T219	14		T224	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T111	15		T50	2		T225	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T35	2		T216	13		T102	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T19	11		T117	13		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T99	18		T186	6		T218	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T103	9		T227	1		T228	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	11		T112	23		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T118	13		T92	3		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T138	8		T219	4		T229	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T102	9		T48	2		T230	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T213	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T215	1		T148	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T21	1		T214	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T19	14		T20	8		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	7		T113	20		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T109	16		T178	1		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T34	1		T147	1		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T93	11		T99	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T34	9		T118	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T121	1		T91	10		T99	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T97	1		T125	11		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T34	9		T100	4		T142	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T142	13		T114	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T110	7		T167	1		T218	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T155	1		T114	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	6		T100	8		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T19	5		T21	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T99	16		T216	11		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T155	5		T103	11		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	1		T97	1		T98	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1424	1			T12	2		T13	6		T17	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T19	13		T20	2		T166	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T24	1		T113	23		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T109	6		T198	7		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T34	1		T147	7		T234	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T93	12		T144	2		T186	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T118	3		T144	3		T217	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T91	5		T99	6		T101	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T125	10		T138	12		T146	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	2		T100	10		T102	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T142	15		T139	12		T187	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T218	4		T224	3		T235	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T111	20		T116	13		T225	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T35	2		T102	2		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	11		T117	13		T226	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T99	18		T216	13		T186	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T103	9		T227	1		T181	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T14	11		T112	23		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1194	1			T104	14		T105	15		T223	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T19	14		T20	3		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T21	1		T24	6		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T109	3		T178	1		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1353	1			T12	2		T13	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T93	13		T99	1		T144	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T34	1		T144	4		T217	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T121	1		T91	10		T99	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T97	1		T178	1		T125	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	3		T101	5		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T142	16		T114	1		T111	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T167	1		T218	5		T219	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T155	1		T114	1		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T35	6		T100	1		T216	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	12		T21	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T99	19		T186	7		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T155	1		T103	10		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	12		T97	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T20	1		T121	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T98	1		T108	1		T138	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T102	10		T48	3		T213	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17153	1			T6	2		T26	1		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T19	13		T20	7		T109	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T24	2		T113	18		T146	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T109	2		T222	3		T198	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	955	1			T13	5		T22	12		T23	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T93	10		T186	5		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T34	8		T217	9		T186	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T91	5		T99	4		T100	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T125	10		T138	11		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T34	8		T142	2		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T142	12		T111	13		T187	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T218	1		T219	13		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T111	14		T237	10		T170	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	2		T100	7		T216	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T19	4		T139	4		T186	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T99	15		T218	7		T128	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T155	4		T103	10		T220	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T112	13		T140	2		T115	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T20	12		T221	9		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T98	10		T219	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T48	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T238	8		T239	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T213	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T215	1		T148	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T21	1		T214	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T19	14		T20	3		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T24	6		T113	25		T138	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T109	8		T178	1		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T34	2		T147	8		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T93	13		T99	1		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T34	1		T118	4		T144	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T121	1		T91	10		T99	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T97	1		T125	11		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T34	3		T100	11		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T142	16		T114	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T110	1		T167	1		T218	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T155	1		T114	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	6		T100	1		T102	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T19	12		T21	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T99	19		T216	14		T186	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T155	1		T103	10		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T14	12		T97	1		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1553	1			T12	2		T13	1		T17	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T19	13		T20	7		T166	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T24	2		T113	18		T146	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T109	14		T198	2		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T240	8		T133	10		T241	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T93	10		T186	5		T222	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	8		T217	9		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T91	5		T99	4		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T125	10		T138	11		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	8		T100	3		T142	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T142	12		T139	11		T187	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T110	6		T218	1		T220	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T111	27		T116	14		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	2		T100	7		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T19	4		T139	4		T186	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T99	15		T216	10		T218	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T155	4		T103	10		T227	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T98	10		T112	13		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1065	1			T13	5		T20	12		T22	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22118

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2901

1

T14

12

T19

43

T21

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19798

1

T6

2

T26

1

T41

1

auto[1]

5221

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	74	1			T96	1		T243	18		T244	12
values[1]	452	1			T91	15		T99	34		T102	3
values[2]	618	1			T19	16		T20	13		T24	6
values[3]	650	1			T24	2		T99	1		T108	1
values[4]	2650	1			T12	2		T13	6		T14	12
values[5]	533	1			T19	27		T97	1		T34	9
values[6]	681	1			T216	24		T155	1		T92	7
values[7]	566	1			T97	1		T99	11		T118	4
values[8]	630	1			T144	3		T214	1		T113	28
values[9]	1014	1			T21	2		T34	11		T121	1
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	648	1			T34	2		T121	1		T91	15
values[1]	532	1			T20	13		T24	8		T93	23
values[2]	766	1			T14	12		T19	16		T21	1
values[3]	2607	1			T12	2		T13	6		T17	2
values[4]	525	1			T19	27		T97	1		T35	8
values[5]	760	1			T99	11		T216	24		T102	38
values[6]	559	1			T97	1		T118	4		T155	1
values[7]	727	1			T21	1		T221	10		T144	7
values[8]	527	1			T21	1		T34	11		T121	1
values[9]	191	1			T125	1		T146	15		T231	1
minimum	17177	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T34	1		T91	10		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T121	1		T99	16		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T20	13		T24	7		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T93	11		T98	11		T100	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T108	1		T155	5		T217	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	1		T19	5		T21	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T12	2		T13	6		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T97	1		T117	1		T142	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T97	1		T92	1		T112	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T19	14		T35	6		T114	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T99	5		T216	11		T102	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T102	1		T138	1		T110	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T92	1		T113	13		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T97	1		T118	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T221	10		T144	2		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T21	1		T157	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T21	1		T121	1		T142	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T34	9		T114	1		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T245	4		T246	1		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T125	1		T146	3		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16999	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T198	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T34	1		T91	5		T102	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T99	18		T138	9		T186	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T24	1		T186	6		T129	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T93	12		T113	8		T125	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T217	8		T111	5		T179	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	11		T19	11		T100	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T20	2		T104	14		T105	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T117	13		T247	1		T228	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T92	6		T112	10		T113	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T19	13		T35	2		T111	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T99	6		T216	13		T102	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T102	9		T138	8		T222	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T92	3		T113	15		T140	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T118	3		T112	13		T166	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T144	5		T139	12		T146	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	1		T186	6		T116	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T142	15		T186	15		T225	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T34	2		T138	12		T186	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T246	2		T148	2		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T146	12		T236	10		T218	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T198	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T96	1		T243	7		T244	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T160	3		T249	2		T250	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T91	10		T102	1		T109	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T99	16		T138	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T20	13		T24	5		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T19	5		T93	11		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	2		T99	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T118	1		T119	1		T48	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T12	2		T13	6		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	1		T21	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T97	1		T34	9		T112	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T19	14		T35	6		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T216	11		T92	1		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T155	1		T102	1		T110	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T99	5		T92	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T97	1		T118	1		T112	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T144	1		T214	1		T113	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T157	1		T158	1		T166	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T21	1		T121	1		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T21	1		T34	9		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T243	11		T251	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T160	2		T249	1		T252	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T91	5		T102	2		T109	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T99	18		T138	9		T186	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T24	1		T34	1		T129	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	11		T93	12		T100	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T111	5		T179	2		T219	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T118	13		T48	2		T181	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T20	2		T104	14		T105	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	11		T117	13		T253	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T112	10		T113	4		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T19	13		T35	2		T111	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T216	13		T92	6		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T102	9		T222	9		T254	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T99	6		T92	3		T102	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T118	3		T112	13		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T144	2		T113	15		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T166	2		T186	6		T116	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T144	3		T142	15		T139	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T34	2		T138	12		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1