Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22135

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2884

1

T21

1

T24

2

T97

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19840

1

T6

2

T26

1

T41

1

auto[1]

5179

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	199	1			T142	28		T102	11		T186	2
values[0]	55	1			T140	6		T263	10		T257	15
values[1]	558	1			T19	43		T20	13		T35	8
values[2]	2710	1			T12	2		T13	6		T17	2
values[3]	557	1			T21	1		T24	2		T97	1
values[4]	660	1			T21	1		T24	6		T121	1
values[5]	698	1			T14	12		T34	2		T117	14
values[6]	481	1			T121	1		T112	25		T157	1
values[7]	651	1			T97	1		T34	11		T99	34
values[8]	611	1			T21	1		T34	9		T216	24
values[9]	688	1			T93	23		T97	1		T221	10
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	575	1			T19	43		T20	13		T35	8
values[1]	2670	1			T12	2		T13	6		T17	2
values[2]	729	1			T21	1		T24	2		T91	15
values[3]	493	1			T21	1		T24	6		T34	2
values[4]	645	1			T14	12		T121	1		T117	14
values[5]	581	1			T157	1		T114	2		T242	9
values[6]	651	1			T97	1		T34	20		T99	34
values[7]	523	1			T21	1		T118	4		T92	4
values[8]	728	1			T93	23		T97	1		T221	10
values[9]	74	1			T186	2		T231	1		T159	1
minimum	17350	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T19	19		T20	13		T113	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T35	6		T226	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T12	2		T13	6		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T97	1		T99	5		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T21	1		T100	8		T186	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T24	2		T91	10		T142	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T21	1		T24	5		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T34	1		T121	1		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	1		T121	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T108	1		T102	1		T112	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T157	1		T114	1		T242	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T114	1		T48	4		T231	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T99	16		T100	4		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T97	1		T34	18		T103	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T125	1		T186	13		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T21	1		T118	1		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T93	11		T97	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T221	10		T101	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T186	1		T231	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T159	1		T343	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17040	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T140	5		T147	1		T272	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T19	24		T113	8		T111	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T35	2		T226	10		T101	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T20	2		T104	14		T105	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T99	6		T265	10		T260	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T186	7		T198	7		T253	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T91	5		T102	2		T113	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T24	1		T48	1		T201	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	1		T186	6		T51	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	11		T117	13		T118	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T102	16		T112	13		T138	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T139	12		T219	13		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	2		T169	1		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T99	18		T100	10		T216	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T34	2		T103	9		T109	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T186	15		T289	6		T268	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T118	3		T92	3		T102	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T93	12		T144	2		T142	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T101	4		T144	3		T186	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T186	1		T295	3		T269	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T267	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T140	1		T224	3		T225	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T142	13		T102	6		T186	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T310	1		T344	3		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T140	5		T263	10		T257	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	19		T20	13		T111	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T35	6		T226	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T12	2		T13	6		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T99	5		T101	1		T265	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T21	1		T100	8		T113	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	2		T97	1		T91	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T21	1		T24	5		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T121	1		T142	3		T113	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	1		T117	1		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T34	1		T108	1		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T121	1		T157	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T112	12		T114	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T99	16		T100	4		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T97	1		T34	9		T109	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T216	11		T254	1		T285	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T21	1		T34	9		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T93	11		T97	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T221	10		T101	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T142	15		T102	5		T186	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T310	7		T344	10		T345	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T140	1		T257	7		T346	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T19	24		T111	15		T146	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T35	2		T226	10		T224	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T20	2		T104	14		T105	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T99	6		T101	3		T265	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T113	4		T186	7		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T91	5		T102	2		T128	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T24	1		T48	1		T260	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T113	15		T187	3		T236	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	11		T117	13		T118	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T34	1		T102	16		T186	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T219	13		T275	6		T247	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T112	13		T138	8		T48	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T99	18		T100	10		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T34	2		T109	2		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T216	13		T254	11		T289	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T118	3		T92	3		T102	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T93	12		T144	2		T217	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T101	4		T144	3		T186	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	26		T20	1		T113	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	6		T226	11		T101	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T12	2		T13	1		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T97	1		T99	7		T265	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	1		T100	1		T186	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T24	2		T91	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T21	1		T24	4		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T34	2		T121	1		T186	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	12		T121	1		T117	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T108	1		T102	17		T112	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T157	1		T114	1		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T114	1		T48	3		T231	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T99	19		T100	11		T216	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T97	1		T34	4		T103	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T125	1		T186	16		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	1		T118	4		T92	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T93	13		T97	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T221	1		T101	5		T144	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T186	2		T231	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T159	1		T343	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17186	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T140	4		T147	1		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T19	17		T20	12		T113	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T35	2		T272	12		T261	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T13	5		T20	7		T22	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T99	4		T170	20		T133	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T100	7		T186	3		T198	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T91	5		T142	2		T113	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T24	2		T277	3		T201	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T228	13		T267	12		T318	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T116	14		T243	6		T220	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T112	11		T278	2		T170	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T242	8		T139	11		T219	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T48	3		T169	1		T237	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T99	15		T100	3		T216	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T34	16		T103	10		T109	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T186	12		T289	5		T279	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T112	2		T110	6		T111	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T93	10		T155	4		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T221	9		T186	1		T280	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T342	6		T258	8		T330	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T267	2		T263	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T301	3		T219	13		T244	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T140	2		T272	4		T224	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T142	16		T102	6		T186	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T310	8		T344	11		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T140	4		T263	1		T257	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T19	26		T20	1		T111	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T35	6		T226	11		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T12	2		T13	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T99	7		T101	4		T265	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T21	1		T100	1		T113	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T24	2		T97	1		T91	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T21	1		T24	4		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T121	1		T142	1		T113	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	12		T117	14		T118	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	2		T108	1		T102	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T121	1		T157	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T112	14		T114	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T99	19		T100	11		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T97	1		T34	3		T109	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T216	14		T254	12		T285	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	1		T34	1		T118	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T93	13		T97	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T221	1		T101	5		T144	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T142	12		T102	5		T218	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T344	2		T345	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T140	2		T263	9		T257	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T19	17		T20	12		T111	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T35	2		T272	4		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T13	5		T20	7		T22	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T99	4		T272	12		T247	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T100	7		T113	12		T186	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T91	5		T128	12		T237	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	2		T260	6		T277	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T142	2		T113	12		T111	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T116	14		T243	6		T220	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T278	2		T235	2		T283	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T242	8		T219	12		T284	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T112	11		T48	3		T169	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T99	15		T100	3		T139	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T34	8		T109	2		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T216	10		T285	1		T289	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T34	8		T103	10		T112	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T93	10		T155	4		T217	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T221	9		T186	1		T286	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19