Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21988

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

3031

1

T14

12

T19

27

T20

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19708

1

T6

2

T26

1

T41

1

auto[1]

5311

1

T12

2

T13

6

T17

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	129	1			T117	14		T35	8		T217	18
values[0]	45	1			T112	13		T201	5		T347	1
values[1]	517	1			T21	1		T121	1		T99	1
values[2]	465	1			T99	11		T144	4		T155	5
values[3]	719	1			T24	6		T99	34		T226	11
values[4]	655	1			T14	12		T20	13		T97	1
values[5]	2600	1			T12	2		T13	6		T17	2
values[6]	563	1			T20	10		T91	15		T100	14
values[7]	610	1			T21	2		T155	1		T214	1
values[8]	658	1			T19	27		T24	2		T93	23
values[9]	907	1			T19	16		T221	10		T216	24
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	431	1			T99	11		T113	28		T138	24
values[1]	604	1			T99	34		T144	4		T155	5
values[2]	638	1			T24	6		T226	11		T144	3
values[3]	2707	1			T12	2		T13	6		T14	12
values[4]	551	1			T97	1		T34	2		T121	1
values[5]	513	1			T20	10		T21	1		T100	14
values[6]	550	1			T21	1		T214	1		T112	25
values[7]	761	1			T19	27		T24	2		T93	23
values[8]	816	1			T19	16		T117	14		T216	24
values[9]	92	1			T35	8		T102	10		T109	5
minimum	17356	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T99	5		T247	3		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T113	13		T138	12		T111	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T99	16		T144	1		T155	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T92	1		T102	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T24	5		T226	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T242	9		T48	1		T126	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T12	2		T13	6		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	1		T97	1		T34	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	1		T121	1		T91	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T97	1		T100	8		T111	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T21	1		T100	4		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	8		T111	10		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T214	1		T113	7		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T21	1		T112	12		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T221	10		T178	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T19	14		T24	2		T93	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T19	5		T118	1		T217	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T117	1		T216	11		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T35	6		T102	1		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T109	3		T166	6		T222	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17045	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T21	1		T99	1		T142	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T99	6		T247	10		T331	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T113	15		T138	12		T111	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T99	18		T144	3		T92	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T92	3		T102	2		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T24	1		T226	10		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	1		T126	14		T128	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T104	14		T105	15		T223	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	11		T139	12		T186	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T34	1		T91	5		T101	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T253	7		T246	2		T348	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T100	10		T102	5		T48	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	2		T111	15		T116	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T113	8		T146	14		T116	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T112	13		T179	2		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T186	6		T147	7		T236	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T19	13		T93	12		T34	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T19	11		T118	3		T217	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T117	13		T216	13		T253	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T35	2		T102	9		T274	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T109	2		T166	2		T222	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T112	10		T161	9		T300	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T35	6		T217	10		T102	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T117	1		T349	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T290	1		T350	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T112	3		T201	3		T347	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T121	1		T102	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T21	1		T99	1		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T99	5		T144	1		T155	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T92	1		T114	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T24	5		T99	16		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T102	1		T242	9		T146	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T20	13		T108	1		T103	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	1		T97	1		T34	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T12	2		T13	6		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T97	1		T98	11		T100	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T91	10		T100	4		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	8		T111	16		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T21	1		T155	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T21	1		T112	12		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T178	1		T125	1		T186	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T19	14		T24	2		T93	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T19	5		T221	10		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T216	11		T109	3		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T35	2		T217	8		T102	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T117	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T112	10		T201	2		T161	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T102	16		T138	9		T147	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T113	15		T138	12		T128	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T99	6		T144	3		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T92	3		T111	5		T186	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	1		T99	18		T226	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T102	2		T146	12		T186	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T103	9		T260	5		T282	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	11		T139	12		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T104	14		T105	15		T223	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T246	2		T348	4		T291	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T91	5		T100	10		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T20	2		T111	15		T253	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T113	8		T146	14		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T112	13		T198	7		T116	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T186	6		T147	7		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T19	13		T93	12		T34	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T19	11		T118	3		T113	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T216	13		T109	2		T166	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T99	7		T247	11		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T113	16		T138	13		T111	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T99	19		T144	4		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T92	4		T102	3		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T24	4		T226	11		T144	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T242	1		T48	2		T126	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T12	2		T13	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	12		T97	1		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	2		T121	1		T91	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T97	1		T100	1		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T21	1		T100	11		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T20	3		T111	16		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T214	1		T113	9		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T21	1		T112	14		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T221	1		T178	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T19	14		T24	2		T93	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T19	12		T118	4		T217	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T117	14		T216	14		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T35	6		T102	10		T274	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T109	3		T166	6		T222	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17241	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T21	1		T99	1		T142	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T99	4		T247	2		T292	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T113	12		T138	11		T111	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T99	15		T155	4		T125	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T146	2		T186	3		T115	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T24	2		T140	2		T218	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T242	8		T126	14		T128	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T13	5		T20	12		T22	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	8		T98	10		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T91	5		T256	9		T181	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T100	7		T111	5		T348	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T100	3		T102	5		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T20	7		T111	9		T243	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T113	6		T146	13		T116	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T112	11		T198	2		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T221	9		T110	14		T186	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	13		T93	10		T34	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	4		T217	9		T113	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T216	10		T305	5		T272	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T35	2		T249	1		T288	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T109	2		T166	2		T222	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T289	13		T316	11		T347	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T142	2		T112	2		T220	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T35	6		T217	9		T102	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T117	14		T349	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T290	1		T350	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T112	11		T201	3		T347	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T121	1		T102	17		T138	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T21	1		T99	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T99	7		T144	4		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T92	4		T114	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T24	4		T99	19		T226	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T102	3		T242	1		T146	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	1		T108	1		T103	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	12		T97	1		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T12	2		T13	1		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T97	1		T98	1		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T91	10		T100	11		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	3		T111	17		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T21	1		T155	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T21	1		T112	14		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T178	1		T125	1		T186	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T19	14		T24	2		T93	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T19	12		T221	1		T118	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T216	14		T109	3		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T35	2		T217	9		T110	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T112	2		T201	2		T161	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T147	9		T247	2		T289	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T142	2		T113	12		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T99	4		T155	4		T125	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T111	13		T186	3		T219	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T24	2		T99	15		T140	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T242	8		T146	2		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T20	12		T103	10		T220	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T34	8		T139	11		T272	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T13	5		T22	12		T23	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T98	10		T100	7		T348	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T91	5		T100	3		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T20	7		T111	14		T243	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T113	6		T146	13		T116	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T112	11		T198	2		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T186	5		T237	9		T255	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T19	13		T93	10		T34	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T19	4		T221	9		T113	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T216	10		T109	2		T166	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19