Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22032

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2987

1

T19

43

T20

10

T21

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19658

1

T6

2

T26

1

T41

1

auto[1]

5361

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	256	1			T99	34		T101	5		T92	7
values[0]	29	1			T186	28		T300	1		-	-
values[1]	491	1			T21	1		T34	2		T118	14
values[2]	617	1			T21	2		T24	2		T121	1
values[3]	477	1			T97	2		T214	1		T113	17
values[4]	464	1			T20	13		T121	1		T100	8
values[5]	2796	1			T12	2		T13	6		T17	2
values[6]	571	1			T117	14		T217	18		T112	13
values[7]	538	1			T34	11		T118	4		T102	10
values[8]	449	1			T14	12		T98	11		T99	11
values[9]	1180	1			T19	43		T20	10		T93	23
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	546	1			T21	1		T92	4		T102	3
values[1]	471	1			T21	2		T24	2		T97	1
values[2]	570	1			T97	1		T214	1		T113	17
values[3]	2669	1			T12	2		T13	6		T17	2
values[4]	597	1			T24	6		T97	1		T117	14
values[5]	535	1			T217	18		T102	10		T112	13
values[6]	548	1			T34	11		T118	4		T114	1
values[7]	631	1			T14	12		T19	27		T20	10
values[8]	1044	1			T19	16		T93	23		T34	9
values[9]	84	1			T226	11		T92	7		T147	1
minimum	17324	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T92	1		T146	3		T219	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T21	1		T102	1		T112	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T97	1		T121	1		T178	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T21	2		T24	2		T111	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T214	1		T113	13		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T97	1		T109	3		T286	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T12	2		T13	6		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T121	1		T96	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T24	5		T97	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T35	6		T144	1		T113	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T217	10		T102	1		T112	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T138	1		T186	4		T231	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T118	1		T119	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T34	9		T114	1		T111	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	1		T98	11		T99	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T19	14		T20	8		T242	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T93	11		T34	9		T91	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T19	5		T100	4		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T226	1		T322	1		T349	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T92	1		T147	1		T328	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17025	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T34	1		T118	1		T155	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T92	3		T146	12		T219	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T102	2		T112	13		T138	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T139	12		T247	1		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T218	6		T129	8		T285	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T113	4		T48	3		T111	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T109	2		T147	8		T317	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T104	14		T105	15		T223	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T129	8		T50	2		T274	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T24	1		T117	13		T138	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	2		T144	2		T113	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T217	8		T102	9		T112	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T138	9		T186	7		T228	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T118	3		T198	7		T187	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	2		T111	15		T186	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	11		T99	6		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T19	13		T20	2		T186	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T93	12		T91	5		T99	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T19	11		T100	10		T101	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T226	10		T326	11		T327	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T92	6		T351	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T34	1		T118	13		T186	21

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T99	16		T102	6		T179	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T101	1		T92	1		T110	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T300	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T186	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T92	1		T233	13		T224	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T21	1		T34	1		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T121	1		T178	2		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T21	2		T24	2		T111	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T97	1		T214	1		T113	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T97	1		T286	11		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T20	13		T100	8		T216	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T121	1		T155	1		T109	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T12	2		T13	6		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	6		T96	1		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T117	1		T217	10		T112	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T114	1		T138	1		T186	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T118	1		T102	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T34	9		T111	10		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	1		T98	11		T99	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T242	9		T110	7		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T93	11		T34	9		T91	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T19	19		T20	8		T100	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T99	18		T102	5		T179	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T101	4		T92	6		T352	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T186	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T92	3		T233	12		T224	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T34	1		T118	13		T102	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T139	12		T146	12		T219	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T116	13		T218	6		T129	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T113	4		T48	3		T275	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T147	8		T227	1		T247	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T216	13		T144	3		T109	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T109	2		T317	2		T274	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T24	1		T104	14		T105	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	2		T144	2		T113	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T117	13		T217	8		T112	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T138	9		T186	7		T302	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T118	3		T102	9		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	2		T111	15		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	11		T99	6		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T186	6		T265	10		T147	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T93	12		T91	5		T226	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T19	24		T20	2		T100	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T92	4		T146	13		T219	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T21	1		T102	3		T112	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T97	1		T121	1		T178	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T21	2		T24	2		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T214	1		T113	5		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T97	1		T109	3		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T12	2		T13	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T121	1		T96	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T24	4		T97	1		T117	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T35	6		T144	3		T113	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T217	9		T102	10		T112	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T138	10		T186	8		T231	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T118	4		T119	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T34	3		T114	1		T111	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	12		T98	1		T99	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	14		T20	3		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T93	13		T34	1		T91	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T19	12		T100	11		T101	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T226	11		T322	1		T349	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T92	7		T147	1		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17171	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T34	2		T118	14		T155	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T146	2		T219	11		T272	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T112	11		T138	11		T139	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T139	11		T277	3		T291	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T111	5		T218	7		T280	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T113	12		T48	3		T111	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T109	2		T286	10		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T13	5		T20	12		T22	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T301	3		T305	5		T261	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T24	2		T221	9		T285	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T35	2		T113	6		T140	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T217	9		T112	2		T113	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T186	3		T240	8		T310	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T198	2		T187	2		T243	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T34	8		T111	9		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T98	10		T99	4		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T19	13		T20	7		T242	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T93	10		T34	8		T91	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T19	4		T100	3		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T326	2		T327	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T328	2		T353	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T233	12		T224	10		T133	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T155	4		T186	17		T337	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T99	19		T102	6		T179	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T101	5		T92	7		T110	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T300	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T186	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T92	4		T233	13		T224	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T21	1		T34	2		T118	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T121	1		T178	2		T139	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T21	2		T24	2		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T97	1		T214	1		T113	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T97	1		T286	1		T147	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T20	1		T100	1		T216	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T121	1		T155	1		T109	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T12	2		T13	1		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T35	6		T96	1		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T117	14		T217	9		T112	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T114	1		T138	10		T186	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T118	4		T102	10		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	3		T111	16		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	12		T98	1		T99	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T242	1		T110	1		T186	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T93	13		T34	1		T91	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T19	26		T20	3		T100	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T99	15		T102	5		T235	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T110	14		T272	4		T328	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T186	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T233	12		T224	10		T170	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T155	4		T112	11		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T139	11		T146	2		T219	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T111	5		T116	14		T218	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T113	12		T48	3		T261	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T286	10		T147	9		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	12		T100	7		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T109	2		T301	3		T305	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T13	5		T22	12		T23	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T35	2		T113	6		T140	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T217	9		T112	2		T113	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T186	3		T277	2		T318	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T198	2		T243	6		T133	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T34	8		T111	9		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T98	10		T99	4		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T242	8		T110	6		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T93	10		T34	8		T91	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T19	17		T20	7		T100	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19