Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20080

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

4939

1

T12

2

T13

6

T17

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19941

1

T6

2

T26

1

T41

1

auto[1]

5078

1

T12

2

T13

6

T17

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	246	1			T108	1		T118	14		T102	10
values[0]	20	1			T24	6		T214	1		T148	1
values[1]	768	1			T19	27		T20	10		T21	2
values[2]	611	1			T34	2		T109	22		T178	1
values[3]	526	1			T93	23		T34	9		T99	1
values[4]	658	1			T97	1		T121	1		T91	15
values[5]	627	1			T34	11		T142	3		T102	28
values[6]	515	1			T155	1		T142	28		T114	1
values[7]	592	1			T19	16		T21	1		T97	1
values[8]	427	1			T99	34		T216	24		T155	5
values[9]	2878	1			T12	2		T13	6		T14	12
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	860	1			T19	27		T20	10		T21	2
values[1]	2667	1			T12	2		T13	6		T17	2
values[2]	523	1			T93	23		T34	9		T99	1
values[3]	675	1			T97	1		T121	1		T91	15
values[4]	601	1			T34	11		T142	31		T102	11
values[5]	439	1			T155	1		T114	1		T125	1
values[6]	632	1			T19	16		T21	1		T97	1
values[7]	512	1			T221	10		T99	34		T155	5
values[8]	710	1			T14	12		T20	13		T97	1
values[9]	145	1			T121	1		T98	11		T108	1
minimum	17255	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T19	14		T20	8		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T21	1		T24	2		T113	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T109	3		T178	1		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1303	1			T12	2		T13	6		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T93	11		T99	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	9		T144	1		T217	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T121	1		T91	10		T99	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T97	1		T178	1		T125	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	9		T142	3		T102	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T142	13		T114	1		T187	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T110	7		T167	1		T218	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	1		T114	1		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T35	6		T100	8		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	5		T21	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T99	16		T186	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T221	10		T155	5		T103	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	1		T97	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	13		T118	1		T92	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T98	11		T108	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T121	1		T102	1		T48	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17016	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T24	5		T214	1		T276	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T19	13		T20	2		T109	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T113	23		T138	9		T48	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T109	2		T222	9		T198	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1057	1			T104	14		T105	15		T223	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T93	12		T144	2		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T144	3		T217	8		T186	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T91	5		T99	6		T100	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T125	10		T138	12		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T34	2		T102	5		T113	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T142	15		T187	3		T219	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T218	4		T219	14		T224	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T111	5		T50	2		T225	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	2		T216	13		T102	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	11		T117	13		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T99	18		T186	6		T218	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T103	9		T227	1		T228	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	11		T112	23		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T118	13		T92	3		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T138	8		T219	4		T229	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T102	9		T48	2		T267	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T24	1		T276	9		T354	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T108	1		T115	8		T219	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T118	1		T102	1		T48	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T355	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T24	5		T214	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T19	14		T20	8		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T21	1		T24	2		T113	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T109	16		T178	1		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T34	1		T147	1		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T93	11		T99	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T34	9		T118	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T121	1		T91	10		T99	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T97	1		T125	11		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T34	9		T142	3		T102	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T114	1		T178	1		T139	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T167	1		T116	15		T218	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T155	1		T142	13		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	6		T100	8		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	5		T21	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T99	16		T216	11		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T155	5		T103	11		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	1		T97	1		T98	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1373	1			T12	2		T13	6		T17	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T219	4		T316	5		T356	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T118	13		T102	9		T48	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T24	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	13		T20	2		T166	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T113	23		T138	9		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T109	6		T198	7		T169	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T34	1		T147	7		T234	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T93	12		T144	2		T92	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T118	3		T144	3		T217	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T91	5		T99	6		T100	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T125	10		T138	12		T146	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	2		T102	21		T113	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T139	12		T187	3		T219	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T116	13		T218	4		T224	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T142	15		T111	20		T225	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T35	2		T102	2		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	11		T117	13		T226	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T99	18		T216	13		T186	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T103	9		T227	1		T181	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	11		T112	23		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1107	1			T104	14		T105	15		T223	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T19	14		T20	3		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T21	1		T24	2		T113	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T109	3		T178	1		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1380	1			T12	2		T13	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T93	13		T99	1		T144	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T34	1		T144	4		T217	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T121	1		T91	10		T99	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T97	1		T178	1		T125	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	3		T142	1		T102	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T142	16		T114	1		T187	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T110	1		T167	1		T218	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T155	1		T114	1		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T35	6		T100	1		T216	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T19	12		T21	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T99	19		T186	7		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T221	1		T155	1		T103	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	12		T97	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T20	1		T118	14		T92	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T98	1		T108	1		T138	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T121	1		T102	10		T48	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17174	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T24	4		T214	1		T276	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T19	13		T20	7		T109	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T113	18		T146	2		T301	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T109	2		T222	3		T198	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	980	1			T13	5		T22	12		T23	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T93	10		T186	5		T259	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	8		T217	9		T186	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T91	5		T99	4		T100	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T125	10		T138	11		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	8		T142	2		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T142	12		T187	2		T219	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T110	6		T218	1		T219	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T111	18		T237	10		T170	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	2		T100	7		T216	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T19	4		T139	4		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T99	15		T218	7		T128	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T221	9		T155	4		T103	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T112	13		T140	2		T115	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	12		T147	9		T149	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T98	10		T219	11		T264	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T48	3		T240	11		T267	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T149	2		T238	8		T355	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T24	2		T357	6		T354	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T108	1		T115	1		T219	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T118	14		T102	10		T48	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T355	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T24	4		T214	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T19	14		T20	3		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T21	1		T24	2		T113	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T109	8		T178	1		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T34	2		T147	8		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T93	13		T99	1		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	1		T118	4		T144	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T121	1		T91	10		T99	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T97	1		T125	11		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	3		T142	1		T102	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T114	1		T178	1		T139	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T167	1		T116	14		T218	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T155	1		T142	16		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	6		T100	1		T102	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	12		T21	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T99	19		T216	14		T186	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T155	1		T103	10		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T14	12		T97	1		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1452	1			T12	2		T13	1		T17	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T115	7		T219	11		T316	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T48	3		T147	9		T292	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T355	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T24	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T19	13		T20	7		T166	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T113	18		T146	2		T301	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T109	14		T198	2		T169	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T281	10		T240	8		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T93	10		T186	5		T222	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	8		T217	9		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T91	5		T99	4		T100	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T125	10		T138	11		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T34	8		T142	2		T102	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T139	11		T187	2		T219	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T116	14		T218	1		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	12		T111	27		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T35	2		T100	7		T110	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T19	4		T139	4		T186	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T99	15		T216	10		T218	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T155	4		T103	10		T227	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T98	10		T112	13		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1028	1			T13	5		T20	12		T22	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19