Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22209

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2810

1

T20

13

T93

23

T97

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19773

1

T6

2

T26

1

T41

1

auto[1]

5246

1

T12

2

T13

6

T17

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T102	17		T272	13		T220	8
values[0]	39	1			T139	11		T111	19		T258	9
values[1]	495	1			T97	1		T91	15		T100	8
values[2]	793	1			T97	1		T34	2		T35	8
values[3]	549	1			T121	1		T217	18		T103	20
values[4]	712	1			T98	11		T216	24		T118	4
values[5]	492	1			T121	1		T221	10		T99	11
values[6]	610	1			T20	13		T97	1		T34	11
values[7]	377	1			T14	12		T20	10		T21	1
values[8]	539	1			T21	1		T93	23		T117	14
values[9]	3013	1			T12	2		T13	6		T17	2
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	569	1			T97	1		T91	15		T108	1
values[1]	836	1			T97	1		T34	2		T35	8
values[2]	480	1			T121	1		T98	11		T217	18
values[3]	656	1			T96	1		T216	24		T118	18
values[4]	560	1			T97	1		T121	1		T221	10
values[5]	451	1			T20	13		T34	11		T112	25
values[6]	2584	1			T12	2		T13	6		T14	12
values[7]	640	1			T19	16		T21	1		T93	23
values[8]	714	1			T21	1		T24	8		T34	9
values[9]	225	1			T19	27		T102	17		T140	6
minimum	17304	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T97	1		T91	10		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T100	8		T101	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T35	6		T157	1		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T97	1		T34	1		T99	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T217	10		T147	1		T301	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T121	1		T98	11		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T96	1		T118	1		T102	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T216	11		T118	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T221	10		T102	1		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T97	1		T121	1		T99	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T119	1		T166	6		T253	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T20	13		T34	9		T112	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T12	2		T13	6		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T117	1		T144	1		T178	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T19	5		T21	1		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T93	11		T110	7		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T21	1		T24	7		T113	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T34	9		T99	1		T100	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T19	14		T102	1		T140	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T111	6		T317	3		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17035	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T142	3		T219	12		T182	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T91	5		T113	15		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T101	4		T144	3		T142	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T35	2		T139	12		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T34	1		T99	18		T103	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T217	8		T147	7		T260	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T253	7		T341	8		T323	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T118	3		T102	5		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T216	13		T118	13		T102	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T102	2		T138	12		T186	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T99	6		T246	2		T358	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T166	2		T128	6		T348	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	2		T112	13		T111	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T14	11		T20	2		T104	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T117	13		T144	2		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	11		T92	3		T187	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T93	12		T48	1		T236	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T24	1		T113	4		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T100	10		T226	10		T112	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T19	13		T102	16		T140	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T317	2		T342	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T219	4		T331	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T102	1		T272	13		T220	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T246	1		T331	1		T284	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T139	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T111	14		T258	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T97	1		T91	10		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T100	8		T101	1		T142	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T35	6		T108	1		T113	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T97	1		T34	1		T99	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T217	10		T114	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T121	1		T103	11		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T118	1		T114	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T98	11		T216	11		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T221	10		T96	1		T102	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T121	1		T99	5		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T119	1		T125	1		T166	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T20	13		T97	1		T34	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T14	1		T20	8		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T144	1		T178	1		T125	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T21	1		T231	1		T187	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T93	11		T117	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T12	2		T13	6		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T34	9		T99	1		T100	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T102	16		T224	3		T275	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T331	3		T284	1		T347	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T139	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T111	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T91	5		T109	2		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T101	4		T142	15		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T35	2		T113	15		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	1		T99	18		T144	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T217	8		T147	7		T201	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T103	9		T219	14		T247	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T118	3		T198	7		T128	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T216	13		T102	9		T146	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T102	7		T138	12		T186	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T99	6		T118	13		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T166	2		T222	9		T128	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T34	2		T112	13		T126	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T14	11		T20	2		T101	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T144	2		T125	10		T111	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T187	3		T116	13		T276	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T93	12		T117	13		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1153	1			T19	24		T24	1		T104	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T100	10		T226	10		T112	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T97	1		T91	10		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T100	1		T101	5		T144	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	6		T157	1		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T97	1		T34	2		T99	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T217	9		T147	8		T301	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T121	1		T98	1		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T96	1		T118	4		T102	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T216	14		T118	14		T102	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T221	1		T102	3		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T97	1		T121	1		T99	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T119	1		T166	6		T253	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	1		T34	3		T112	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T12	2		T13	1		T14	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T117	14		T144	3		T178	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T19	12		T21	1		T92	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T93	13		T110	1		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T21	1		T24	6		T113	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T34	1		T99	1		T100	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T19	14		T102	17		T140	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T111	1		T317	3		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17206	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T142	1		T219	5		T182	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T91	5		T113	12		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T100	7		T155	4		T142	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T35	2		T139	11		T48	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T99	15		T103	10		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T217	9		T301	3		T280	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T98	10		T277	2		T170	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T102	5		T198	2		T115	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T216	10		T146	2		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T221	9		T138	11		T186	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T99	4		T242	8		T285	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T166	2		T128	5		T220	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T20	12		T34	8		T112	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T13	5		T20	7		T22	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T125	10		T186	5		T243	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T19	4		T187	2		T116	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T93	10		T110	6		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T24	2		T113	12		T286	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T34	8		T100	3		T112	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T19	13		T140	2		T272	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T111	5		T317	2		T149	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T109	2		T139	4		T171	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T142	2		T219	11		T303	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T102	17		T272	1		T220	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T246	1		T331	4		T284	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T139	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T111	6		T258	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T97	1		T91	10		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T100	1		T101	5		T142	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T35	6		T108	1		T113	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T97	1		T34	2		T99	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T217	9		T114	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T121	1		T103	10		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T118	4		T114	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T98	1		T216	14		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T221	1		T96	1		T102	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T121	1		T99	7		T118	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T119	1		T125	1		T166	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	1		T97	1		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	12		T20	3		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T144	3		T178	1		T125	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T21	1		T231	1		T187	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T93	13		T117	14		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T12	2		T13	1		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T34	1		T99	1		T100	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T272	12		T220	7		T224	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T284	1		T347	10		T238	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T139	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T111	13		T258	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T91	5		T109	2		T147	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T100	7		T142	14		T109	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T35	2		T113	12		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T99	15		T155	4		T146	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T217	9		T301	3		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T103	10		T219	13		T261	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T198	2		T128	12		T280	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T98	10		T216	10		T146	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T221	9		T102	5		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T99	4		T285	1		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T166	2		T222	3		T128	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T20	12		T34	8		T112	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T20	7		T227	1		T228	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T125	10		T111	9		T186	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T187	2		T116	14		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T93	10		T110	6		T218	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T13	5		T19	17		T22	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T34	8		T100	3		T112	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19