Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22135

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2884

1

T20

23

T21

3

T34

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20034

1

T6

2

T26

1

T41

1

auto[1]

4985

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T97	1		T35	8		T112	25
values[0]	80	1			T138	10		T285	48		T277	3
values[1]	464	1			T97	1		T99	1		T101	4
values[2]	590	1			T14	12		T20	13		T21	1
values[3]	571	1			T21	1		T97	1		T117	14
values[4]	638	1			T21	1		T221	10		T101	5
values[5]	768	1			T99	34		T96	1		T100	8
values[6]	437	1			T108	1		T113	28		T109	5
values[7]	525	1			T19	27		T34	9		T155	1
values[8]	2693	1			T12	2		T13	6		T17	2
values[9]	859	1			T19	16		T20	10		T34	11
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	456	1			T21	1		T97	1		T101	4
values[1]	554	1			T14	12		T20	13		T21	1
values[2]	634	1			T121	1		T117	14		T221	10
values[3]	521	1			T21	1		T217	18		T113	17
values[4]	744	1			T99	34		T96	1		T100	8
values[5]	539	1			T19	27		T108	1		T113	28
values[6]	2636	1			T12	2		T13	6		T17	2
values[7]	620	1			T24	2		T93	23		T99	11
values[8]	761	1			T19	16		T20	10		T97	1
values[9]	136	1			T91	15		T35	8		T145	1
minimum	17418	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T97	1		T101	1		T178	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	1		T118	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	1		T24	5		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T20	13		T21	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T92	1		T103	11		T48	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T121	1		T117	1		T221	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T109	13		T157	1		T139	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T21	1		T217	10		T113	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T100	8		T109	3		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T99	16		T96	1		T216	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T19	14		T108	1		T111	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T113	13		T186	6		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T12	2		T13	6		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T34	9		T92	1		T186	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T24	2		T93	11		T99	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T144	2		T102	1		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T19	5		T97	1		T34	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	8		T98	11		T142	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T91	10		T35	6		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T145	1		T115	8		T236	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17078	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T138	1		T277	3		T303	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T101	3		T218	6		T260	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T118	13		T48	1		T253	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	11		T24	1		T118	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T116	13		T128	9		T247	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T92	6		T103	9		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T117	13		T226	10		T101	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T109	4		T139	6		T129	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T217	8		T113	4		T166	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T109	2		T139	12		T186	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T99	18		T216	13		T102	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	13		T111	15		T179	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T113	15		T186	6		T187	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T104	14		T105	15		T223	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T92	3		T186	15		T222	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T93	12		T99	6		T100	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T144	5		T102	9		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T19	11		T34	2		T113	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T20	2		T112	13		T186	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T91	5		T35	2		T291	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T236	10		T246	2		T296	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T138	9		T300	2		T283	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T97	1		T35	6		T158	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T112	12		T145	1		T167	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T285	23		T284	3		T302	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T138	1		T277	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T97	1		T99	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T245	4		T289	6		T359	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	1		T24	5		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	13		T21	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T97	1		T142	13		T92	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T21	1		T117	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T109	13		T157	1		T139	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T21	1		T221	10		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T100	8		T139	12		T110	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T99	16		T96	1		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T108	1		T109	3		T111	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T113	13		T231	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T19	14		T155	1		T102	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T34	9		T186	6		T222	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T12	2		T13	6		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T144	2		T92	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T19	5		T34	9		T91	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	8		T98	11		T142	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T35	2		T169	1		T234	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T112	13		T198	7		T236	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T285	25		T284	1		T302	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T138	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T101	3		T111	5		T218	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T289	6		T300	2		T283	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T14	11		T24	1		T118	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T118	13		T48	1		T116	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T142	15		T92	6		T103	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T117	13		T226	10		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T109	4		T139	6		T129	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T101	4		T217	8		T102	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T139	12		T186	7		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T99	18		T216	13		T102	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T109	2		T111	15		T179	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T113	15		T218	4		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T19	13		T102	5		T116	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T186	6		T222	9		T187	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T93	12		T104	14		T105	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T144	5		T92	3		T186	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T19	11		T34	2		T91	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T20	2		T102	9		T186	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T97	1		T101	4		T178	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T21	1		T118	14		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	12		T24	4		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T20	1		T21	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T92	7		T103	10		T48	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T121	1		T117	14		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T109	5		T157	1		T139	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T21	1		T217	9		T113	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T100	1		T109	3		T139	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T99	19		T96	1		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T19	14		T108	1		T111	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T113	16		T186	7		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T12	2		T13	1		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T34	1		T92	4		T186	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T24	2		T93	13		T99	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T144	7		T102	10		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T19	12		T97	1		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T20	3		T98	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T91	10		T35	6		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T145	1		T115	1		T236	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17246	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T138	10		T277	1		T303	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T301	3		T218	7		T260	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T110	14		T289	5		T336	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T24	2		T142	12		T112	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T20	12		T116	14		T286	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T103	10		T48	3		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T221	9		T146	13		T289	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T109	12		T139	4		T110	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T217	9		T113	12		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T100	7		T109	2		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T99	15		T216	10		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T19	13		T111	9		T243	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T113	12		T186	5		T187	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T13	5		T22	12		T23	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T34	8		T186	12		T222	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T93	10		T99	4		T100	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T111	5		T186	1		T317	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	4		T34	8		T113	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T20	7		T98	10		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T91	5		T35	2		T244	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T115	7		T236	11		T149	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T111	13		T128	5		T285	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T277	2		T303	13		T283	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T97	1		T35	6		T158	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T112	14		T145	1		T167	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T285	31		T284	3		T302	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T138	10		T277	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T97	1		T99	1		T101	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T245	4		T289	7		T359	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	12		T24	4		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T20	1		T21	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T97	1		T142	16		T92	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	1		T117	14		T226	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T109	5		T157	1		T139	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T21	1		T221	1		T101	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T100	1		T139	13		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T99	19		T96	1		T216	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T108	1		T109	3		T111	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T113	16		T231	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	14		T155	1		T102	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	1		T186	7		T222	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T12	2		T13	1		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T144	7		T92	4		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T19	12		T34	3		T91	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T20	3		T98	1		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T35	2		T169	1		T291	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T112	11		T198	2		T236	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T285	17		T284	1		T302	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T277	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T111	13		T301	3		T218	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T289	5		T303	13		T283	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T24	2		T112	2		T261	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T20	12		T110	14		T116	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T142	12		T103	10		T48	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T247	10		T289	13		T281	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T109	12		T139	4		T256	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T221	9		T217	9		T113	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T100	7		T139	11		T110	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T99	15		T216	10		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T109	2		T111	9		T243	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T113	12		T218	1		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T19	13		T102	5		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T34	8		T186	5		T222	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T13	5		T22	12		T23	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T111	5		T186	12		T219	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	4		T34	8		T91	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T20	7		T98	10		T142	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19