Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22111

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2908

1

T14

12

T19

43

T21

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19800

1

T6

2

T26

1

T41

1

auto[1]

5219

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	193	1			T142	28		T231	1		T218	21
values[0]	59	1			T243	18		T160	5		T250	9
values[1]	446	1			T20	13		T91	15		T96	1
values[2]	609	1			T19	16		T24	6		T93	23
values[3]	675	1			T24	2		T99	1		T108	1
values[4]	2651	1			T12	2		T13	6		T14	12
values[5]	518	1			T19	27		T97	1		T34	9
values[6]	719	1			T35	8		T216	24		T155	1
values[7]	607	1			T97	1		T99	11		T118	4
values[8]	563	1			T144	3		T214	1		T157	1
values[9]	828	1			T21	2		T34	11		T121	1
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	555	1			T20	13		T34	2		T91	15
values[1]	553	1			T19	16		T24	8		T93	23
values[2]	729	1			T14	12		T108	1		T118	14
values[3]	2613	1			T12	2		T13	6		T17	2
values[4]	545	1			T19	27		T97	1		T35	8
values[5]	683	1			T216	24		T102	28		T109	17
values[6]	574	1			T97	1		T99	11		T118	4
values[7]	776	1			T144	7		T214	1		T157	1
values[8]	547	1			T21	2		T121	1		T221	10
values[9]	153	1			T34	11		T125	1		T231	1
minimum	17291	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T20	13		T34	1		T91	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T99	16		T100	8		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T24	7		T99	1		T186	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	5		T93	11		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T108	1		T155	5		T217	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	1		T118	1		T103	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T12	2		T13	6		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T21	1		T97	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T97	1		T92	1		T112	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T19	14		T35	6		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T216	11		T102	7		T109	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T138	1		T110	15		T222	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T99	5		T92	1		T113	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T97	1		T118	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T144	2		T214	1		T139	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T157	1		T48	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T21	1		T121	1		T221	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T21	1		T114	1		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T246	1		T360	1		T248	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T34	9		T125	1		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17048	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T138	1		T186	4		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T34	1		T91	5		T102	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T99	18		T186	1		T198	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T24	1		T186	6		T129	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	11		T93	12		T100	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T217	8		T111	5		T179	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	11		T118	13		T103	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T20	2		T104	14		T105	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T117	13		T247	1		T228	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T92	6		T112	10		T113	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T19	13		T35	2		T102	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T216	13		T102	21		T109	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T138	8		T222	9		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T99	6		T92	3		T113	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T118	3		T112	13		T166	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T144	5		T139	12		T146	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	1		T186	6		T116	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T142	15		T186	15		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T138	12		T146	12		T186	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T246	2		T248	12		T361	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T34	2		T236	10		T218	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T138	9		T186	7		T201	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T142	13		T360	1		T343	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T231	1		T218	10		T256	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T243	7		T251	11		T362	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T160	3		T250	9		T252	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	13		T91	10		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T138	1		T140	2		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T24	5		T34	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T19	5		T93	11		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T24	2		T99	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T118	1		T119	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T12	2		T13	6		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	1		T21	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T97	1		T34	9		T112	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	14		T114	1		T242	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T216	11		T92	1		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T35	6		T155	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T99	5		T92	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T97	1		T118	1		T112	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T144	1		T214	1		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T157	1		T158	1		T166	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T21	1		T121	1		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T21	1		T34	9		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T142	15		T363	14		T361	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T218	11		T227	1		T276	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T243	11		T251	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T160	2		T252	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T91	5		T102	2		T109	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T138	9		T186	8		T198	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T24	1		T34	1		T129	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T19	11		T93	12		T99	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T111	5		T179	2		T219	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T118	13		T181	13		T225	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T20	2		T104	14		T105	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	11		T117	13		T253	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T112	10		T113	4		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T19	13		T111	15		T254	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T216	13		T92	6		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T35	2		T102	9		T138	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T99	6		T92	3		T102	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T118	3		T112	13		T116	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T144	2		T51	11		T224	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T166	2		T186	6		T116	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T144	3		T139	12		T146	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T34	2		T138	12		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T20	1		T34	2		T91	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T99	19		T100	1		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T24	6		T99	1		T186	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	12		T93	13		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T108	1		T155	1		T217	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	12		T118	14		T103	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T12	2		T13	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T21	1		T97	1		T117	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T97	1		T92	7		T112	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T19	14		T35	6		T102	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T216	14		T102	23		T109	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T138	9		T110	1		T222	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T99	7		T92	4		T113	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T97	1		T118	4		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T144	7		T214	1		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T157	1		T48	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T21	1		T121	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T21	1		T114	1		T138	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T246	3		T360	1		T248	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T34	3		T125	1		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17198	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T138	10		T186	8		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T20	12		T91	5		T233	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T99	15		T100	7		T186	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T24	2		T115	7		T237	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T19	4		T93	10		T98	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T155	4		T217	9		T111	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T103	10		T181	12		T281	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T13	5		T20	7		T22	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T142	2		T237	10		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T112	2		T113	12		T218	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T19	13		T35	2		T242	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T216	10		T102	5		T109	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T110	14		T222	3		T255	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T99	4		T113	12		T140	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T112	11		T166	2		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T139	11		T111	5		T146	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T186	5		T116	14		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T221	9		T142	12		T110	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T138	11		T146	2		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T257	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T34	8		T236	11		T218	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T109	2		T128	5		T243	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T186	3		T201	2		T328	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T142	16		T360	1		T343	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T231	1		T218	12		T256	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T243	12		T251	3		T362	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T160	3		T250	1		T252	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T20	1		T91	10		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T138	10		T140	2		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T24	4		T34	2		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T19	12		T93	13		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T24	2		T99	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T118	14		T119	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T12	2		T13	1		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	12		T21	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T97	1		T34	1		T112	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T19	14		T114	1		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T216	14		T92	7		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T35	6		T155	1		T102	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T99	7		T92	4		T102	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T97	1		T118	4		T112	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T144	3		T214	1		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T157	1		T158	1		T166	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T21	1		T121	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	1		T34	3		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T142	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T218	9		T256	9		T227	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T243	6		T251	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T160	2		T250	8		T252	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T20	12		T91	5		T109	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T186	4		T198	2		T147	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T24	2		T115	7		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	4		T93	10		T98	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T155	4		T111	13		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T272	12		T181	12		T281	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T13	5		T20	7		T22	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T142	2		T237	10		T260	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T34	8		T112	2		T113	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T19	13		T242	8		T111	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T216	10		T102	5		T109	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T35	2		T110	14		T222	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T99	4		T113	12		T140	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T112	11		T219	13		T247	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T286	10		T272	4		T220	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T166	2		T186	5		T116	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T221	9		T139	11		T110	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	8		T138	11		T146	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19