Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T34	2		T91	10		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T121	1		T99	19		T138	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T20	1		T24	6		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T93	13		T98	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T108	1		T155	1		T217	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	12		T19	12		T21	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T12	2		T13	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T97	1		T117	14		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T97	1		T92	7		T112	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	14		T35	6		T114	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T99	7		T216	14		T102	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T102	10		T138	9		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T92	4		T113	16		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T97	1		T118	4		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T221	1		T144	7		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T21	1		T157	1		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T21	1		T121	1		T142	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T34	3		T114	1		T138	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T245	4		T246	3		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T125	1		T146	13		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17154	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T198	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T91	5		T109	2		T115	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T99	15		T186	4		T187	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T20	12		T24	2		T237	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T93	10		T98	10		T100	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T155	4		T217	9		T111	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T19	4		T100	3		T103	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T13	5		T20	7		T22	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T142	2		T237	10		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T112	2		T113	12		T218	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T19	13		T35	2		T242	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T99	4		T216	10		T102	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T110	14		T222	3		T255	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T113	12		T140	2		T219	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T112	11		T166	2		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T221	9		T139	11		T111	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T186	5		T116	14		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T142	12		T110	6		T186	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T34	8		T138	11		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T148	2		T257	10		T258	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T146	2		T236	11		T218	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T251	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T198	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T96	1		T243	12		T244	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T160	3		T249	2		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T91	10		T102	3		T109	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T99	19		T138	10		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T20	1		T24	4		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T19	12		T93	13		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	2		T99	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T118	14		T119	1		T48	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T12	2		T13	1		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	12		T21	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T97	1		T34	1		T112	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T19	14		T35	6		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T216	14		T92	7		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T155	1		T102	10		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T99	7		T92	4		T102	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T97	1		T118	4		T112	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T144	3		T214	1		T113	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T157	1		T158	1		T166	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T21	1		T121	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T21	1		T34	3		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T243	6		T244	11		T251	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T160	2		T249	1		T250	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T91	5		T109	2		T128	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T99	15		T186	4		T198	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T20	12		T24	2		T115	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T19	4		T93	10		T98	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T155	4		T111	13		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	3		T181	12		T259	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T13	5		T20	7		T22	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T142	2		T237	10		T260	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	8		T112	2		T113	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T19	13		T35	2		T242	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T216	10		T102	5		T109	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T110	14		T222	3		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T99	4		T219	12		T261	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T112	11		T219	13		T247	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T113	12		T140	2		T111	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T166	2		T186	5		T116	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T221	9		T142	12		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T34	8		T138	11		T146	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19