Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22127

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2892

1

T21

1

T24

2

T97

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19839

1

T6

2

T26

1

T41

1

auto[1]

5180

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T253	1		-	-		-	-
values[0]	79	1			T262	1		T263	10		T264	11
values[1]	494	1			T19	27		T20	13		T35	8
values[2]	2717	1			T12	2		T13	6		T17	2
values[3]	663	1			T21	1		T24	2		T97	1
values[4]	602	1			T21	1		T24	6		T121	1
values[5]	641	1			T14	12		T34	2		T117	14
values[6]	493	1			T121	1		T112	25		T157	1
values[7]	607	1			T97	1		T34	11		T100	14
values[8]	628	1			T21	1		T34	9		T99	34
values[9]	943	1			T93	23		T97	1		T221	10
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	730	1			T19	43		T20	13		T35	8
values[1]	2685	1			T12	2		T13	6		T17	2
values[2]	722	1			T21	1		T24	2		T91	15
values[3]	526	1			T21	1		T24	6		T34	2
values[4]	635	1			T14	12		T117	14		T108	1
values[5]	559	1			T121	1		T109	5		T157	1
values[6]	629	1			T97	1		T34	11		T99	34
values[7]	580	1			T21	1		T34	9		T118	4
values[8]	678	1			T93	23		T221	10		T96	1
values[9]	113	1			T97	1		T157	1		T231	1
minimum	17162	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T19	19		T20	13		T113	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	6		T226	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T12	2		T13	6		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T97	1		T265	1		T261	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	1		T100	8		T186	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T24	2		T91	10		T99	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T21	1		T24	5		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T34	1		T121	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	1		T117	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T108	1		T112	12		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T121	1		T157	1		T114	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T109	3		T114	1		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T99	16		T100	4		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T97	1		T34	9		T103	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T125	1		T186	13		T218	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T21	1		T34	9		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T93	11		T96	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T221	10		T101	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T97	1		T157	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T253	1		T266	1		T267	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16989	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T263	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T19	24		T113	8		T111	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T35	2		T226	10		T101	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T20	2		T104	14		T105	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T265	10		T260	5		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T186	7		T198	7		T253	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T91	5		T99	6		T102	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T24	1		T48	1		T181	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	1		T102	16		T186	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	11		T117	13		T118	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T112	13		T138	8		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T139	12		T219	13		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T109	2		T48	2		T169	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T99	18		T100	10		T216	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T34	2		T103	9		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T186	15		T218	11		T268	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T118	3		T92	3		T102	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T93	12		T144	2		T142	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T101	4		T144	3		T186	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T268	7		T269	10		T203	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T267	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T253	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T262	1		T270	4		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T263	10		T264	8		T257	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T19	14		T20	13		T111	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T35	6		T226	1		T140	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T12	2		T13	6		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T99	5		T101	1		T272	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	1		T100	8		T113	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T24	2		T97	1		T91	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	1		T24	5		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T121	1		T113	13		T111	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	1		T117	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T34	1		T108	1		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T121	1		T157	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T112	12		T114	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T100	4		T125	1		T139	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T97	1		T34	9		T109	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T99	16		T216	11		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	1		T34	9		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T93	11		T97	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T221	10		T101	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T264	3		T257	7		T273	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T19	13		T111	15		T146	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	2		T226	10		T140	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T19	11		T20	2		T104	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T99	6		T101	3		T274	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T113	4		T186	7		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T91	5		T102	2		T128	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T24	1		T118	13		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T113	15		T187	3		T236	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	11		T117	13		T116	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T34	1		T102	16		T186	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T219	13		T275	6		T276	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T112	13		T138	8		T48	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T100	10		T139	12		T218	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	2		T109	2		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T99	18		T216	13		T254	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T118	3		T92	3		T102	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T93	12		T144	2		T142	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T101	4		T144	3		T186	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T19	26		T20	1		T113	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T35	6		T226	11		T101	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T12	2		T13	1		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T97	1		T265	11		T261	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	1		T100	1		T186	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T24	2		T91	10		T99	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T21	1		T24	4		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	2		T121	1		T102	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	12		T117	14		T118	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T108	1		T112	14		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T121	1		T157	1		T114	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T109	3		T114	1		T48	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T99	19		T100	11		T216	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T97	1		T34	3		T103	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T125	1		T186	16		T218	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	1		T34	1		T118	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T93	13		T96	1		T144	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T221	1		T101	5		T144	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T97	1		T157	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T253	1		T266	1		T267	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17152	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T263	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T19	17		T20	12		T113	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T35	2		T140	2		T272	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T13	5		T20	7		T22	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T261	10		T170	20		T133	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T100	7		T186	3		T198	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T91	5		T99	4		T142	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T24	2		T181	12		T277	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T237	9		T228	13		T267	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T116	14		T243	6		T220	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T112	11		T237	10		T278	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T242	8		T139	11		T219	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T109	2		T48	3		T169	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T99	15		T100	3		T216	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T34	8		T103	10		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T186	12		T218	9		T279	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T34	8		T112	2		T110	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T93	10		T155	4		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T221	9		T186	1		T280	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T281	10		T203	2		T282	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T267	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T263	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T253	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T262	1		T270	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T263	1		T264	4		T257	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T19	14		T20	1		T111	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T35	6		T226	11		T140	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T12	2		T13	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T99	7		T101	4		T272	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	1		T100	1		T113	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T24	2		T97	1		T91	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	1		T24	4		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T121	1		T113	16		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T14	12		T117	14		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	2		T108	1		T102	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T121	1		T157	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T112	14		T114	1		T138	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T100	11		T125	1		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T97	1		T34	3		T109	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T99	19		T216	14		T254	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	1		T34	1		T118	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T93	13		T97	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T221	1		T101	5		T144	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T270	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T263	9		T264	7		T257	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T19	13		T20	12		T111	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T35	2		T140	2		T272	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T13	5		T19	4		T20	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T99	4		T272	12		T247	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T100	7		T113	12		T186	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T91	5		T142	2		T128	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T24	2		T260	6		T277	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T113	12		T111	5		T187	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T116	14		T243	6		T220	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T278	2		T235	2		T283	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T242	8		T219	12		T284	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T112	11		T48	3		T169	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T100	3		T139	11		T218	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T34	8		T109	2		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T99	15		T216	10		T285	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	8		T103	10		T112	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T93	10		T155	4		T142	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T221	9		T186	1		T286	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19