Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22145

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2874

1

T14

12

T19

27

T20

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19789

1

T6

2

T26

1

T41

1

auto[1]

5230

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T287	10		-	-		-	-
values[0]	83	1			T21	1		T112	13		T254	12
values[1]	477	1			T121	1		T99	1		T142	3
values[2]	486	1			T99	11		T144	7		T155	5
values[3]	670	1			T24	6		T99	34		T226	11
values[4]	726	1			T14	12		T20	13		T97	1
values[5]	2524	1			T12	2		T13	6		T17	2
values[6]	594	1			T20	10		T21	1		T91	15
values[7]	565	1			T21	1		T97	1		T155	1
values[8]	643	1			T19	27		T24	2		T93	23
values[9]	1090	1			T19	16		T117	14		T35	8
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	628	1			T21	1		T121	1		T99	12
values[1]	596	1			T99	34		T144	4		T155	5
values[2]	709	1			T20	13		T24	6		T108	1
values[3]	2630	1			T12	2		T13	6		T14	12
values[4]	570	1			T97	1		T34	2		T121	1
values[5]	525	1			T20	10		T21	1		T100	14
values[6]	527	1			T21	1		T214	1		T112	25
values[7]	763	1			T19	27		T24	2		T93	23
values[8]	745	1			T19	16		T117	14		T216	24
values[9]	150	1			T35	8		T102	10		T109	5
minimum	17176	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T121	1		T99	5		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	1		T99	1		T142	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T99	16		T144	1		T155	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T92	1		T119	1		T158	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T24	5		T108	1		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T20	13		T102	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T12	2		T13	6		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	1		T97	1		T98	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T121	1		T91	10		T101	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T97	1		T34	1		T100	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T100	4		T155	1		T102	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	8		T21	1		T111	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T214	1		T113	7		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T21	1		T112	12		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	2		T221	10		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T19	14		T93	11		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T19	5		T118	1		T217	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T117	1		T216	11		T113	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T35	6		T102	1		T109	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T114	1		T178	1		T222	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17001	1			T15	196		T16	19		T18	186
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T99	6		T102	16		T113	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T112	10		T138	12		T111	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T99	18		T144	3		T92	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T92	3		T146	12		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	1		T226	10		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T102	2		T139	12		T126	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T104	14		T105	15		T223	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	11		T186	15		T275	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T91	5		T101	7		T118	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T34	1		T253	7		T129	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T100	10		T102	5		T186	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	2		T111	15		T116	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T113	8		T48	2		T146	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T112	13		T179	2		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T186	6		T147	7		T236	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T19	13		T93	12		T34	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T19	11		T118	3		T217	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T117	13		T216	13		T113	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T35	2		T102	9		T109	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T222	9		T249	1		T288	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	2		T26	1		T41	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T287	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T289	14		T133	3		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T21	1		T112	3		T254	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T121	1		T102	1		T113	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T99	1		T142	3		T138	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T99	5		T144	2		T155	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T92	1		T102	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	5		T99	16		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T114	1		T242	9		T146	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T34	9		T108	1		T103	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T20	13		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T12	2		T13	6		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T97	1		T34	1		T98	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T91	10		T100	4		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	8		T21	1		T100	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T155	1		T214	1		T113	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T21	1		T97	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T24	2		T178	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	14		T93	11		T34	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T19	5		T35	6		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T117	1		T216	11		T113	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T287	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T289	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T112	10		T254	11		T201	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T102	16		T113	15		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T138	12		T128	1		T284	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T99	6		T144	5		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T92	3		T102	2		T111	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T24	1		T99	18		T226	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T146	12		T186	15		T126	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T103	9		T51	11		T260	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	11		T139	12		T129	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T104	14		T105	15		T223	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T34	1		T278	2		T291	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T91	5		T100	10		T101	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T20	2		T111	15		T253	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T113	8		T146	14		T186	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T198	7		T116	1		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T186	6		T147	7		T255	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T19	13		T93	12		T34	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T19	11		T35	2		T118	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T117	13		T216	13		T113	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T121	1		T99	7		T102	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	1		T99	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T99	19		T144	4		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T92	4		T119	1		T158	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T24	4		T108	1		T226	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T20	1		T102	3		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T12	2		T13	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	12		T97	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T121	1		T91	10		T101	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T97	1		T34	2		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T100	11		T155	1		T102	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T20	3		T21	1		T111	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T214	1		T113	9		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T21	1		T112	14		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	2		T221	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T19	14		T93	13		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T19	12		T118	4		T217	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T117	14		T216	14		T113	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T35	6		T102	10		T109	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T114	1		T178	1		T222	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17164	1			T6	2		T26	1		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T99	4		T113	12		T247	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T142	2		T112	2		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T99	15		T155	4		T125	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T146	2		T286	10		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	2		T140	2		T218	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T20	12		T242	8		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T13	5		T22	12		T23	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T98	10		T186	12		T272	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T91	5		T219	11		T243	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T100	7		T111	5		T256	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T100	3		T102	5		T187	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T20	7		T111	9		T260	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T113	6		T48	3		T146	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T112	11		T198	2		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T221	9		T110	14		T186	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T19	13		T93	10		T34	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T19	4		T217	9		T109	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T216	10		T113	12		T166	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T35	2		T109	2		T218	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T222	3		T249	1		T288	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T292	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T287	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T289	12		T133	1		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T21	1		T112	11		T254	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T121	1		T102	17		T113	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T99	1		T142	1		T138	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T99	7		T144	7		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T92	4		T102	3		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T24	4		T99	19		T226	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T114	1		T242	1		T146	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T34	1		T108	1		T103	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	12		T20	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T12	2		T13	1		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T97	1		T34	2		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T91	10		T100	11		T101	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	3		T21	1		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T155	1		T214	1		T113	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T21	1		T97	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	2		T178	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T19	14		T93	13		T34	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T19	12		T35	6		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T117	14		T216	14		T113	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T287	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T289	13		T133	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T112	2		T201	2		T161	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T113	12		T147	9		T247	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T142	2		T138	11		T220	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T99	4		T155	4		T125	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T111	13		T219	12		T128	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	2		T99	15		T140	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T242	8		T146	2		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	8		T103	10		T291	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T20	12		T139	11		T272	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T13	5		T22	12		T23	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T98	10		T256	9		T280	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T91	5		T100	3		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T20	7		T100	7		T111	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T113	6		T146	13		T116	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T198	2		T255	13		T133	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T186	5		T237	9		T255	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T19	13		T93	10		T34	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T19	4		T35	2		T221	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T216	10		T113	12		T166	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19