Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22129

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2890

1

T19

27

T20

23

T21

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20004

1

T6

2

T26

1

T41

1

auto[1]

5015

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T293	1		T294	1		-	-
values[0]	68	1			T97	1		T128	12		T284	4
values[1]	509	1			T21	1		T99	1		T101	4
values[2]	547	1			T14	12		T20	13		T24	6
values[3]	580	1			T21	2		T97	1		T117	14
values[4]	644	1			T221	10		T101	5		T217	18
values[5]	760	1			T99	34		T96	1		T100	8
values[6]	466	1			T34	9		T108	1		T113	28
values[7]	512	1			T19	27		T155	1		T102	11
values[8]	2738	1			T12	2		T13	6		T17	2
values[9]	1042	1			T19	16		T20	10		T97	1
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	715	1			T21	1		T97	1		T99	1
values[1]	549	1			T14	12		T20	13		T21	1
values[2]	629	1			T117	14		T226	11		T101	5
values[3]	553	1			T21	1		T221	10		T217	18
values[4]	698	1			T99	34		T96	1		T100	8
values[5]	523	1			T108	1		T113	28		T109	5
values[6]	2691	1			T12	2		T13	6		T17	2
values[7]	620	1			T19	16		T24	2		T99	11
values[8]	725	1			T20	10		T93	23		T97	1
values[9]	155	1			T91	15		T35	8		T145	1
minimum	17161	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T97	1		T99	1		T101	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T21	1		T118	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T24	5		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T20	13		T21	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T92	1		T103	11		T48	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T117	1		T226	1		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T109	13		T139	5		T110	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	1		T221	10		T217	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T100	8		T157	1		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T99	16		T96	1		T216	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T108	1		T109	3		T111	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T113	13		T186	6		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T12	2		T13	6		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	14		T34	9		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T19	5		T24	2		T99	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T144	1		T102	1		T111	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T93	11		T97	1		T34	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	8		T98	11		T142	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T91	10		T35	6		T244	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T145	1		T231	1		T115	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T138	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T101	3		T111	5		T218	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T118	13		T253	6		T289	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	11		T24	1		T118	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	1		T116	13		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T92	6		T103	9		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T117	13		T226	10		T101	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T109	4		T139	6		T295	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T217	8		T113	4		T166	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T139	12		T186	7		T130	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T99	18		T216	13		T102	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T109	2		T111	15		T179	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T113	15		T186	6		T187	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T104	14		T105	15		T223	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	13		T92	3		T186	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T19	11		T99	6		T100	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T144	3		T102	9		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T93	12		T34	2		T169	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T20	2		T112	13		T113	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T91	5		T35	2		T279	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T246	2		T296	2		T160	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T138	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T293	1		T294	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T97	1		T128	6		T284	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T297	4		T263	13		T298	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T99	1		T101	1		T178	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T21	1		T138	1		T245	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	1		T24	5		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T20	13		T121	1		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T97	1		T142	13		T92	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T21	2		T117	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T157	1		T139	5		T256	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T221	10		T101	1		T217	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T100	8		T109	13		T139	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T99	16		T96	1		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T108	1		T109	3		T111	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T34	9		T113	13		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T155	1		T102	6		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	14		T186	6		T187	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T12	2		T13	6		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T144	1		T92	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T19	5		T97	1		T34	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T20	8		T98	11		T142	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T128	6		T284	1		T299	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T298	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T101	3		T111	5		T218	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T138	9		T289	6		T300	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T14	11		T24	1		T118	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T118	13		T48	1		T116	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T142	15		T92	6		T103	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T117	13		T226	10		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T139	6		T129	8		T255	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T101	4		T217	8		T102	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T109	4		T139	12		T186	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T99	18		T216	13		T102	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T109	2		T111	15		T179	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T113	15		T218	4		T275	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T102	5		T116	1		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T19	13		T186	6		T187	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T93	12		T104	14		T105	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T144	3		T92	3		T186	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T19	11		T34	2		T91	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T20	2		T102	9		T112	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T97	1		T99	1		T101	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	1		T118	14		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	12		T24	4		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T20	1		T21	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T92	7		T103	10		T48	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T117	14		T226	11		T101	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T109	5		T139	7		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T21	1		T221	1		T217	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T100	1		T157	1		T139	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T99	19		T96	1		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T108	1		T109	3		T111	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T113	16		T186	7		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T12	2		T13	1		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	14		T34	1		T92	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T19	12		T24	2		T99	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T144	4		T102	10		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T93	13		T97	1		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	3		T98	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T91	10		T35	6		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T145	1		T231	1		T115	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T138	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T111	13		T301	3		T218	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T110	14		T289	5		T277	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T24	2		T142	12		T112	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T20	12		T116	14		T128	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T103	10		T48	3		T247	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T146	13		T286	10		T289	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T109	12		T139	4		T110	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T221	9		T217	9		T113	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T100	7		T139	11		T186	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T99	15		T216	10		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T109	2		T111	9		T243	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T113	12		T186	5		T187	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T13	5		T22	12		T23	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T19	13		T34	8		T186	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	4		T99	4		T100	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T111	5		T186	1		T228	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T93	10		T34	8		T169	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T20	7		T98	10		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T91	5		T35	2		T244	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T115	7		T149	2		T296	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T293	1		T294	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T97	1		T128	7		T284	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T297	1		T263	1		T298	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T99	1		T101	4		T178	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T21	1		T138	10		T245	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	12		T24	4		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	1		T121	1		T118	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T97	1		T142	16		T92	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	2		T117	14		T226	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T157	1		T139	7		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T221	1		T101	5		T217	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T100	1		T109	5		T139	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T99	19		T96	1		T216	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T108	1		T109	3		T111	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	1		T113	16		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T155	1		T102	6		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T19	14		T186	7		T187	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T12	2		T13	1		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T144	4		T92	4		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T19	12		T97	1		T34	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T20	3		T98	1		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T128	5		T284	1		T302	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T297	3		T263	12		T298	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T111	13		T301	3		T218	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T289	5		T277	2		T303	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T24	2		T261	4		T304	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T20	12		T110	14		T116	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T142	12		T103	10		T112	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T247	10		T289	13		T281	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T139	4		T256	9		T280	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T221	9		T217	9		T113	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T100	7		T109	12		T139	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T99	15		T216	10		T242	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T109	2		T111	9		T243	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T34	8		T113	12		T218	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T102	5		T219	13		T305	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T19	13		T186	5		T187	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T13	5		T22	12		T23	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T111	5		T186	12		T222	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T19	4		T34	8		T91	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T20	7		T98	10		T142	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19