Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22072

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2947

1

T14

12

T20

23

T21

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19371

1

T6

2

T26

1

T41

1

auto[1]

5648

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	426	1			T15	4		T18	6		T24	3
values[0]	80	1			T216	24		T118	14		T169	3
values[1]	744	1			T20	13		T21	1		T24	2
values[2]	2844	1			T12	2		T13	6		T17	2
values[3]	500	1			T155	1		T103	20		T157	1
values[4]	723	1			T14	12		T97	2		T99	1
values[5]	539	1			T19	16		T34	9		T101	5
values[6]	450	1			T19	27		T99	34		T118	4
values[7]	389	1			T34	2		T121	1		T91	15
values[8]	444	1			T24	6		T114	1		T178	1
values[9]	1143	1			T20	10		T21	1		T34	11
minimum	16737	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1007	1			T20	13		T21	1		T24	2
values[1]	2718	1			T12	2		T13	6		T17	2
values[2]	540	1			T100	14		T101	4		T142	28
values[3]	652	1			T14	12		T97	2		T99	1
values[4]	514	1			T19	43		T34	9		T101	5
values[5]	453	1			T34	2		T118	4		T92	4
values[6]	482	1			T121	1		T91	15		T99	34
values[7]	448	1			T24	6		T117	14		T99	11
values[8]	803	1			T20	10		T21	1		T34	11
values[9]	232	1			T100	8		T113	17		T232	1
minimum	17170	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T24	2		T121	1		T155	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T20	13		T21	1		T98	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T12	2		T13	6		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T21	1		T97	1		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T100	4		T142	13		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T101	1		T103	11		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T97	1		T99	1		T112	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	1		T97	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T19	19		T34	9		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T214	1		T102	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	1		T118	1		T92	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T138	12		T110	7		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T91	10		T102	6		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T121	1		T99	16		T242	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T117	1		T178	1		T139	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T24	5		T99	5		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T34	9		T226	1		T102	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T20	8		T21	1		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T100	8		T260	1		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T113	13		T232	1		T307	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16990	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T284	2		T308	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T112	10		T186	7		T236	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T216	13		T118	13		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T93	12		T104	14		T105	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T35	2		T139	12		T111	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T100	10		T142	15		T116	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T101	3		T103	9		T138	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T112	13		T125	10		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	11		T102	2		T113	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T19	24		T101	4		T92	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T102	9		T198	7		T129	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	1		T118	3		T92	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T138	12		T218	4		T219	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T91	5		T102	5		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T99	18		T234	3		T309	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T117	13		T139	6		T166	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T24	1		T99	6		T228	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T34	2		T226	10		T102	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T20	2		T109	4		T186	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T260	5		T292	9		T310	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T113	4		T307	11		T311	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T284	3		T308	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T15	4		T18	6		T24	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T238	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T312	1		T313	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T216	11		T118	1		T169	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T24	2		T125	1		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T20	13		T21	1		T98	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T12	2		T13	6		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T21	1		T97	1		T35	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T155	1		T146	14		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T103	11		T157	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T97	1		T99	1		T100	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	1		T97	1		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T19	5		T34	9		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T214	1		T102	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T19	14		T118	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T99	16		T119	1		T138	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	1		T91	10		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T121	1		T242	9		T218	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T178	1		T138	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	5		T114	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T34	9		T117	1		T100	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T20	8		T21	1		T221	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16574	1			T15	192		T16	19		T18	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T314	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T313	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T216	13		T118	13		T169	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T274	8		T315	6		T316	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T144	5		T109	2		T140	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T93	12		T104	14		T105	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T35	2		T139	12		T111	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	14		T116	1		T147	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T103	9		T138	9		T50	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T100	10		T142	15		T112	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	11		T101	3		T102	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T19	11		T101	4		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T102	9		T147	7		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T19	13		T118	3		T317	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T99	18		T138	12		T219	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	1		T91	5		T92	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T218	4		T234	3		T269	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T138	8		T166	2		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T24	1		T255	14		T309	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T34	2		T117	13		T226	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T20	2		T99	6		T113	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T24	2		T121	1		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T20	1		T21	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T12	2		T13	1		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T21	1		T97	1		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T100	11		T142	16		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T101	4		T103	10		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T97	1		T99	1		T112	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	12		T97	1		T102	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T19	26		T34	1		T101	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T214	1		T102	10		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T34	2		T118	4		T92	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T138	13		T110	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T91	10		T102	6		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T121	1		T99	19		T242	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T117	14		T178	1		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	4		T99	7		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T34	3		T226	11		T102	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T20	3		T21	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T100	1		T260	6		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T113	5		T232	1		T307	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17153	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T284	5		T308	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T155	4		T112	2		T186	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T20	12		T98	10		T216	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T13	5		T22	12		T23	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	2		T139	11		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T100	3		T142	12		T147	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T103	10		T146	2		T128	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T112	11		T125	10		T186	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T113	12		T222	3		T115	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T19	17		T34	8		T272	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T198	2		T281	10		T277	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T219	12		T317	2		T220	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T138	11		T110	6		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T91	5		T102	5		T130	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T99	15		T242	8		T309	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T139	4		T166	2		T186	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T24	2		T99	4		T111	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	8		T113	6		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	7		T221	9		T109	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T100	7		T292	7		T303	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T113	12		T297	3		T311	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	425	1			T15	4		T18	6		T24	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T238	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T312	1		T313	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T216	14		T118	14		T169	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T24	2		T125	1		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T20	1		T21	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T12	2		T13	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T21	1		T97	1		T35	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T155	1		T146	15		T116	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T103	10		T157	1		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T97	1		T99	1		T100	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	12		T97	1		T101	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	12		T34	1		T101	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T214	1		T102	10		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T19	14		T118	4		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T99	19		T119	1		T138	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T34	2		T91	10		T92	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T121	1		T242	1		T218	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T178	1		T138	9		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T24	4		T114	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T34	3		T117	14		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T20	3		T21	1		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16737	1			T6	2		T26	1		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T216	10		T169	1		T318	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T220	7		T315	12		T316	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	12		T98	10		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T13	5		T22	12		T23	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	2		T139	11		T111	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T146	13		T147	9		T218	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T103	10		T305	5		T181	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T100	3		T142	12		T112	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T113	12		T146	2		T222	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T19	4		T34	8		T187	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T110	6		T281	10		T277	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T19	13		T317	2		T272	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T99	15		T138	11		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T91	5		T102	5		T219	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T242	8		T218	1		T319	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T166	2		T186	1		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T24	2		T111	5		T286	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T34	8		T100	7		T113	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T20	7		T221	9		T99	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19