Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22021

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2998

1

T14

12

T19

16

T20

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19434

1

T6

2

T26

1

T41

1

auto[1]

5585

1

T12

2

T13

6

T14

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	693	1			T15	4		T18	6		T21	1
values[0]	17	1			T118	14		T245	2		T312	1
values[1]	839	1			T20	13		T21	1		T98	11
values[2]	2783	1			T12	2		T13	6		T17	2
values[3]	496	1			T155	1		T142	28		T103	20
values[4]	720	1			T14	12		T97	2		T99	1
values[5]	542	1			T19	43		T34	9		T101	5
values[6]	447	1			T118	4		T119	1		T138	24
values[7]	471	1			T34	2		T121	1		T91	15
values[8]	411	1			T24	6		T99	11		T114	1
values[9]	863	1			T20	10		T117	14		T96	1
minimum	16737	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	827	1			T20	13		T21	1		T24	2
values[1]	2707	1			T12	2		T13	6		T17	2
values[2]	582	1			T100	14		T155	1		T142	28
values[3]	608	1			T14	12		T97	2		T99	1
values[4]	539	1			T19	43		T34	9		T101	5
values[5]	467	1			T34	2		T92	4		T138	24
values[6]	455	1			T121	1		T91	15		T99	34
values[7]	448	1			T24	6		T117	14		T99	11
values[8]	823	1			T20	10		T21	1		T34	11
values[9]	204	1			T113	17		T260	6		T306	1
minimum	17359	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	1		T24	2		T121	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T20	13		T144	1		T155	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T12	2		T13	6		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T21	1		T93	11		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T100	4		T155	1		T142	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T103	11		T157	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T97	2		T99	1		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	1		T102	1		T113	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T19	14		T34	9		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	5		T118	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T34	1		T92	1		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T110	7		T127	1		T219	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T91	10		T99	16		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T121	1		T242	9		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T24	5		T117	1		T99	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T114	1		T178	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T20	8		T34	9		T100	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T21	1		T221	10		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T260	1		T306	1		T292	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T113	13		T238	1		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17040	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T118	1		T265	1		T256	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T216	13		T144	3		T112	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T144	2		T109	2		T140	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T104	14		T105	15		T223	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T93	12		T35	2		T217	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T100	10		T142	15		T116	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T103	9		T138	9		T146	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T101	3		T112	13		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	11		T102	2		T113	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T19	13		T101	4		T92	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	11		T118	3		T102	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T34	1		T92	3		T138	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T219	4		T234	3		T284	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T91	5		T99	18		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T247	10		T309	2		T331	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T24	1		T117	13		T99	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T166	2		T233	12		T228	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	2		T34	2		T226	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T102	16		T109	4		T186	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T260	5		T292	9		T310	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T113	4		T311	13		T332	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T118	13		T265	10		T331	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	499	1			T15	4		T18	6		T24	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T21	1		T221	10		T113	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T118	1		T245	2		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T21	1		T98	11		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	13		T144	1		T109	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T12	2		T13	6		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T21	1		T93	11		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T155	1		T142	13		T146	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T103	11		T157	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T97	2		T99	1		T100	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	1		T102	1		T113	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T19	14		T34	9		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T19	5		T214	1		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	12		T317	3		T272	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T118	1		T119	1		T110	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T34	1		T91	10		T99	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T121	1		T242	9		T247	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T24	5		T99	5		T111	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T114	1		T178	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T20	8		T117	1		T100	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T96	1		T102	1		T109	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16574	1			T15	192		T16	19		T18	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T34	2		T226	10		T260	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T113	4		T186	1		T333	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T118	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T216	13		T144	3		T112	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T144	2		T109	2		T140	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T104	14		T105	15		T223	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T93	12		T35	2		T217	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T142	15		T146	14		T116	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T103	9		T138	9		T228	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T100	10		T101	3		T112	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	11		T102	2		T113	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T19	13		T101	4		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T19	11		T102	9		T229	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T138	12		T317	2		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T118	3		T219	4		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T34	1		T91	5		T99	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T247	10		T234	3		T309	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T24	1		T99	6		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T166	2		T233	12		T279	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T20	2		T117	13		T113	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T102	16		T109	4		T116	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	1		T24	2		T121	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T20	1		T144	3		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T12	2		T13	1		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T21	1		T93	13		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T100	11		T155	1		T142	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T103	10		T157	1		T138	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T97	2		T99	1		T101	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	12		T102	3		T113	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T19	14		T34	1		T101	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T19	12		T118	4		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T34	2		T92	4		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T110	1		T127	1		T219	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T91	10		T99	19		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T121	1		T242	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T24	4		T117	14		T99	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T114	1		T178	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T20	3		T34	3		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T21	1		T221	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T260	6		T306	1		T292	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T113	5		T238	1		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17222	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T118	14		T265	11		T256	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T216	10		T112	2		T186	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T20	12		T155	4		T109	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T13	5		T22	12		T23	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T93	10		T35	2		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T100	3		T142	12		T147	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T103	10		T146	2		T228	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T112	11		T186	5		T187	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T113	12		T222	3		T115	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T19	13		T34	8		T125	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T19	4		T198	2		T280	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T138	11		T218	1		T219	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T110	6		T219	11		T237	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T91	5		T99	15		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T242	8		T247	2		T309	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T24	2		T99	4		T139	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T166	2		T233	12		T272	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T20	7		T34	8		T100	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T221	9		T109	12		T116	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T292	7		T310	7		T303	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T113	12		T311	11		T334	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T98	10		T142	2		T267	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T256	9		T283	8		T335	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	500	1			T15	4		T18	6		T24	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T21	1		T221	1		T113	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T118	14		T245	2		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T21	1		T98	1		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T20	1		T144	3		T109	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T12	2		T13	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	1		T93	13		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T155	1		T142	16		T146	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T103	10		T157	1		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T97	2		T99	1		T100	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	12		T102	3		T113	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T19	14		T34	1		T101	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	12		T214	1		T102	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	13		T317	3		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T118	4		T119	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T34	2		T91	10		T99	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T121	1		T242	1		T247	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T24	4		T99	7		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T114	1		T178	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T20	3		T117	14		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T96	1		T102	17		T109	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16737	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T34	8		T336	12		T337	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T221	9		T113	12		T333	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T98	10		T216	10		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T20	12		T109	2		T140	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T13	5		T22	12		T23	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T93	10		T35	2		T155	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T142	12		T146	13		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T103	10		T305	5		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T100	3		T112	11		T186	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T113	12		T146	2		T222	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T19	13		T34	8		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T19	4		T280	3		T237	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T138	11		T317	2		T272	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T110	6		T219	11		T259	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T91	5		T99	15		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T242	8		T247	2		T309	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T24	2		T99	4		T111	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T166	2		T233	12		T272	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T20	7		T100	7		T113	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T109	12		T116	14		T243	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19