Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25019

1

T6

2

T26

1

T41

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22311

1

T6

2

T26

1

T41

1

auto[ADC_CTRL_FILTER_COND_OUT]

2708

1

T20

13

T93

23

T97

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19854

1

T6

2

T26

1

T41

1

auto[1]

5165

1

T12

2

T13

6

T17

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21275

1

T12

2

T13

6

T14

1

auto[1]

3744

1

T6

2

T26

1

T41

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T315	19		T338	2		T339	1
values[0]	34	1			T111	19		T258	15		-	-
values[1]	524	1			T97	1		T91	15		T35	8
values[2]	727	1			T97	1		T34	2		T99	34
values[3]	590	1			T121	1		T217	18		T103	20
values[4]	733	1			T98	11		T99	11		T216	24
values[5]	516	1			T20	13		T121	1		T221	10
values[6]	532	1			T97	1		T34	11		T112	25
values[7]	439	1			T20	10		T21	1		T144	3
values[8]	508	1			T14	12		T21	1		T93	23
values[9]	3243	1			T12	2		T13	6		T17	2
minimum	17151	1			T6	2		T26	1		T41	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	721	1			T97	1		T91	15		T108	1
values[1]	790	1			T97	1		T34	2		T35	8
values[2]	438	1			T121	1		T98	11		T217	18
values[3]	706	1			T96	1		T216	24		T118	18
values[4]	582	1			T97	1		T121	1		T221	10
values[5]	468	1			T20	13		T34	11		T112	25
values[6]	2552	1			T12	2		T13	6		T14	12
values[7]	640	1			T19	16		T21	1		T93	23
values[8]	771	1			T21	1		T24	8		T34	9
values[9]	179	1			T19	27		T140	6		T111	6
minimum	17172	1			T6	2		T26	1		T41	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

3254

1

T13

5

T19

17

T20

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T97	1		T91	10		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T100	8		T101	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T35	6		T114	1		T139	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T97	1		T34	1		T99	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T217	10		T214	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T121	1		T98	11		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T96	1		T118	1		T102	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T216	11		T118	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T221	10		T138	12		T186	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T97	1		T121	1		T99	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T119	1		T166	6		T126	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T20	13		T34	9		T112	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T12	2		T13	6		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T117	1		T178	2		T186	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T19	5		T21	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T93	11		T144	1		T110	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T21	1		T24	7		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	9		T99	1		T100	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T19	14		T140	5		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T111	6		T317	3		T129	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16994	1			T15	196		T16	19		T18	186
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T340	1		T270	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T91	5		T142	15		T113	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T101	4		T144	3		T92	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T35	2		T139	12		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	1		T99	18		T103	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T217	8		T147	7		T260	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T265	10		T253	7		T341	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T118	3		T102	5		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T216	13		T118	13		T102	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T138	12		T186	7		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T99	6		T102	2		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T166	2		T126	14		T128	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	2		T112	13		T111	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T14	11		T20	2		T104	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T117	13		T186	6		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T19	11		T187	3		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T93	12		T144	2		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T24	1		T92	3		T102	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T100	10		T226	10		T112	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T19	13		T140	1		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T317	2		T129	8		T342	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	2		T26	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T340	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T315	13		T338	2		T339	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T258	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T111	14		T258	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T97	1		T91	10		T35	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T100	8		T101	1		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T108	1		T113	13		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T97	1		T34	1		T99	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T217	10		T114	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T121	1		T103	11		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T118	1		T214	1		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T98	11		T99	5		T216	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T221	10		T96	1		T102	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T20	13		T121	1		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T119	1		T166	6		T222	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T97	1		T34	9		T112	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T20	8		T21	1		T125	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T144	1		T178	1		T111	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T14	1		T21	1		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T93	11		T117	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T12	2		T13	6		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T34	9		T99	1		T100	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T15	196		T16	19		T18	186
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T315	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T111	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T91	5		T35	2		T142	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T101	4		T92	6		T109	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T113	15		T139	12		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T34	1		T99	18		T144	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T217	8		T219	13		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T103	9		T146	14		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T118	3		T147	7		T254	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T99	6		T216	13		T102	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T102	5		T138	12		T186	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T118	13		T102	2		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T166	2		T222	9		T289	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T34	2		T112	13		T304	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T20	2		T125	10		T138	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T144	2		T111	15		T186	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	11		T101	3		T187	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T93	12		T117	13		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T19	24		T24	1		T104	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T100	10		T226	10		T112	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T26	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T97	1		T91	10		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T100	1		T101	5		T144	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T35	6		T114	1		T139	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T97	1		T34	2		T99	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T217	9		T214	1		T147	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T121	1		T98	1		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T96	1		T118	4		T102	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T216	14		T118	14		T102	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T221	1		T138	13		T186	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T97	1		T121	1		T99	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T119	1		T166	6		T126	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T20	1		T34	3		T112	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T12	2		T13	1		T14	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T117	14		T178	2		T186	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	12		T21	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T93	13		T144	3		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	1		T24	6		T92	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T34	1		T99	1		T100	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T19	14		T140	4		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T111	1		T317	3		T129	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17159	1			T6	2		T26	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T340	5		T270	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T91	5		T142	12		T113	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T100	7		T155	4		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	2		T139	11		T48	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T99	15		T103	10		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T217	9		T301	3		T280	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T98	10		T261	10		T170	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T102	5		T198	2		T115	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T216	10		T146	2		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T221	9		T138	11		T186	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T99	4		T242	8		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T166	2		T126	14		T128	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T20	12		T34	8		T112	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T13	5		T20	7		T22	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T186	5		T243	6		T247	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T19	4		T187	2		T116	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T93	10		T110	6		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T24	2		T113	12		T286	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	8		T100	3		T112	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T19	13		T140	2		T272	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T111	5		T317	2		T149	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T139	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T270	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T315	7		T338	2		T339	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T111	6		T258	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T97	1		T91	10		T35	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T100	1		T101	5		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T108	1		T113	16		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T97	1		T34	2		T99	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T217	9		T114	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T121	1		T103	10		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T118	4		T214	1		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T98	1		T99	7		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T221	1		T96	1		T102	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T20	1		T121	1		T118	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T119	1		T166	6		T222	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T97	1		T34	3		T112	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T20	3		T21	1		T125	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T144	3		T178	1		T111	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	12		T21	1		T101	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T93	13		T117	14		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T12	2		T13	1		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T34	1		T99	1		T100	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17151	1			T6	2		T26	1		T41	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T315	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T258	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T111	13		T258	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T91	5		T35	2		T142	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T100	7		T142	2		T109	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T113	12		T139	11		T48	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T99	15		T155	4		T280	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T217	9		T301	3		T219	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T103	10		T146	13		T219	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T280	3		T255	13		T287	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T98	10		T99	4		T216	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T221	9		T102	5		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T20	12		T133	10		T279	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T166	2		T222	3		T256	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T34	8		T112	11		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T20	7		T125	10		T126	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T111	9		T186	5		T243	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T187	2		T116	14		T260	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T93	10		T110	6		T218	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T13	5		T19	17		T22	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T34	8		T100	3		T112	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21765

1

T6

2

T26

1

T41

1

auto[1]

auto[0]

3254

1

T13

5

T19

17

T20

19