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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.51 98.98 95.69 100.00 100.00 98.18 98.64 91.07


Total test records in report: 914
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T350 /workspace/coverage/default/42.adc_ctrl_filters_polled.72709978 Feb 04 01:07:50 PM PST 24 Feb 04 01:25:39 PM PST 24 495274572850 ps
T354 /workspace/coverage/default/33.adc_ctrl_clock_gating.385076716 Feb 04 01:06:27 PM PST 24 Feb 04 01:14:36 PM PST 24 485099575875 ps
T777 /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1350194921 Feb 04 01:06:13 PM PST 24 Feb 04 01:12:04 PM PST 24 490337159400 ps
T778 /workspace/coverage/default/48.adc_ctrl_fsm_reset.1325983562 Feb 04 01:09:05 PM PST 24 Feb 04 01:15:05 PM PST 24 108696354167 ps
T779 /workspace/coverage/default/28.adc_ctrl_lowpower_counter.718474447 Feb 04 01:05:44 PM PST 24 Feb 04 01:06:16 PM PST 24 29513220623 ps
T780 /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3041649301 Feb 04 01:03:35 PM PST 24 Feb 04 01:16:24 PM PST 24 330727583738 ps
T781 /workspace/coverage/default/6.adc_ctrl_filters_both.3831757009 Feb 04 01:04:01 PM PST 24 Feb 04 01:09:51 PM PST 24 324529921916 ps
T239 /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3539003084 Feb 04 01:09:05 PM PST 24 Feb 04 01:26:47 PM PST 24 493890745717 ps
T782 /workspace/coverage/default/2.adc_ctrl_alert_test.2291204872 Feb 04 01:03:13 PM PST 24 Feb 04 01:03:15 PM PST 24 532749175 ps
T783 /workspace/coverage/default/1.adc_ctrl_smoke.666482077 Feb 04 01:03:08 PM PST 24 Feb 04 01:03:14 PM PST 24 6209802663 ps
T784 /workspace/coverage/default/11.adc_ctrl_alert_test.2940269511 Feb 04 01:04:22 PM PST 24 Feb 04 01:04:25 PM PST 24 464337642 ps
T785 /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1229243881 Feb 04 01:04:36 PM PST 24 Feb 04 01:06:23 PM PST 24 169707664630 ps
T786 /workspace/coverage/default/7.adc_ctrl_stress_all.220758236 Feb 04 01:04:05 PM PST 24 Feb 04 01:08:08 PM PST 24 369674125528 ps
T787 /workspace/coverage/default/17.adc_ctrl_poweron_counter.1738649837 Feb 04 01:04:48 PM PST 24 Feb 04 01:05:08 PM PST 24 5172648622 ps
T788 /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2712207042 Feb 04 01:06:39 PM PST 24 Feb 04 01:18:04 PM PST 24 323832309415 ps
T789 /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.329026557 Feb 04 01:03:17 PM PST 24 Feb 04 01:04:06 PM PST 24 74470509299 ps
T790 /workspace/coverage/default/16.adc_ctrl_filters_both.1422911724 Feb 04 01:04:43 PM PST 24 Feb 04 01:05:53 PM PST 24 157735365340 ps
T791 /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3398287528 Feb 04 01:03:35 PM PST 24 Feb 04 01:14:09 PM PST 24 489720337142 ps
T792 /workspace/coverage/default/23.adc_ctrl_fsm_reset.1785331351 Feb 04 01:05:02 PM PST 24 Feb 04 01:15:18 PM PST 24 110167480193 ps
T793 /workspace/coverage/default/7.adc_ctrl_smoke.2908436630 Feb 04 01:04:05 PM PST 24 Feb 04 01:04:15 PM PST 24 5925908474 ps
T794 /workspace/coverage/default/42.adc_ctrl_filters_interrupt.563811639 Feb 04 01:07:49 PM PST 24 Feb 04 01:20:32 PM PST 24 333002877292 ps
T342 /workspace/coverage/default/30.adc_ctrl_clock_gating.3682078137 Feb 04 01:06:19 PM PST 24 Feb 04 01:11:57 PM PST 24 489170686528 ps
T795 /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1753316338 Feb 04 01:06:51 PM PST 24 Feb 04 01:08:04 PM PST 24 31246542568 ps
T324 /workspace/coverage/default/40.adc_ctrl_filters_polled.3301216904 Feb 04 01:07:25 PM PST 24 Feb 04 01:26:35 PM PST 24 494970983276 ps
T258 /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2076377512 Feb 04 01:04:00 PM PST 24 Feb 04 01:10:02 PM PST 24 324321520300 ps
T796 /workspace/coverage/default/18.adc_ctrl_stress_all.947470729 Feb 04 01:05:01 PM PST 24 Feb 04 01:12:41 PM PST 24 208467278247 ps
T797 /workspace/coverage/default/12.adc_ctrl_smoke.1572067193 Feb 04 01:04:22 PM PST 24 Feb 04 01:04:36 PM PST 24 5774684029 ps
T798 /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1139895871 Feb 04 01:04:39 PM PST 24 Feb 04 01:05:42 PM PST 24 25649898411 ps
T799 /workspace/coverage/default/25.adc_ctrl_filters_polled.2905582090 Feb 04 01:05:17 PM PST 24 Feb 04 01:14:54 PM PST 24 489645297137 ps
T800 /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2279664596 Feb 04 01:08:11 PM PST 24 Feb 04 01:14:22 PM PST 24 161315656306 ps
T273 /workspace/coverage/default/32.adc_ctrl_filters_interrupt.712322858 Feb 04 01:06:16 PM PST 24 Feb 04 01:25:58 PM PST 24 491563459802 ps
T801 /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2396257858 Feb 04 01:04:45 PM PST 24 Feb 04 01:10:20 PM PST 24 497499519736 ps
T802 /workspace/coverage/default/20.adc_ctrl_filters_both.1677309878 Feb 04 01:04:58 PM PST 24 Feb 04 01:05:40 PM PST 24 156658533597 ps
T803 /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1689614487 Feb 04 01:06:14 PM PST 24 Feb 04 01:07:37 PM PST 24 52117723415 ps
T804 /workspace/coverage/default/7.adc_ctrl_alert_test.4128085563 Feb 04 01:04:07 PM PST 24 Feb 04 01:04:16 PM PST 24 322392338 ps
T805 /workspace/coverage/default/29.adc_ctrl_lowpower_counter.789311343 Feb 04 01:06:06 PM PST 24 Feb 04 01:06:44 PM PST 24 21928064114 ps
T355 /workspace/coverage/default/0.adc_ctrl_filters_wakeup.69384241 Feb 04 01:03:09 PM PST 24 Feb 04 01:06:04 PM PST 24 340880029104 ps
T806 /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2977279076 Feb 04 01:06:12 PM PST 24 Feb 04 01:07:12 PM PST 24 22657735386 ps
T330 /workspace/coverage/default/43.adc_ctrl_filters_both.978971576 Feb 04 01:08:09 PM PST 24 Feb 04 01:09:32 PM PST 24 329244890308 ps
T807 /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2395982223 Feb 04 01:06:16 PM PST 24 Feb 04 01:09:49 PM PST 24 328964651108 ps
T808 /workspace/coverage/default/36.adc_ctrl_poweron_counter.2069818156 Feb 04 01:06:59 PM PST 24 Feb 04 01:07:10 PM PST 24 3238108254 ps
T809 /workspace/coverage/default/41.adc_ctrl_filters_both.1055254151 Feb 04 01:07:56 PM PST 24 Feb 04 01:08:25 PM PST 24 168007185452 ps
T810 /workspace/coverage/default/27.adc_ctrl_clock_gating.3679392836 Feb 04 01:05:32 PM PST 24 Feb 04 01:12:49 PM PST 24 334812258157 ps
T811 /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3185085693 Feb 04 01:04:57 PM PST 24 Feb 04 01:08:06 PM PST 24 326513315440 ps
T812 /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3289739449 Feb 04 01:04:23 PM PST 24 Feb 04 01:09:21 PM PST 24 490216523119 ps
T813 /workspace/coverage/default/22.adc_ctrl_alert_test.182164438 Feb 04 01:05:01 PM PST 24 Feb 04 01:05:09 PM PST 24 496666844 ps
T814 /workspace/coverage/default/38.adc_ctrl_poweron_counter.1100483805 Feb 04 01:07:13 PM PST 24 Feb 04 01:07:28 PM PST 24 5490615120 ps
T815 /workspace/coverage/default/15.adc_ctrl_alert_test.2369731576 Feb 04 01:04:43 PM PST 24 Feb 04 01:04:53 PM PST 24 416004582 ps
T298 /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3777721387 Feb 04 01:08:11 PM PST 24 Feb 04 01:10:41 PM PST 24 121058733000 ps
T816 /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.732649473 Feb 04 01:09:04 PM PST 24 Feb 04 01:10:52 PM PST 24 169250698384 ps
T817 /workspace/coverage/default/33.adc_ctrl_poweron_counter.1567160718 Feb 04 01:06:28 PM PST 24 Feb 04 01:06:30 PM PST 24 3907041556 ps
T818 /workspace/coverage/default/30.adc_ctrl_alert_test.1232425500 Feb 04 01:06:10 PM PST 24 Feb 04 01:06:18 PM PST 24 493659253 ps
T819 /workspace/coverage/default/8.adc_ctrl_stress_all.1276902413 Feb 04 01:04:20 PM PST 24 Feb 04 01:04:49 PM PST 24 11653850123 ps
T820 /workspace/coverage/default/16.adc_ctrl_smoke.479147978 Feb 04 01:04:40 PM PST 24 Feb 04 01:04:59 PM PST 24 6084560063 ps
T821 /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3313536828 Feb 04 01:03:53 PM PST 24 Feb 04 01:07:07 PM PST 24 326998605967 ps
T371 /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3877385229 Feb 04 01:04:42 PM PST 24 Feb 04 01:09:57 PM PST 24 130914428527 ps
T822 /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1179100671 Feb 04 01:09:10 PM PST 24 Feb 04 01:10:04 PM PST 24 332192448434 ps
T823 /workspace/coverage/default/39.adc_ctrl_clock_gating.3821150492 Feb 04 01:07:36 PM PST 24 Feb 04 01:13:28 PM PST 24 163961770049 ps
T824 /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1243556605 Feb 04 01:04:46 PM PST 24 Feb 04 01:05:46 PM PST 24 123047632733 ps
T825 /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1273114341 Feb 04 01:04:50 PM PST 24 Feb 04 01:07:56 PM PST 24 123928085090 ps
T270 /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3813714643 Feb 04 01:03:56 PM PST 24 Feb 04 01:16:28 PM PST 24 338857981159 ps
T826 /workspace/coverage/default/0.adc_ctrl_clock_gating.4066867752 Feb 04 01:03:09 PM PST 24 Feb 04 01:03:49 PM PST 24 162143523417 ps
T827 /workspace/coverage/default/11.adc_ctrl_fsm_reset.1536008485 Feb 04 01:04:31 PM PST 24 Feb 04 01:12:09 PM PST 24 84841643551 ps
T828 /workspace/coverage/default/6.adc_ctrl_alert_test.594880158 Feb 04 01:04:01 PM PST 24 Feb 04 01:04:03 PM PST 24 345110276 ps
T829 /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.919401297 Feb 04 01:06:56 PM PST 24 Feb 04 01:11:42 PM PST 24 495878525995 ps
T830 /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1103529330 Feb 04 01:09:15 PM PST 24 Feb 04 01:10:46 PM PST 24 164371288379 ps
T831 /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1179760193 Feb 04 01:07:49 PM PST 24 Feb 04 01:08:29 PM PST 24 32957354637 ps
T832 /workspace/coverage/default/33.adc_ctrl_alert_test.848741219 Feb 04 01:06:24 PM PST 24 Feb 04 01:06:27 PM PST 24 406351229 ps
T833 /workspace/coverage/default/21.adc_ctrl_smoke.1870851275 Feb 04 01:04:43 PM PST 24 Feb 04 01:05:07 PM PST 24 5898367453 ps
T339 /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4291317146 Feb 04 01:09:09 PM PST 24 Feb 04 01:13:36 PM PST 24 327346194815 ps
T834 /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2139602400 Feb 04 01:04:48 PM PST 24 Feb 04 01:19:06 PM PST 24 333591024622 ps
T351 /workspace/coverage/default/44.adc_ctrl_filters_both.1994802195 Feb 04 01:08:45 PM PST 24 Feb 04 01:10:30 PM PST 24 327212142508 ps
T332 /workspace/coverage/default/28.adc_ctrl_filters_both.3457526857 Feb 04 01:05:50 PM PST 24 Feb 04 01:12:18 PM PST 24 164120795038 ps
T835 /workspace/coverage/default/15.adc_ctrl_clock_gating.3482610742 Feb 04 01:04:34 PM PST 24 Feb 04 01:16:48 PM PST 24 327440134522 ps
T836 /workspace/coverage/default/26.adc_ctrl_alert_test.1455668403 Feb 04 01:05:31 PM PST 24 Feb 04 01:05:39 PM PST 24 447541133 ps
T837 /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3807746467 Feb 04 01:04:20 PM PST 24 Feb 04 01:11:12 PM PST 24 161876161426 ps
T196 /workspace/coverage/default/14.adc_ctrl_fsm_reset.3801988017 Feb 04 01:04:34 PM PST 24 Feb 04 01:14:23 PM PST 24 130456350484 ps
T838 /workspace/coverage/default/47.adc_ctrl_alert_test.1376555011 Feb 04 01:09:02 PM PST 24 Feb 04 01:09:04 PM PST 24 522573846 ps
T839 /workspace/coverage/default/30.adc_ctrl_filters_polled.51032803 Feb 04 01:06:09 PM PST 24 Feb 04 01:07:23 PM PST 24 165314812391 ps
T271 /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2982891821 Feb 04 01:04:41 PM PST 24 Feb 04 01:07:26 PM PST 24 462769473833 ps
T840 /workspace/coverage/default/21.adc_ctrl_stress_all.2209095399 Feb 04 01:05:02 PM PST 24 Feb 04 01:14:46 PM PST 24 115925491488 ps
T841 /workspace/coverage/default/45.adc_ctrl_poweron_counter.786903132 Feb 04 01:08:45 PM PST 24 Feb 04 01:08:55 PM PST 24 3205465697 ps
T842 /workspace/coverage/default/5.adc_ctrl_poweron_counter.2479112187 Feb 04 01:03:52 PM PST 24 Feb 04 01:03:55 PM PST 24 3153383385 ps
T843 /workspace/coverage/default/19.adc_ctrl_poweron_counter.2351993792 Feb 04 01:05:01 PM PST 24 Feb 04 01:05:11 PM PST 24 3210266990 ps
T844 /workspace/coverage/default/10.adc_ctrl_filters_interrupt.703356937 Feb 04 01:04:14 PM PST 24 Feb 04 01:07:32 PM PST 24 321692253101 ps
T845 /workspace/coverage/default/30.adc_ctrl_filters_wakeup.81849163 Feb 04 01:06:10 PM PST 24 Feb 04 01:26:00 PM PST 24 498861632323 ps
T846 /workspace/coverage/default/39.adc_ctrl_poweron_counter.813464825 Feb 04 01:07:25 PM PST 24 Feb 04 01:07:43 PM PST 24 4626383267 ps
T847 /workspace/coverage/default/41.adc_ctrl_filters_polled.2451046390 Feb 04 01:07:34 PM PST 24 Feb 04 01:15:51 PM PST 24 489948897128 ps
T848 /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2275804089 Feb 04 01:09:03 PM PST 24 Feb 04 01:21:20 PM PST 24 329147083341 ps
T327 /workspace/coverage/default/34.adc_ctrl_clock_gating.1878025236 Feb 04 01:06:50 PM PST 24 Feb 04 01:08:12 PM PST 24 336815400790 ps
T849 /workspace/coverage/default/49.adc_ctrl_smoke.1123660146 Feb 04 01:09:01 PM PST 24 Feb 04 01:09:16 PM PST 24 6049959210 ps
T850 /workspace/coverage/default/34.adc_ctrl_poweron_counter.1063118834 Feb 04 01:06:45 PM PST 24 Feb 04 01:06:56 PM PST 24 4895542975 ps
T851 /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2578561685 Feb 04 01:03:31 PM PST 24 Feb 04 01:06:10 PM PST 24 80718368325 ps
T852 /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2406789994 Feb 04 01:07:27 PM PST 24 Feb 04 01:18:57 PM PST 24 323157074052 ps
T853 /workspace/coverage/default/26.adc_ctrl_fsm_reset.2941083242 Feb 04 01:05:29 PM PST 24 Feb 04 01:15:30 PM PST 24 99394475845 ps
T854 /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3074321825 Feb 04 01:03:35 PM PST 24 Feb 04 01:06:20 PM PST 24 268948955693 ps
T855 /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2318940291 Feb 04 01:09:00 PM PST 24 Feb 04 01:12:26 PM PST 24 382299912253 ps
T856 /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3523247969 Feb 04 01:06:26 PM PST 24 Feb 04 01:11:05 PM PST 24 490970460127 ps
T857 /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1757074581 Feb 04 01:04:35 PM PST 24 Feb 04 01:12:29 PM PST 24 485728235257 ps
T858 /workspace/coverage/default/27.adc_ctrl_filters_both.4131609576 Feb 04 01:05:46 PM PST 24 Feb 04 01:07:30 PM PST 24 166341113746 ps
T859 /workspace/coverage/default/30.adc_ctrl_fsm_reset.3131627655 Feb 04 01:06:11 PM PST 24 Feb 04 01:15:14 PM PST 24 92788663084 ps
T860 /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3947645452 Feb 04 01:07:37 PM PST 24 Feb 04 01:08:22 PM PST 24 68451314383 ps
T861 /workspace/coverage/default/6.adc_ctrl_stress_all.2826517951 Feb 04 01:04:03 PM PST 24 Feb 04 01:04:12 PM PST 24 5841106260 ps
T862 /workspace/coverage/default/32.adc_ctrl_filters_wakeup.649007596 Feb 04 01:06:17 PM PST 24 Feb 04 01:09:16 PM PST 24 326772175912 ps
T346 /workspace/coverage/default/36.adc_ctrl_clock_gating.2504557551 Feb 04 01:06:55 PM PST 24 Feb 04 01:19:30 PM PST 24 324729689132 ps
T863 /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2149024538 Feb 04 01:03:09 PM PST 24 Feb 04 01:04:56 PM PST 24 167759160267 ps
T362 /workspace/coverage/default/15.adc_ctrl_filters_polled.672757240 Feb 04 01:04:40 PM PST 24 Feb 04 01:07:37 PM PST 24 324623847097 ps
T864 /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3728162225 Feb 04 01:04:32 PM PST 24 Feb 04 01:25:12 PM PST 24 496325162082 ps
T865 /workspace/coverage/default/0.adc_ctrl_alert_test.2937794476 Feb 04 01:03:11 PM PST 24 Feb 04 01:03:13 PM PST 24 312339613 ps
T866 /workspace/coverage/default/29.adc_ctrl_filters_both.3342969095 Feb 04 01:06:04 PM PST 24 Feb 04 01:12:44 PM PST 24 162353604042 ps
T867 /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4014331277 Feb 04 01:06:50 PM PST 24 Feb 04 01:13:27 PM PST 24 158840774872 ps
T46 /workspace/coverage/default/1.adc_ctrl_sec_cm.4281998459 Feb 04 01:03:18 PM PST 24 Feb 04 01:03:30 PM PST 24 4012355092 ps
T868 /workspace/coverage/default/20.adc_ctrl_filters_polled.1937301178 Feb 04 01:04:47 PM PST 24 Feb 04 01:08:24 PM PST 24 160479005214 ps
T77 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.830061561 Feb 04 12:40:16 PM PST 24 Feb 04 12:40:30 PM PST 24 426756523 ps
T869 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3666616505 Feb 04 12:40:39 PM PST 24 Feb 04 12:40:42 PM PST 24 493165054 ps
T870 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4219424523 Feb 04 12:41:10 PM PST 24 Feb 04 12:41:13 PM PST 24 591933262 ps
T871 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.768423083 Feb 04 12:40:33 PM PST 24 Feb 04 12:40:41 PM PST 24 482899959 ps
T872 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2973728707 Feb 04 12:40:25 PM PST 24 Feb 04 12:40:39 PM PST 24 1215264401 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2443705253 Feb 04 12:40:18 PM PST 24 Feb 04 12:40:38 PM PST 24 2155293193 ps
T874 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1270029615 Feb 04 12:40:46 PM PST 24 Feb 04 12:40:53 PM PST 24 4570544316 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.847729191 Feb 04 12:40:19 PM PST 24 Feb 04 12:40:33 PM PST 24 411881969 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2496536425 Feb 04 12:40:18 PM PST 24 Feb 04 12:40:36 PM PST 24 8912419061 ps
T877 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2082215127 Feb 04 12:40:41 PM PST 24 Feb 04 12:40:49 PM PST 24 4261831383 ps
T878 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1635399109 Feb 04 12:40:46 PM PST 24 Feb 04 12:41:08 PM PST 24 7827500388 ps
T879 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1917414355 Feb 04 12:41:00 PM PST 24 Feb 04 12:41:04 PM PST 24 470539528 ps
T880 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3540355344 Feb 04 12:40:58 PM PST 24 Feb 04 12:41:04 PM PST 24 454883182 ps
T881 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3409835076 Feb 04 12:40:37 PM PST 24 Feb 04 12:40:47 PM PST 24 5105167348 ps
T882 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2924571260 Feb 04 12:41:00 PM PST 24 Feb 04 12:41:05 PM PST 24 487165841 ps
T883 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3620167953 Feb 04 12:40:36 PM PST 24 Feb 04 12:40:42 PM PST 24 473720804 ps
T884 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2113871274 Feb 04 12:41:00 PM PST 24 Feb 04 12:41:05 PM PST 24 479147696 ps
T885 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.840379925 Feb 04 12:40:46 PM PST 24 Feb 04 12:40:48 PM PST 24 656469635 ps
T886 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.498067572 Feb 04 12:40:27 PM PST 24 Feb 04 12:40:39 PM PST 24 597680629 ps
T83 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1192080900 Feb 04 12:40:19 PM PST 24 Feb 04 12:40:37 PM PST 24 998353744 ps
T84 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.807545237 Feb 04 12:41:00 PM PST 24 Feb 04 12:41:04 PM PST 24 514756820 ps
T887 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3961685937 Feb 04 12:41:00 PM PST 24 Feb 04 12:41:04 PM PST 24 575866681 ps
T888 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1755901537 Feb 04 12:40:19 PM PST 24 Feb 04 12:40:38 PM PST 24 4237830373 ps
T889 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2086669680 Feb 04 12:40:41 PM PST 24 Feb 04 12:40:44 PM PST 24 2434515053 ps
T890 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.833869573 Feb 04 12:41:04 PM PST 24 Feb 04 12:41:08 PM PST 24 470864152 ps
T891 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3241939046 Feb 04 12:40:20 PM PST 24 Feb 04 12:40:35 PM PST 24 361536569 ps
T892 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.40959388 Feb 04 12:41:09 PM PST 24 Feb 04 12:41:10 PM PST 24 473025449 ps
T893 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2621643543 Feb 04 12:41:00 PM PST 24 Feb 04 12:41:14 PM PST 24 4657139536 ps
T894 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2839759489 Feb 04 12:40:36 PM PST 24 Feb 04 12:40:47 PM PST 24 8086476900 ps
T895 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3893986075 Feb 04 12:40:36 PM PST 24 Feb 04 12:40:42 PM PST 24 501566982 ps
T896 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4053093909 Feb 04 12:40:46 PM PST 24 Feb 04 12:40:48 PM PST 24 547527645 ps
T897 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.658413669 Feb 04 12:40:46 PM PST 24 Feb 04 12:40:49 PM PST 24 453986398 ps
T898 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1761639605 Feb 04 12:40:17 PM PST 24 Feb 04 12:40:48 PM PST 24 7370600831 ps
T85 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.419558980 Feb 04 12:40:16 PM PST 24 Feb 04 12:40:43 PM PST 24 41226695705 ps
T86 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1748411830 Feb 04 12:40:39 PM PST 24 Feb 04 12:40:43 PM PST 24 484926665 ps
T899 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.572394629 Feb 04 12:40:57 PM PST 24 Feb 04 12:41:03 PM PST 24 467539667 ps
T900 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1655278183 Feb 04 12:41:00 PM PST 24 Feb 04 12:41:05 PM PST 24 325062718 ps
T901 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1996083329 Feb 04 12:40:59 PM PST 24 Feb 04 12:41:04 PM PST 24 375617588 ps
T902 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3728287851 Feb 04 12:40:33 PM PST 24 Feb 04 12:40:43 PM PST 24 597811055 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1375605795 Feb 04 12:40:37 PM PST 24 Feb 04 12:40:42 PM PST 24 341378522 ps
T904 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2986444425 Feb 04 12:41:17 PM PST 24 Feb 04 12:41:28 PM PST 24 3846281372 ps
T905 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2703451718 Feb 04 12:40:58 PM PST 24 Feb 04 12:41:23 PM PST 24 8402521839 ps
T906 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.338965101 Feb 04 12:41:14 PM PST 24 Feb 04 12:41:18 PM PST 24 556922960 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3464206583 Feb 04 12:40:11 PM PST 24 Feb 04 12:40:30 PM PST 24 1137475810 ps
T908 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2771444786 Feb 04 12:40:20 PM PST 24 Feb 04 12:40:36 PM PST 24 1138829224 ps
T909 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3635246991 Feb 04 12:40:38 PM PST 24 Feb 04 12:40:42 PM PST 24 388238781 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3397415587 Feb 04 12:40:17 PM PST 24 Feb 04 12:40:31 PM PST 24 426566132 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.283912281 Feb 04 12:40:19 PM PST 24 Feb 04 12:40:34 PM PST 24 700981823 ps
T912 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.708855962 Feb 04 12:40:42 PM PST 24 Feb 04 12:40:45 PM PST 24 359208073 ps
T913 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1863893868 Feb 04 12:40:41 PM PST 24 Feb 04 12:40:46 PM PST 24 4333172361 ps
T914 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4273079984 Feb 04 12:41:12 PM PST 24 Feb 04 12:41:16 PM PST 24 353852569 ps

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2535551350
Short name T3
Test name
Test status
Simulation time 4537962116 ps
CPU time 6.27 seconds
Started Feb 04 12:40:28 PM PST 24
Finished Feb 04 12:40:44 PM PST 24
Peak memory 201700 kb
Host smart-19c68868-18e7-4afd-96ae-0119cd502a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535551350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2535551350
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4071205441
Short name T5
Test name
Test status
Simulation time 304732374 ps
CPU time 0.97 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:34 PM PST 24
Peak memory 201088 kb
Host smart-006ce9eb-a0f6-4234-b297-77b3df05260f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071205441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4071205441
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4214351979
Short name T20
Test name
Test status
Simulation time 324514852338 ps
CPU time 194.25 seconds
Started Feb 04 01:04:38 PM PST 24
Finished Feb 04 01:07:57 PM PST 24
Peak memory 201600 kb
Host smart-0509289f-0d2b-4925-a2ea-8974fada90f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214351979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4214351979
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3656441481
Short name T186
Test name
Test status
Simulation time 935450215265 ps
CPU time 240.78 seconds
Started Feb 04 01:06:07 PM PST 24
Finished Feb 04 01:10:16 PM PST 24
Peak memory 218184 kb
Host smart-0175fb1e-8d0a-481e-9ef7-3dfe1059393d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656441481 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3656441481
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1211823472
Short name T102
Test name
Test status
Simulation time 659360218816 ps
CPU time 1645.1 seconds
Started Feb 04 01:05:52 PM PST 24
Finished Feb 04 01:33:18 PM PST 24
Peak memory 201540 kb
Host smart-bc84c8fb-ccc4-4909-9442-acca9b861442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211823472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1211823472
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3361859325
Short name T29
Test name
Test status
Simulation time 2123874183 ps
CPU time 4.37 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:37 PM PST 24
Peak memory 201240 kb
Host smart-5993338c-e009-4e9c-a4a6-a25c19e6b009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361859325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3361859325
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.950770169
Short name T24
Test name
Test status
Simulation time 186191266628 ps
CPU time 155.85 seconds
Started Feb 04 01:04:38 PM PST 24
Finished Feb 04 01:07:18 PM PST 24
Peak memory 210380 kb
Host smart-653ee029-b0ae-41c8-9312-1040b3a74462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950770169 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.950770169
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2111429200
Short name T113
Test name
Test status
Simulation time 491818281553 ps
CPU time 318.72 seconds
Started Feb 04 01:04:12 PM PST 24
Finished Feb 04 01:09:34 PM PST 24
Peak memory 201608 kb
Host smart-cf7ed58d-e196-41c3-916f-43b8899cd01d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111429200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2111429200
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2804531711
Short name T63
Test name
Test status
Simulation time 410808441 ps
CPU time 0.83 seconds
Started Feb 04 12:41:10 PM PST 24
Finished Feb 04 12:41:13 PM PST 24
Peak memory 201276 kb
Host smart-8a5d85d2-2254-43f1-be50-966d2830fe04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804531711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2804531711
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4076635909
Short name T219
Test name
Test status
Simulation time 503184420681 ps
CPU time 553.17 seconds
Started Feb 04 01:06:41 PM PST 24
Finished Feb 04 01:16:00 PM PST 24
Peak memory 201416 kb
Host smart-4dcc1f92-a247-4dca-9fb8-8e6a6a4dacce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076635909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4076635909
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3932290922
Short name T34
Test name
Test status
Simulation time 486079234035 ps
CPU time 876.1 seconds
Started Feb 04 01:03:37 PM PST 24
Finished Feb 04 01:18:21 PM PST 24
Peak memory 201668 kb
Host smart-f7eca6a0-6213-4979-b96b-46ef0aa4c474
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932290922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3932290922
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.98792353
Short name T111
Test name
Test status
Simulation time 488571744615 ps
CPU time 1104.27 seconds
Started Feb 04 01:09:06 PM PST 24
Finished Feb 04 01:27:32 PM PST 24
Peak memory 201524 kb
Host smart-ca3c6357-5ab5-4d38-b024-3cd9e8e44421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98792353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.98792353
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2341582799
Short name T247
Test name
Test status
Simulation time 499098803285 ps
CPU time 819.82 seconds
Started Feb 04 01:05:43 PM PST 24
Finished Feb 04 01:19:24 PM PST 24
Peak memory 201484 kb
Host smart-757863cd-be56-4132-bc69-ec9f963e2bf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341582799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2341582799
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2185330311
Short name T99
Test name
Test status
Simulation time 483926538929 ps
CPU time 1043.04 seconds
Started Feb 04 01:04:22 PM PST 24
Finished Feb 04 01:21:46 PM PST 24
Peak memory 201584 kb
Host smart-6ca2c2f0-235c-4c98-b190-1ee52636c256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185330311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2185330311
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3903057409
Short name T181
Test name
Test status
Simulation time 326594820317 ps
CPU time 197.12 seconds
Started Feb 04 01:03:54 PM PST 24
Finished Feb 04 01:07:12 PM PST 24
Peak memory 201652 kb
Host smart-4eee8d90-0f13-44e1-b384-af47824cf8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903057409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3903057409
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2389127607
Short name T37
Test name
Test status
Simulation time 484727650 ps
CPU time 3.52 seconds
Started Feb 04 12:40:28 PM PST 24
Finished Feb 04 12:40:41 PM PST 24
Peak memory 209752 kb
Host smart-b0ea5a5b-1798-46ea-84f2-a448339ca3de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389127607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2389127607
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2198733150
Short name T17
Test name
Test status
Simulation time 331823512323 ps
CPU time 181.07 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:08:09 PM PST 24
Peak memory 201556 kb
Host smart-808b72e0-d581-42bc-943c-ba5a0808b9b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198733150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2198733150
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.621783901
Short name T109
Test name
Test status
Simulation time 332409818567 ps
CPU time 153.17 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:07:41 PM PST 24
Peak memory 201468 kb
Host smart-82d354f1-d8ed-4e33-8979-bcfb28367af7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621783901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.621783901
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3529975176
Short name T116
Test name
Test status
Simulation time 498103232103 ps
CPU time 188 seconds
Started Feb 04 01:04:02 PM PST 24
Finished Feb 04 01:07:12 PM PST 24
Peak memory 201596 kb
Host smart-b20460c7-a7d6-47aa-8a0e-6dd36ae5c571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529975176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3529975176
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2785549731
Short name T112
Test name
Test status
Simulation time 327828334764 ps
CPU time 739.56 seconds
Started Feb 04 01:05:21 PM PST 24
Finished Feb 04 01:17:44 PM PST 24
Peak memory 201672 kb
Host smart-c0e8d137-908e-4c0b-9ebd-e40267e0dace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785549731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2785549731
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3280455653
Short name T69
Test name
Test status
Simulation time 549917665 ps
CPU time 1.39 seconds
Started Feb 04 12:40:26 PM PST 24
Finished Feb 04 12:40:39 PM PST 24
Peak memory 201320 kb
Host smart-5ac768d2-7069-4379-b63c-f2bf80eba192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280455653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3280455653
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1387281227
Short name T289
Test name
Test status
Simulation time 326980656177 ps
CPU time 743.17 seconds
Started Feb 04 01:06:21 PM PST 24
Finished Feb 04 01:18:45 PM PST 24
Peak memory 201668 kb
Host smart-565b7820-db82-4f03-adf2-75b2490f5def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387281227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1387281227
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4002761425
Short name T35
Test name
Test status
Simulation time 427576628943 ps
CPU time 713.87 seconds
Started Feb 04 01:05:49 PM PST 24
Finished Feb 04 01:17:44 PM PST 24
Peak memory 210352 kb
Host smart-0789b249-6d07-4521-9eaf-e2c2778895a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002761425 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4002761425
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.723975407
Short name T133
Test name
Test status
Simulation time 332337400379 ps
CPU time 196.05 seconds
Started Feb 04 01:07:13 PM PST 24
Finished Feb 04 01:10:36 PM PST 24
Peak memory 201700 kb
Host smart-ee686edf-0621-45b0-b383-87715c02f890
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723975407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.723975407
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1539860993
Short name T218
Test name
Test status
Simulation time 490801981090 ps
CPU time 1226.52 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:24:49 PM PST 24
Peak memory 201536 kb
Host smart-384b2a8e-19e5-48ad-a56b-61c1d3f4b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539860993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1539860993
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2640535765
Short name T257
Test name
Test status
Simulation time 329251716713 ps
CPU time 690.82 seconds
Started Feb 04 01:04:39 PM PST 24
Finished Feb 04 01:16:14 PM PST 24
Peak memory 201624 kb
Host smart-4e8ff4de-8255-4d86-b800-5864450f025f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640535765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2640535765
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.417176389
Short name T42
Test name
Test status
Simulation time 8157073931 ps
CPU time 18.36 seconds
Started Feb 04 01:03:51 PM PST 24
Finished Feb 04 01:04:10 PM PST 24
Peak memory 217776 kb
Host smart-9293dca5-653a-4e82-aca1-2c76d11dd252
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417176389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.417176389
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3324902290
Short name T277
Test name
Test status
Simulation time 504608957343 ps
CPU time 289.29 seconds
Started Feb 04 01:05:00 PM PST 24
Finished Feb 04 01:09:54 PM PST 24
Peak memory 201748 kb
Host smart-a225b155-c53b-475b-8a6c-939b8a2be3fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324902290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3324902290
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.356412232
Short name T292
Test name
Test status
Simulation time 331474155388 ps
CPU time 773.2 seconds
Started Feb 04 01:03:19 PM PST 24
Finished Feb 04 01:16:14 PM PST 24
Peak memory 201584 kb
Host smart-95f73c31-74f8-4e28-8d54-736bab0813ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356412232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.356412232
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3092808076
Short name T284
Test name
Test status
Simulation time 113283296929 ps
CPU time 163.54 seconds
Started Feb 04 01:05:02 PM PST 24
Finished Feb 04 01:07:52 PM PST 24
Peak memory 210288 kb
Host smart-b40dc566-0381-48f1-a285-dce827fd686d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092808076 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3092808076
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.4093741774
Short name T147
Test name
Test status
Simulation time 511115659923 ps
CPU time 652.86 seconds
Started Feb 04 01:06:45 PM PST 24
Finished Feb 04 01:17:42 PM PST 24
Peak memory 201676 kb
Host smart-f693fed7-6beb-44b5-95a7-19ff71a41632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093741774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.4093741774
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1680094991
Short name T75
Test name
Test status
Simulation time 696237922 ps
CPU time 2.69 seconds
Started Feb 04 12:40:17 PM PST 24
Finished Feb 04 12:40:32 PM PST 24
Peak memory 201484 kb
Host smart-1e4244e0-91e9-4a77-8254-97de906ee13a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680094991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1680094991
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3218861569
Short name T246
Test name
Test status
Simulation time 578009647870 ps
CPU time 1606.29 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:35:53 PM PST 24
Peak memory 201784 kb
Host smart-b808aae3-d3cb-49ec-ad18-f7d6ead4e7b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218861569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3218861569
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.4000478683
Short name T253
Test name
Test status
Simulation time 487601240288 ps
CPU time 289.99 seconds
Started Feb 04 01:03:52 PM PST 24
Finished Feb 04 01:08:43 PM PST 24
Peak memory 201680 kb
Host smart-e53c1964-8ebd-4e86-888e-54baaa5fd99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000478683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.4000478683
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1562351151
Short name T118
Test name
Test status
Simulation time 328198017130 ps
CPU time 364.41 seconds
Started Feb 04 01:05:02 PM PST 24
Finished Feb 04 01:11:13 PM PST 24
Peak memory 201012 kb
Host smart-b597e837-e899-4ccd-9bc1-64044c151cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562351151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1562351151
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2916685031
Short name T263
Test name
Test status
Simulation time 485348253579 ps
CPU time 1014.67 seconds
Started Feb 04 01:03:32 PM PST 24
Finished Feb 04 01:20:31 PM PST 24
Peak memory 201648 kb
Host smart-4157f405-d692-4737-aa5c-bb6549f2a67b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916685031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2916685031
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4133338160
Short name T160
Test name
Test status
Simulation time 179354385794 ps
CPU time 462.91 seconds
Started Feb 04 01:07:28 PM PST 24
Finished Feb 04 01:15:15 PM PST 24
Peak memory 218408 kb
Host smart-968af2a7-ba8b-448e-8b13-c5a7a385b0b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133338160 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4133338160
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.12836424
Short name T326
Test name
Test status
Simulation time 329702609381 ps
CPU time 791.16 seconds
Started Feb 04 01:07:26 PM PST 24
Finished Feb 04 01:20:44 PM PST 24
Peak memory 201684 kb
Host smart-86703145-bff6-4bca-aca7-7757535ca0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12836424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.12836424
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.710323054
Short name T282
Test name
Test status
Simulation time 222382962509 ps
CPU time 264.03 seconds
Started Feb 04 01:04:48 PM PST 24
Finished Feb 04 01:09:20 PM PST 24
Peak memory 210612 kb
Host smart-f3a7dbed-e25f-4ee9-9ec9-3a9ab5cbaabf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710323054 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.710323054
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.569986414
Short name T114
Test name
Test status
Simulation time 490750973486 ps
CPU time 1111.93 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:27:38 PM PST 24
Peak memory 201648 kb
Host smart-a95799bb-e969-49e2-ae99-f25b311a5e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569986414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.569986414
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1938401689
Short name T92
Test name
Test status
Simulation time 392372181067 ps
CPU time 642.56 seconds
Started Feb 04 01:08:10 PM PST 24
Finished Feb 04 01:18:53 PM PST 24
Peak memory 212232 kb
Host smart-7056625d-bf31-4521-8c93-253b81f2f0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938401689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1938401689
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.53687900
Short name T251
Test name
Test status
Simulation time 491367168725 ps
CPU time 1192.89 seconds
Started Feb 04 01:04:38 PM PST 24
Finished Feb 04 01:24:36 PM PST 24
Peak memory 201712 kb
Host smart-96bac66d-9fd0-459a-810f-f5fec5b35c90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53687900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gatin
g.53687900
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4144537414
Short name T138
Test name
Test status
Simulation time 483566146983 ps
CPU time 1109.39 seconds
Started Feb 04 01:04:17 PM PST 24
Finished Feb 04 01:22:48 PM PST 24
Peak memory 201600 kb
Host smart-2a626576-2969-41d4-b4da-c4a1324615d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144537414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4144537414
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2832221484
Short name T287
Test name
Test status
Simulation time 40879385925 ps
CPU time 83.89 seconds
Started Feb 04 01:08:13 PM PST 24
Finished Feb 04 01:09:38 PM PST 24
Peak memory 209828 kb
Host smart-41bfcac1-acc2-438e-9cb2-c816c7df3281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832221484 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2832221484
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.437109440
Short name T36
Test name
Test status
Simulation time 528479835 ps
CPU time 2.6 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:36 PM PST 24
Peak memory 201372 kb
Host smart-7849c9f2-3dfd-40da-9d44-497f1e284d96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437109440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.437109440
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3533606212
Short name T139
Test name
Test status
Simulation time 356113706064 ps
CPU time 210.28 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:07:52 PM PST 24
Peak memory 201492 kb
Host smart-a2bc5e18-3ae2-4866-865d-80b5cfee49ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533606212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3533606212
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2848909341
Short name T198
Test name
Test status
Simulation time 253711675351 ps
CPU time 520.6 seconds
Started Feb 04 01:04:16 PM PST 24
Finished Feb 04 01:12:58 PM PST 24
Peak memory 217640 kb
Host smart-c3d56202-6b78-4bd3-8221-591a90cb5b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848909341 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2848909341
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2831429109
Short name T315
Test name
Test status
Simulation time 234955473032 ps
CPU time 135.05 seconds
Started Feb 04 01:07:48 PM PST 24
Finished Feb 04 01:10:06 PM PST 24
Peak memory 201664 kb
Host smart-abee46bd-9830-4a50-a9b1-9337c9098838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831429109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2831429109
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1571876544
Short name T267
Test name
Test status
Simulation time 550998417674 ps
CPU time 270.5 seconds
Started Feb 04 01:09:12 PM PST 24
Finished Feb 04 01:13:44 PM PST 24
Peak memory 218396 kb
Host smart-0689a16d-a932-4dfa-aa23-e5113b7bdb4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571876544 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1571876544
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3813714643
Short name T270
Test name
Test status
Simulation time 338857981159 ps
CPU time 751.72 seconds
Started Feb 04 01:03:56 PM PST 24
Finished Feb 04 01:16:28 PM PST 24
Peak memory 201548 kb
Host smart-afaabdd0-6e75-41d7-a530-b4ac138b3234
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813714643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3813714643
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3932930184
Short name T428
Test name
Test status
Simulation time 165355463253 ps
CPU time 362.72 seconds
Started Feb 04 01:03:16 PM PST 24
Finished Feb 04 01:09:22 PM PST 24
Peak memory 201596 kb
Host smart-1c6838c8-9291-48c3-bbf3-f3f81c714124
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932930184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3932930184
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2254359776
Short name T117
Test name
Test status
Simulation time 163495806750 ps
CPU time 207.73 seconds
Started Feb 04 01:04:31 PM PST 24
Finished Feb 04 01:08:00 PM PST 24
Peak memory 201624 kb
Host smart-2794e252-df2a-4a50-abf9-21890f4f27a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254359776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2254359776
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2987634901
Short name T310
Test name
Test status
Simulation time 493116876363 ps
CPU time 1082.4 seconds
Started Feb 04 01:09:13 PM PST 24
Finished Feb 04 01:27:17 PM PST 24
Peak memory 201696 kb
Host smart-3fd72c8a-f638-4b01-86a3-611fe79be62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987634901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2987634901
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.69384241
Short name T355
Test name
Test status
Simulation time 340880029104 ps
CPU time 172.28 seconds
Started Feb 04 01:03:09 PM PST 24
Finished Feb 04 01:06:04 PM PST 24
Peak memory 201556 kb
Host smart-5bc8a2e5-c055-4c2c-b882-a347e91a7074
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69384241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wa
keup.69384241
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.4293608672
Short name T142
Test name
Test status
Simulation time 323171372352 ps
CPU time 620.06 seconds
Started Feb 04 01:06:41 PM PST 24
Finished Feb 04 01:17:07 PM PST 24
Peak memory 201324 kb
Host smart-88fab8b8-230c-44e8-ae83-855a4b73e9c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293608672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.4293608672
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3563792919
Short name T300
Test name
Test status
Simulation time 235553590340 ps
CPU time 345.29 seconds
Started Feb 04 01:09:17 PM PST 24
Finished Feb 04 01:15:03 PM PST 24
Peak memory 210344 kb
Host smart-5291d368-6e20-4fd3-92bc-68bc48a2110d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563792919 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3563792919
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2076377512
Short name T258
Test name
Test status
Simulation time 324321520300 ps
CPU time 360.86 seconds
Started Feb 04 01:04:00 PM PST 24
Finished Feb 04 01:10:02 PM PST 24
Peak memory 201572 kb
Host smart-0a048986-dd18-4521-a9d5-c228bb21ff84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076377512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2076377512
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2518417925
Short name T2
Test name
Test status
Simulation time 8559256599 ps
CPU time 21.68 seconds
Started Feb 04 12:40:55 PM PST 24
Finished Feb 04 12:41:24 PM PST 24
Peak memory 201744 kb
Host smart-6392f373-e770-4b8a-b0f6-30da3474fdda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518417925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2518417925
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.922508188
Short name T442
Test name
Test status
Simulation time 316960750 ps
CPU time 0.93 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:04:56 PM PST 24
Peak memory 201184 kb
Host smart-e8d3efa0-7ecf-4bfa-8501-d679b51a8f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922508188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.922508188
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3677898635
Short name T148
Test name
Test status
Simulation time 504732935584 ps
CPU time 236.38 seconds
Started Feb 04 01:03:15 PM PST 24
Finished Feb 04 01:07:12 PM PST 24
Peak memory 201576 kb
Host smart-485f8a92-b583-4b4b-9839-77ffb0359f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677898635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3677898635
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3967771740
Short name T105
Test name
Test status
Simulation time 335259160474 ps
CPU time 152.34 seconds
Started Feb 04 01:04:17 PM PST 24
Finished Feb 04 01:06:51 PM PST 24
Peak memory 201568 kb
Host smart-b5320829-5cb0-4231-a3ba-815cef51d0d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967771740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3967771740
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3600794674
Short name T318
Test name
Test status
Simulation time 523263761425 ps
CPU time 1231.07 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:24:53 PM PST 24
Peak memory 201656 kb
Host smart-5842b533-c05e-4328-9d6e-4a01efab9ddd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600794674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3600794674
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.769023869
Short name T238
Test name
Test status
Simulation time 354596548869 ps
CPU time 403.1 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:10:04 PM PST 24
Peak memory 201184 kb
Host smart-9092e3ce-518f-4bed-83d3-e25bc5975233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769023869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.769023869
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.934287230
Short name T293
Test name
Test status
Simulation time 492658095580 ps
CPU time 939.14 seconds
Started Feb 04 01:05:15 PM PST 24
Finished Feb 04 01:20:56 PM PST 24
Peak memory 201640 kb
Host smart-24622663-96e9-4863-a3df-dc5d6a38e09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934287230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.934287230
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1372314569
Short name T193
Test name
Test status
Simulation time 92443097636 ps
CPU time 287.23 seconds
Started Feb 04 01:05:23 PM PST 24
Finished Feb 04 01:10:13 PM PST 24
Peak memory 201468 kb
Host smart-21b30c8f-88ca-4c67-a1e2-622cb28f6dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372314569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1372314569
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3869560978
Short name T213
Test name
Test status
Simulation time 501029284435 ps
CPU time 1167.89 seconds
Started Feb 04 01:06:07 PM PST 24
Finished Feb 04 01:25:44 PM PST 24
Peak memory 201620 kb
Host smart-ee045858-f872-4768-bfd8-c1b0583dfe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869560978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3869560978
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4065123548
Short name T313
Test name
Test status
Simulation time 488455591040 ps
CPU time 493.07 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:17:20 PM PST 24
Peak memory 201576 kb
Host smart-0e7fb61a-2e8c-4046-aff6-6efa6bde22e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065123548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4065123548
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3801988017
Short name T196
Test name
Test status
Simulation time 130456350484 ps
CPU time 586.3 seconds
Started Feb 04 01:04:34 PM PST 24
Finished Feb 04 01:14:23 PM PST 24
Peak memory 201880 kb
Host smart-46f2f5df-9cd3-4c8d-944b-0354c99d2c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801988017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3801988017
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3482610742
Short name T835
Test name
Test status
Simulation time 327440134522 ps
CPU time 731 seconds
Started Feb 04 01:04:34 PM PST 24
Finished Feb 04 01:16:48 PM PST 24
Peak memory 201552 kb
Host smart-716509fc-7a6d-403d-9ecc-5ce7e231b0cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482610742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3482610742
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2019470601
Short name T214
Test name
Test status
Simulation time 158759916112 ps
CPU time 97.24 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:06:33 PM PST 24
Peak memory 201484 kb
Host smart-559eeddf-331f-4bc9-999a-37dc46c8b75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019470601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2019470601
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2310847873
Short name T209
Test name
Test status
Simulation time 117651738862 ps
CPU time 556.78 seconds
Started Feb 04 01:03:43 PM PST 24
Finished Feb 04 01:13:02 PM PST 24
Peak memory 201896 kb
Host smart-de44da1e-765e-46d3-aec0-f62b44611fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310847873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2310847873
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3682078137
Short name T342
Test name
Test status
Simulation time 489170686528 ps
CPU time 336.9 seconds
Started Feb 04 01:06:19 PM PST 24
Finished Feb 04 01:11:57 PM PST 24
Peak memory 201520 kb
Host smart-d96e9b90-7b20-4002-a5db-28c5f4d0d94a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682078137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3682078137
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.976977083
Short name T249
Test name
Test status
Simulation time 29615066354 ps
CPU time 49.81 seconds
Started Feb 04 01:06:30 PM PST 24
Finished Feb 04 01:07:20 PM PST 24
Peak memory 201780 kb
Host smart-7e077fda-ed66-48c2-8af4-0cdba5db4b8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976977083 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.976977083
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.72709978
Short name T350
Test name
Test status
Simulation time 495274572850 ps
CPU time 1066.89 seconds
Started Feb 04 01:07:50 PM PST 24
Finished Feb 04 01:25:39 PM PST 24
Peak memory 201604 kb
Host smart-dc4411bd-d929-4a11-b6b9-ce8c15902d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72709978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.72709978
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2111172431
Short name T394
Test name
Test status
Simulation time 652371072 ps
CPU time 2.08 seconds
Started Feb 04 12:40:16 PM PST 24
Finished Feb 04 12:40:30 PM PST 24
Peak memory 201620 kb
Host smart-72018b86-93ba-4b40-9a5d-f6f62bd624cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111172431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2111172431
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2309948198
Short name T364
Test name
Test status
Simulation time 8025424179 ps
CPU time 7.19 seconds
Started Feb 04 12:40:17 PM PST 24
Finished Feb 04 12:40:36 PM PST 24
Peak memory 201688 kb
Host smart-b04abf2a-7dd1-48f3-bed0-45691e77817e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309948198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2309948198
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.16087593
Short name T207
Test name
Test status
Simulation time 644952026485 ps
CPU time 607.11 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:14:29 PM PST 24
Peak memory 210364 kb
Host smart-f229d759-f5d0-4338-bbe1-f7ef3a69177e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16087593 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.16087593
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3462188845
Short name T206
Test name
Test status
Simulation time 81309815172 ps
CPU time 330.5 seconds
Started Feb 04 01:04:21 PM PST 24
Finished Feb 04 01:09:53 PM PST 24
Peak memory 201896 kb
Host smart-f0ed978a-9e11-401a-b562-8fbd089e5f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462188845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3462188845
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2010016153
Short name T256
Test name
Test status
Simulation time 162305253078 ps
CPU time 360.67 seconds
Started Feb 04 01:04:35 PM PST 24
Finished Feb 04 01:10:40 PM PST 24
Peak memory 201644 kb
Host smart-3c64f2e3-3eea-4681-8a1c-53b763fbc824
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010016153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2010016153
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1501014904
Short name T368
Test name
Test status
Simulation time 106965501883 ps
CPU time 332.67 seconds
Started Feb 04 01:04:35 PM PST 24
Finished Feb 04 01:10:12 PM PST 24
Peak memory 201880 kb
Host smart-e6e7b301-6202-4efb-8e7b-13e385e2dd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501014904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1501014904
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2014045534
Short name T203
Test name
Test status
Simulation time 385565410985 ps
CPU time 879.79 seconds
Started Feb 04 01:04:39 PM PST 24
Finished Feb 04 01:19:23 PM PST 24
Peak memory 211696 kb
Host smart-5115e621-0b81-4469-8ae5-1f7037a953da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014045534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2014045534
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1420879667
Short name T236
Test name
Test status
Simulation time 158497387323 ps
CPU time 396.93 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:11:32 PM PST 24
Peak memory 201512 kb
Host smart-c208a79d-4f7f-48c7-a980-1f3d762cd682
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420879667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1420879667
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.363552791
Short name T353
Test name
Test status
Simulation time 345560935170 ps
CPU time 755.04 seconds
Started Feb 04 01:04:40 PM PST 24
Finished Feb 04 01:17:24 PM PST 24
Peak memory 201612 kb
Host smart-6789758e-3785-4eb9-a5a2-ab233cd5ce9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363552791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.363552791
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3877385229
Short name T371
Test name
Test status
Simulation time 130914428527 ps
CPU time 306.25 seconds
Started Feb 04 01:04:42 PM PST 24
Finished Feb 04 01:09:57 PM PST 24
Peak memory 210384 kb
Host smart-76570ac1-8398-4f2c-9aab-9a6fd21fdcb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877385229 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3877385229
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1363631744
Short name T314
Test name
Test status
Simulation time 164290849857 ps
CPU time 98.62 seconds
Started Feb 04 01:05:32 PM PST 24
Finished Feb 04 01:07:16 PM PST 24
Peak memory 201680 kb
Host smart-26351464-2472-47d6-96cd-aaa024ae9f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363631744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1363631744
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3864153879
Short name T344
Test name
Test status
Simulation time 327498513619 ps
CPU time 686.39 seconds
Started Feb 04 01:06:06 PM PST 24
Finished Feb 04 01:17:41 PM PST 24
Peak memory 201588 kb
Host smart-4859f339-01cb-4ec6-8df4-30cab3d18abb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864153879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3864153879
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3777721387
Short name T298
Test name
Test status
Simulation time 121058733000 ps
CPU time 150.1 seconds
Started Feb 04 01:08:11 PM PST 24
Finished Feb 04 01:10:41 PM PST 24
Peak memory 210260 kb
Host smart-5fadff78-dd46-4ceb-ba72-321d65ff423f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777721387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3777721387
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2023491731
Short name T340
Test name
Test status
Simulation time 336774939094 ps
CPU time 175.61 seconds
Started Feb 04 01:04:04 PM PST 24
Finished Feb 04 01:07:02 PM PST 24
Peak memory 201608 kb
Host smart-8739ddf2-94db-4b27-b88a-26e4c5c5405e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023491731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2023491731
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1447969684
Short name T48
Test name
Test status
Simulation time 375485632625 ps
CPU time 55.54 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:05:17 PM PST 24
Peak memory 201592 kb
Host smart-f1becc69-f905-44f1-8905-6e75d648a900
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447969684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1447969684
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1047848207
Short name T73
Test name
Test status
Simulation time 3745521232 ps
CPU time 7.43 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:37 PM PST 24
Peak memory 201188 kb
Host smart-0a419428-f7e0-4ff1-84d3-de4afc508014
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047848207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1047848207
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2771444786
Short name T908
Test name
Test status
Simulation time 1138829224 ps
CPU time 3.22 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:36 PM PST 24
Peak memory 201260 kb
Host smart-d2ce8435-e582-4862-ac09-3a13190bf1b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771444786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2771444786
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1530097442
Short name T192
Test name
Test status
Simulation time 627973092 ps
CPU time 1.16 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:34 PM PST 24
Peak memory 201052 kb
Host smart-3a024d4e-862f-471c-8ecb-8f0e66854c21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530097442 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1530097442
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.847729191
Short name T875
Test name
Test status
Simulation time 411881969 ps
CPU time 1.51 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:33 PM PST 24
Peak memory 201316 kb
Host smart-6e5686ab-639e-4c7c-a115-d35d62c4e8c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847729191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.847729191
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.189761830
Short name T390
Test name
Test status
Simulation time 2200962294 ps
CPU time 2.54 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:34 PM PST 24
Peak memory 201468 kb
Host smart-b694dcd5-46c6-4d7a-af8b-c9af36976c6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189761830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.189761830
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.309682925
Short name T56
Test name
Test status
Simulation time 8511739942 ps
CPU time 17.24 seconds
Started Feb 04 12:40:10 PM PST 24
Finished Feb 04 12:40:41 PM PST 24
Peak memory 201648 kb
Host smart-05f8b596-2883-46b1-bb14-7702fc992394
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309682925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.309682925
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4107746427
Short name T70
Test name
Test status
Simulation time 1457714039 ps
CPU time 1.61 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:31 PM PST 24
Peak memory 201096 kb
Host smart-e3379ec4-2c9b-43c2-9bea-c9da5d83b767
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107746427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4107746427
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2171335295
Short name T411
Test name
Test status
Simulation time 26962662566 ps
CPU time 62.63 seconds
Started Feb 04 12:40:13 PM PST 24
Finished Feb 04 12:41:30 PM PST 24
Peak memory 201612 kb
Host smart-eaedc76d-ddc8-4ad4-b874-0fac7f5932ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171335295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2171335295
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2905563014
Short name T88
Test name
Test status
Simulation time 647759823 ps
CPU time 1.31 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:33 PM PST 24
Peak memory 201260 kb
Host smart-7dad6c0f-492f-4791-bb48-361735e10e94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905563014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2905563014
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.531540912
Short name T81
Test name
Test status
Simulation time 689557986 ps
CPU time 1.39 seconds
Started Feb 04 12:40:14 PM PST 24
Finished Feb 04 12:40:28 PM PST 24
Peak memory 201320 kb
Host smart-bf0210e5-10d4-435a-afad-d7313c4544c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531540912 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.531540912
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.192821125
Short name T33
Test name
Test status
Simulation time 506501576 ps
CPU time 0.83 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:32 PM PST 24
Peak memory 201208 kb
Host smart-6c49cdc5-f490-41d1-84bf-257b1ea7c89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192821125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.192821125
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2265181466
Short name T38
Test name
Test status
Simulation time 311605302 ps
CPU time 1.31 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:35 PM PST 24
Peak memory 201248 kb
Host smart-35e840e8-dc78-4b9f-a0f7-766c255e747d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265181466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2265181466
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2443705253
Short name T873
Test name
Test status
Simulation time 2155293193 ps
CPU time 8.55 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:38 PM PST 24
Peak memory 201468 kb
Host smart-6da76525-0467-4ccc-8be9-12b32aa7157f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443705253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2443705253
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.768423083
Short name T871
Test name
Test status
Simulation time 482899959 ps
CPU time 1.71 seconds
Started Feb 04 12:40:33 PM PST 24
Finished Feb 04 12:40:41 PM PST 24
Peak memory 201076 kb
Host smart-7cc43d5e-29d9-4f2c-934c-46c60ff9be33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768423083 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.768423083
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3763021593
Short name T28
Test name
Test status
Simulation time 472267774 ps
CPU time 1.81 seconds
Started Feb 04 12:40:37 PM PST 24
Finished Feb 04 12:40:43 PM PST 24
Peak memory 201332 kb
Host smart-c26f6df1-ea9a-4653-973d-c9aa54aaf9c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763021593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3763021593
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3635246991
Short name T909
Test name
Test status
Simulation time 388238781 ps
CPU time 0.89 seconds
Started Feb 04 12:40:38 PM PST 24
Finished Feb 04 12:40:42 PM PST 24
Peak memory 201020 kb
Host smart-79f49669-3f83-4be8-a09e-a7dae4bbefb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635246991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3635246991
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2086669680
Short name T889
Test name
Test status
Simulation time 2434515053 ps
CPU time 1.42 seconds
Started Feb 04 12:40:41 PM PST 24
Finished Feb 04 12:40:44 PM PST 24
Peak memory 201420 kb
Host smart-b0aad9a8-1463-4146-a14b-2a88c2c0e155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086669680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2086669680
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3893986075
Short name T895
Test name
Test status
Simulation time 501566982 ps
CPU time 1.83 seconds
Started Feb 04 12:40:36 PM PST 24
Finished Feb 04 12:40:42 PM PST 24
Peak memory 201600 kb
Host smart-1baf12cf-a179-40ee-a20e-dc23661d8e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893986075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3893986075
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2839759489
Short name T894
Test name
Test status
Simulation time 8086476900 ps
CPU time 7.13 seconds
Started Feb 04 12:40:36 PM PST 24
Finished Feb 04 12:40:47 PM PST 24
Peak memory 201680 kb
Host smart-cff85fb4-f422-46b1-ad90-f973e06f32bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839759489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2839759489
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3620167953
Short name T883
Test name
Test status
Simulation time 473720804 ps
CPU time 1.12 seconds
Started Feb 04 12:40:36 PM PST 24
Finished Feb 04 12:40:42 PM PST 24
Peak memory 201392 kb
Host smart-8349479f-7d66-4967-a345-abbaaf78e8b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620167953 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3620167953
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1748411830
Short name T86
Test name
Test status
Simulation time 484926665 ps
CPU time 1.34 seconds
Started Feb 04 12:40:39 PM PST 24
Finished Feb 04 12:40:43 PM PST 24
Peak memory 201304 kb
Host smart-7a89aded-96ff-4f8d-8809-fa89cb594f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748411830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1748411830
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4053093909
Short name T896
Test name
Test status
Simulation time 547527645 ps
CPU time 0.9 seconds
Started Feb 04 12:40:46 PM PST 24
Finished Feb 04 12:40:48 PM PST 24
Peak memory 200856 kb
Host smart-47d0e7d2-0131-45d2-9100-e86de86bc924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053093909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.4053093909
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3409835076
Short name T881
Test name
Test status
Simulation time 5105167348 ps
CPU time 5.97 seconds
Started Feb 04 12:40:37 PM PST 24
Finished Feb 04 12:40:47 PM PST 24
Peak memory 201176 kb
Host smart-bd7b0cff-f069-4b9c-b3eb-4eee235edb0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409835076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3409835076
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3729283242
Short name T62
Test name
Test status
Simulation time 822569887 ps
CPU time 2.85 seconds
Started Feb 04 12:40:27 PM PST 24
Finished Feb 04 12:40:40 PM PST 24
Peak memory 217888 kb
Host smart-6c8a95e5-281a-4c9b-a183-84634d1d3aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729283242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3729283242
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1030487194
Short name T30
Test name
Test status
Simulation time 4714382092 ps
CPU time 6.59 seconds
Started Feb 04 12:40:37 PM PST 24
Finished Feb 04 12:40:48 PM PST 24
Peak memory 201680 kb
Host smart-6c1b5972-e942-44e1-b9af-571227779c30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030487194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1030487194
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3228312004
Short name T417
Test name
Test status
Simulation time 432841159 ps
CPU time 1.4 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:05 PM PST 24
Peak memory 201380 kb
Host smart-4c9328f5-e377-438c-86e9-c8866bc5918f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228312004 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3228312004
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.708855962
Short name T912
Test name
Test status
Simulation time 359208073 ps
CPU time 1.53 seconds
Started Feb 04 12:40:42 PM PST 24
Finished Feb 04 12:40:45 PM PST 24
Peak memory 201252 kb
Host smart-7f5a1f71-85a9-41c6-b941-7dc4c47a3e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708855962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.708855962
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1762002264
Short name T64
Test name
Test status
Simulation time 456157929 ps
CPU time 1.73 seconds
Started Feb 04 12:40:34 PM PST 24
Finished Feb 04 12:40:41 PM PST 24
Peak memory 201168 kb
Host smart-10573982-300e-471c-b8d4-a841ce4491ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762002264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1762002264
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.156063788
Short name T412
Test name
Test status
Simulation time 4780459674 ps
CPU time 11.22 seconds
Started Feb 04 12:40:46 PM PST 24
Finished Feb 04 12:40:58 PM PST 24
Peak memory 201708 kb
Host smart-4d36f06f-5914-45e9-929f-5d5c0cf0991d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156063788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.156063788
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3728287851
Short name T902
Test name
Test status
Simulation time 597811055 ps
CPU time 3.46 seconds
Started Feb 04 12:40:33 PM PST 24
Finished Feb 04 12:40:43 PM PST 24
Peak memory 209696 kb
Host smart-13345a2e-247a-4793-be8f-f5a9a3dec439
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728287851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3728287851
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1635399109
Short name T878
Test name
Test status
Simulation time 7827500388 ps
CPU time 20.69 seconds
Started Feb 04 12:40:46 PM PST 24
Finished Feb 04 12:41:08 PM PST 24
Peak memory 201404 kb
Host smart-7bd5a42b-2625-40d5-bd9e-d43a6ddf4229
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635399109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1635399109
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4069173974
Short name T385
Test name
Test status
Simulation time 501660359 ps
CPU time 1.92 seconds
Started Feb 04 12:41:10 PM PST 24
Finished Feb 04 12:41:14 PM PST 24
Peak memory 201352 kb
Host smart-ada4f076-84ee-4b4c-b67f-46521487ebb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069173974 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4069173974
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.833869573
Short name T890
Test name
Test status
Simulation time 470864152 ps
CPU time 1.65 seconds
Started Feb 04 12:41:04 PM PST 24
Finished Feb 04 12:41:08 PM PST 24
Peak memory 201344 kb
Host smart-cc52c9ee-9522-4bda-b40c-4c296af41eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833869573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.833869573
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1655278183
Short name T900
Test name
Test status
Simulation time 325062718 ps
CPU time 1.44 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:05 PM PST 24
Peak memory 200432 kb
Host smart-93ca9bbc-c3c1-472d-88c9-a08a3210aac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655278183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1655278183
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2986444425
Short name T904
Test name
Test status
Simulation time 3846281372 ps
CPU time 4.31 seconds
Started Feb 04 12:41:17 PM PST 24
Finished Feb 04 12:41:28 PM PST 24
Peak memory 201584 kb
Host smart-8a7110b6-785a-4096-b696-9ecb10a0d405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986444425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2986444425
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.324855957
Short name T386
Test name
Test status
Simulation time 458342555 ps
CPU time 3.25 seconds
Started Feb 04 12:41:01 PM PST 24
Finished Feb 04 12:41:09 PM PST 24
Peak memory 201656 kb
Host smart-096f6ae3-4a16-4aa1-aebb-6de51859737b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324855957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.324855957
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2311827377
Short name T406
Test name
Test status
Simulation time 4385475836 ps
CPU time 10.31 seconds
Started Feb 04 12:40:59 PM PST 24
Finished Feb 04 12:41:13 PM PST 24
Peak memory 201688 kb
Host smart-8d8f886e-8842-4d1b-b8e8-55d69e15ba69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311827377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2311827377
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2051874406
Short name T372
Test name
Test status
Simulation time 459594949 ps
CPU time 1.36 seconds
Started Feb 04 12:41:09 PM PST 24
Finished Feb 04 12:41:12 PM PST 24
Peak memory 201432 kb
Host smart-4cb77493-9d3c-416e-be7b-ebd880f61d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051874406 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2051874406
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.572394629
Short name T899
Test name
Test status
Simulation time 467539667 ps
CPU time 0.99 seconds
Started Feb 04 12:40:57 PM PST 24
Finished Feb 04 12:41:03 PM PST 24
Peak memory 201348 kb
Host smart-afd146f8-cd0b-423f-90c5-75daf8108617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572394629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.572394629
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4291736285
Short name T416
Test name
Test status
Simulation time 565283999 ps
CPU time 0.83 seconds
Started Feb 04 12:41:09 PM PST 24
Finished Feb 04 12:41:11 PM PST 24
Peak memory 201172 kb
Host smart-43ed1e0c-9000-4c4c-8d79-47a5b01dd11a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291736285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.4291736285
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2621643543
Short name T893
Test name
Test status
Simulation time 4657139536 ps
CPU time 11.42 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:14 PM PST 24
Peak memory 201716 kb
Host smart-eaec7d5b-a65e-4911-a2f8-3e446c5e2dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621643543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2621643543
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3850527766
Short name T404
Test name
Test status
Simulation time 372228742 ps
CPU time 2.04 seconds
Started Feb 04 12:40:57 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201520 kb
Host smart-79aa93cb-2c0f-402b-be0b-52e3a86b17e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850527766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3850527766
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2594264414
Short name T59
Test name
Test status
Simulation time 4450228334 ps
CPU time 11.67 seconds
Started Feb 04 12:40:58 PM PST 24
Finished Feb 04 12:41:14 PM PST 24
Peak memory 201588 kb
Host smart-7bad9434-021a-41ff-bdf0-4e469d316681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594264414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2594264414
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2113871274
Short name T884
Test name
Test status
Simulation time 479147696 ps
CPU time 1.81 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:05 PM PST 24
Peak memory 201380 kb
Host smart-b19dc16a-4e18-4095-b77c-f9289967c92d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113871274 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2113871274
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.807545237
Short name T84
Test name
Test status
Simulation time 514756820 ps
CPU time 1.5 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201324 kb
Host smart-7b24d502-c5e4-4091-a42a-7d0811598ef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807545237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.807545237
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.658562103
Short name T409
Test name
Test status
Simulation time 432833167 ps
CPU time 1.59 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:05 PM PST 24
Peak memory 200524 kb
Host smart-1ae06e0e-6a5b-4b75-91eb-702fba3955b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658562103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.658562103
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1453010435
Short name T68
Test name
Test status
Simulation time 2527694897 ps
CPU time 2.79 seconds
Started Feb 04 12:40:54 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201392 kb
Host smart-d011ba4a-fad3-40ed-8ea8-855c9d07d093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453010435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1453010435
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3202856947
Short name T58
Test name
Test status
Simulation time 603387043 ps
CPU time 2.15 seconds
Started Feb 04 12:41:10 PM PST 24
Finished Feb 04 12:41:14 PM PST 24
Peak memory 201572 kb
Host smart-88f26035-08d8-42d4-a393-51695f65a84e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202856947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3202856947
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1478496973
Short name T61
Test name
Test status
Simulation time 8898363337 ps
CPU time 7.57 seconds
Started Feb 04 12:40:59 PM PST 24
Finished Feb 04 12:41:10 PM PST 24
Peak memory 201712 kb
Host smart-da3b28db-e6ef-452e-92ce-ea2fa72d73bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478496973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1478496973
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2136477840
Short name T389
Test name
Test status
Simulation time 382247206 ps
CPU time 0.94 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201376 kb
Host smart-c85c5b86-274f-4ae4-93a3-26a1cc5a4697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136477840 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2136477840
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4219424523
Short name T870
Test name
Test status
Simulation time 591933262 ps
CPU time 1.11 seconds
Started Feb 04 12:41:10 PM PST 24
Finished Feb 04 12:41:13 PM PST 24
Peak memory 201292 kb
Host smart-00ff2694-99e1-4c8e-acbb-b5daa9847ab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219424523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4219424523
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2424847349
Short name T41
Test name
Test status
Simulation time 330286384 ps
CPU time 1.38 seconds
Started Feb 04 12:41:11 PM PST 24
Finished Feb 04 12:41:14 PM PST 24
Peak memory 201012 kb
Host smart-38cf1479-ac18-4fcd-8328-3c057c8126f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424847349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2424847349
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.708602371
Short name T396
Test name
Test status
Simulation time 2206021290 ps
CPU time 2.12 seconds
Started Feb 04 12:41:10 PM PST 24
Finished Feb 04 12:41:14 PM PST 24
Peak memory 201408 kb
Host smart-169ba9e3-dd0e-40a7-9b01-ad2a4c86f1af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708602371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.708602371
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2924571260
Short name T882
Test name
Test status
Simulation time 487165841 ps
CPU time 2.38 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:05 PM PST 24
Peak memory 201540 kb
Host smart-aaf2a611-a279-4046-8409-c50c2f519b75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924571260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2924571260
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1510127805
Short name T1
Test name
Test status
Simulation time 5441427213 ps
CPU time 2.07 seconds
Started Feb 04 12:41:03 PM PST 24
Finished Feb 04 12:41:09 PM PST 24
Peak memory 201700 kb
Host smart-8ce51a9d-8458-4d95-b1fc-6b47ca58fae6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510127805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1510127805
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.436087554
Short name T384
Test name
Test status
Simulation time 609844295 ps
CPU time 1.46 seconds
Started Feb 04 12:41:02 PM PST 24
Finished Feb 04 12:41:08 PM PST 24
Peak memory 201412 kb
Host smart-2426b7c7-5737-432d-a9e5-8114fa31099f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436087554 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.436087554
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1022020479
Short name T67
Test name
Test status
Simulation time 313635294 ps
CPU time 1.49 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201308 kb
Host smart-0b0fa7fb-8383-4f25-a9fd-db70d6d62bc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022020479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1022020479
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4125422339
Short name T419
Test name
Test status
Simulation time 457481202 ps
CPU time 1.14 seconds
Started Feb 04 12:40:54 PM PST 24
Finished Feb 04 12:41:02 PM PST 24
Peak memory 201092 kb
Host smart-80fb7205-837b-43d1-aeee-a160b34aadf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125422339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4125422339
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1444492289
Short name T424
Test name
Test status
Simulation time 4383618160 ps
CPU time 11.19 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:15 PM PST 24
Peak memory 201688 kb
Host smart-1c467dda-e7c2-4006-bbbf-1f6048123d75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444492289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1444492289
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1608835734
Short name T423
Test name
Test status
Simulation time 545398372 ps
CPU time 1.62 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201608 kb
Host smart-2f878697-3f24-4bea-9ab4-0d971a67b309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608835734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1608835734
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.651092226
Short name T4
Test name
Test status
Simulation time 10409827036 ps
CPU time 4.13 seconds
Started Feb 04 12:41:02 PM PST 24
Finished Feb 04 12:41:10 PM PST 24
Peak memory 201716 kb
Host smart-af79548c-f225-490e-ae32-9cc128f5726f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651092226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.651092226
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3961685937
Short name T887
Test name
Test status
Simulation time 575866681 ps
CPU time 1.2 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201388 kb
Host smart-77b64ab4-5dc8-462e-9e64-8c5a0b536e1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961685937 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3961685937
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1148160891
Short name T74
Test name
Test status
Simulation time 509961866 ps
CPU time 0.91 seconds
Started Feb 04 12:40:57 PM PST 24
Finished Feb 04 12:41:03 PM PST 24
Peak memory 201252 kb
Host smart-1d93c2dc-55e9-4106-8d5b-f6feafef1d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148160891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1148160891
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1077813881
Short name T9
Test name
Test status
Simulation time 2716744884 ps
CPU time 6.13 seconds
Started Feb 04 12:40:59 PM PST 24
Finished Feb 04 12:41:09 PM PST 24
Peak memory 201416 kb
Host smart-a0f6c235-35b0-467e-a8c2-9d6fca7840e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077813881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1077813881
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.48408858
Short name T60
Test name
Test status
Simulation time 818203569 ps
CPU time 2.75 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:06 PM PST 24
Peak memory 209824 kb
Host smart-ddeb5c6b-53ac-4f34-82d9-5a35f5eb4fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48408858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.48408858
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2703451718
Short name T905
Test name
Test status
Simulation time 8402521839 ps
CPU time 20.81 seconds
Started Feb 04 12:40:58 PM PST 24
Finished Feb 04 12:41:23 PM PST 24
Peak memory 201592 kb
Host smart-9fa9dd75-b88c-4f9a-9706-0c0e9af0a0a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703451718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2703451718
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4079730533
Short name T418
Test name
Test status
Simulation time 409843203 ps
CPU time 1.3 seconds
Started Feb 04 12:41:03 PM PST 24
Finished Feb 04 12:41:08 PM PST 24
Peak memory 201424 kb
Host smart-75dd81b1-7340-40e7-94de-ca5662e020c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079730533 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.4079730533
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3849147286
Short name T71
Test name
Test status
Simulation time 405708773 ps
CPU time 1.71 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:05 PM PST 24
Peak memory 201260 kb
Host smart-24d785d3-d45e-41fd-b5bd-cb0ae382d084
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849147286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3849147286
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1551393195
Short name T399
Test name
Test status
Simulation time 447483851 ps
CPU time 0.72 seconds
Started Feb 04 12:41:02 PM PST 24
Finished Feb 04 12:41:07 PM PST 24
Peak memory 201060 kb
Host smart-81d479b5-1625-46bb-8181-2aef6fe17f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551393195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1551393195
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2106972106
Short name T87
Test name
Test status
Simulation time 3000104274 ps
CPU time 2.43 seconds
Started Feb 04 12:41:09 PM PST 24
Finished Feb 04 12:41:12 PM PST 24
Peak memory 201468 kb
Host smart-d6cb4355-a75d-4201-945b-f1c1df838ed8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106972106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2106972106
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2720693815
Short name T393
Test name
Test status
Simulation time 416167658 ps
CPU time 2.86 seconds
Started Feb 04 12:41:10 PM PST 24
Finished Feb 04 12:41:15 PM PST 24
Peak memory 201512 kb
Host smart-c9be8dba-d78c-43ed-9244-659b7ee558e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720693815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2720693815
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1192080900
Short name T83
Test name
Test status
Simulation time 998353744 ps
CPU time 5.22 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:37 PM PST 24
Peak memory 201416 kb
Host smart-940cd852-95b8-47bc-9589-c0b6eede3c8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192080900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1192080900
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1450332075
Short name T379
Test name
Test status
Simulation time 52890292190 ps
CPU time 125.6 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:42:39 PM PST 24
Peak memory 201824 kb
Host smart-7fbf4096-8611-4e2b-8130-6f3bcdf0cec2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450332075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1450332075
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3778781767
Short name T25
Test name
Test status
Simulation time 807409505 ps
CPU time 2.82 seconds
Started Feb 04 12:40:14 PM PST 24
Finished Feb 04 12:40:30 PM PST 24
Peak memory 201236 kb
Host smart-30555879-2b92-4478-a15e-5029b4adc6f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778781767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3778781767
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.542558858
Short name T10
Test name
Test status
Simulation time 584262896 ps
CPU time 1.27 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:31 PM PST 24
Peak memory 201596 kb
Host smart-db7aa114-0217-4a48-ae35-09f8e5057566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542558858 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.542558858
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1860410295
Short name T66
Test name
Test status
Simulation time 466920133 ps
CPU time 1.86 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:33 PM PST 24
Peak memory 201352 kb
Host smart-c4e22093-0c92-47e3-bd27-34c4dbb76e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860410295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1860410295
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1733619737
Short name T26
Test name
Test status
Simulation time 304041973 ps
CPU time 1.3 seconds
Started Feb 04 12:40:17 PM PST 24
Finished Feb 04 12:40:30 PM PST 24
Peak memory 201148 kb
Host smart-8e86b427-e9ab-43db-82fb-57ee7632f2a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733619737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1733619737
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1316576523
Short name T381
Test name
Test status
Simulation time 5395917517 ps
CPU time 6.65 seconds
Started Feb 04 12:40:17 PM PST 24
Finished Feb 04 12:40:35 PM PST 24
Peak memory 201532 kb
Host smart-a2cf62f2-d347-437d-b1bf-633165ab294a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316576523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1316576523
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4263828200
Short name T90
Test name
Test status
Simulation time 657151957 ps
CPU time 1.92 seconds
Started Feb 04 12:40:12 PM PST 24
Finished Feb 04 12:40:29 PM PST 24
Peak memory 201544 kb
Host smart-eeb26a59-af36-46bc-8257-64be3b38ce15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263828200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4263828200
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2496536425
Short name T876
Test name
Test status
Simulation time 8912419061 ps
CPU time 5.78 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:36 PM PST 24
Peak memory 201548 kb
Host smart-02aa1ace-3115-4fb6-9008-ef4312ee46a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496536425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2496536425
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4268147425
Short name T413
Test name
Test status
Simulation time 405473176 ps
CPU time 0.87 seconds
Started Feb 04 12:41:09 PM PST 24
Finished Feb 04 12:41:11 PM PST 24
Peak memory 201388 kb
Host smart-b0ef9f03-5b56-4f53-a425-5cf87aca9c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268147425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4268147425
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2946146393
Short name T6
Test name
Test status
Simulation time 301144382 ps
CPU time 1.31 seconds
Started Feb 04 12:41:09 PM PST 24
Finished Feb 04 12:41:12 PM PST 24
Peak memory 201216 kb
Host smart-0de57b11-2362-4ea2-b762-bcba46026af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946146393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2946146393
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1917414355
Short name T879
Test name
Test status
Simulation time 470539528 ps
CPU time 0.93 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201072 kb
Host smart-6c706e7d-8919-469a-b3f6-d7ff5968c98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917414355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1917414355
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1114542381
Short name T422
Test name
Test status
Simulation time 492069570 ps
CPU time 0.92 seconds
Started Feb 04 12:40:59 PM PST 24
Finished Feb 04 12:41:03 PM PST 24
Peak memory 201120 kb
Host smart-dff544a0-73c4-476f-bac0-50e601501f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114542381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1114542381
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.734640788
Short name T191
Test name
Test status
Simulation time 351323992 ps
CPU time 0.72 seconds
Started Feb 04 12:41:00 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201316 kb
Host smart-5addf058-179b-445a-9900-db1d4c31a1dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734640788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.734640788
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1172702616
Short name T79
Test name
Test status
Simulation time 329582595 ps
CPU time 1.32 seconds
Started Feb 04 12:41:03 PM PST 24
Finished Feb 04 12:41:08 PM PST 24
Peak memory 201144 kb
Host smart-b89c73e3-e755-4528-b8ac-371e470f9950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172702616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1172702616
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.40959388
Short name T892
Test name
Test status
Simulation time 473025449 ps
CPU time 0.84 seconds
Started Feb 04 12:41:09 PM PST 24
Finished Feb 04 12:41:10 PM PST 24
Peak memory 201336 kb
Host smart-717e0de0-833c-434a-9ae8-6b21f0caf8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40959388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.40959388
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.865669826
Short name T400
Test name
Test status
Simulation time 295246480 ps
CPU time 1.3 seconds
Started Feb 04 12:41:02 PM PST 24
Finished Feb 04 12:41:07 PM PST 24
Peak memory 201336 kb
Host smart-5bda4074-63c7-4e6c-8c45-ff6f48e1a581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865669826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.865669826
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1639776365
Short name T378
Test name
Test status
Simulation time 488144649 ps
CPU time 0.73 seconds
Started Feb 04 12:41:09 PM PST 24
Finished Feb 04 12:41:11 PM PST 24
Peak memory 201180 kb
Host smart-8e276960-e490-4c21-8f23-60bc66649073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639776365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1639776365
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1204091992
Short name T425
Test name
Test status
Simulation time 548508946 ps
CPU time 0.92 seconds
Started Feb 04 12:41:02 PM PST 24
Finished Feb 04 12:41:07 PM PST 24
Peak memory 201328 kb
Host smart-77402359-4b7f-49ff-bf86-b90fd542e6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204091992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1204091992
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.283912281
Short name T911
Test name
Test status
Simulation time 700981823 ps
CPU time 2.78 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:34 PM PST 24
Peak memory 201464 kb
Host smart-62766bae-68e4-4a3d-ab5b-e958cac35581
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283912281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.283912281
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.750536233
Short name T391
Test name
Test status
Simulation time 52553041347 ps
CPU time 35.41 seconds
Started Feb 04 12:40:16 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201508 kb
Host smart-0198e7ed-f1a3-4911-925f-4efac172d35d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750536233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.750536233
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3464206583
Short name T907
Test name
Test status
Simulation time 1137475810 ps
CPU time 3.34 seconds
Started Feb 04 12:40:11 PM PST 24
Finished Feb 04 12:40:30 PM PST 24
Peak memory 201312 kb
Host smart-357117ad-2241-4a9d-a9f4-624b47ba9e75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464206583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3464206583
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2500600547
Short name T410
Test name
Test status
Simulation time 349887226 ps
CPU time 1.23 seconds
Started Feb 04 12:40:16 PM PST 24
Finished Feb 04 12:40:30 PM PST 24
Peak memory 201384 kb
Host smart-150662b5-cb12-43be-aacb-b75a6eadb7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500600547 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2500600547
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3446500640
Short name T72
Test name
Test status
Simulation time 411679506 ps
CPU time 1.27 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:32 PM PST 24
Peak memory 201364 kb
Host smart-9bfa7eff-cfb8-4b84-b0ed-a8ed5ec3704c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446500640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3446500640
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1838522619
Short name T80
Test name
Test status
Simulation time 287699037 ps
CPU time 1.34 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:32 PM PST 24
Peak memory 201144 kb
Host smart-4995450f-22bb-4ad8-bc82-619386e09f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838522619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1838522619
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3797418919
Short name T402
Test name
Test status
Simulation time 4296241516 ps
CPU time 2.14 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:33 PM PST 24
Peak memory 201728 kb
Host smart-ef23e673-f79b-4957-ae8c-9923388abae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797418919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3797418919
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3560783789
Short name T89
Test name
Test status
Simulation time 1581335967 ps
CPU time 2.68 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:34 PM PST 24
Peak memory 201544 kb
Host smart-fc8aded4-27b8-499c-a62b-2d14be68a806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560783789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3560783789
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1755901537
Short name T888
Test name
Test status
Simulation time 4237830373 ps
CPU time 6.65 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:38 PM PST 24
Peak memory 201660 kb
Host smart-b4b91729-32ca-42b1-847e-c5cdc8cda56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755901537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1755901537
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3540355344
Short name T880
Test name
Test status
Simulation time 454883182 ps
CPU time 1.68 seconds
Started Feb 04 12:40:58 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201332 kb
Host smart-2e5992fd-852f-491e-a530-7b4217a6c118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540355344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3540355344
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1996083329
Short name T901
Test name
Test status
Simulation time 375617588 ps
CPU time 1.08 seconds
Started Feb 04 12:40:59 PM PST 24
Finished Feb 04 12:41:04 PM PST 24
Peak memory 201316 kb
Host smart-dde540b2-9200-4e7c-beac-54f9d3b072b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996083329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1996083329
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2964701564
Short name T65
Test name
Test status
Simulation time 499614650 ps
CPU time 0.97 seconds
Started Feb 04 12:41:03 PM PST 24
Finished Feb 04 12:41:08 PM PST 24
Peak memory 201072 kb
Host smart-afbdb946-63fb-46f0-be57-6fd2c9612240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964701564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2964701564
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1263216856
Short name T415
Test name
Test status
Simulation time 531114753 ps
CPU time 1.3 seconds
Started Feb 04 12:41:02 PM PST 24
Finished Feb 04 12:41:07 PM PST 24
Peak memory 201128 kb
Host smart-59dc0412-1b98-4d0b-ade9-e30b83c5913b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263216856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1263216856
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3522953032
Short name T401
Test name
Test status
Simulation time 463312035 ps
CPU time 0.74 seconds
Started Feb 04 12:41:02 PM PST 24
Finished Feb 04 12:41:07 PM PST 24
Peak memory 201108 kb
Host smart-0f11fe76-4501-43c4-9d38-1b4590100e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522953032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3522953032
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1111939412
Short name T395
Test name
Test status
Simulation time 606034433 ps
CPU time 0.71 seconds
Started Feb 04 12:41:04 PM PST 24
Finished Feb 04 12:41:07 PM PST 24
Peak memory 201060 kb
Host smart-4c781279-c8ee-4c31-8d47-828f04d20730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111939412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1111939412
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3693798121
Short name T387
Test name
Test status
Simulation time 468600659 ps
CPU time 1.69 seconds
Started Feb 04 12:41:10 PM PST 24
Finished Feb 04 12:41:13 PM PST 24
Peak memory 201148 kb
Host smart-1aa43754-1c1e-44a6-b39d-3cdf58c65d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693798121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3693798121
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.184930381
Short name T377
Test name
Test status
Simulation time 344026722 ps
CPU time 0.85 seconds
Started Feb 04 12:41:01 PM PST 24
Finished Feb 04 12:41:06 PM PST 24
Peak memory 201144 kb
Host smart-4fd2c209-d63c-4012-aa55-88586df3f6be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184930381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.184930381
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2108769266
Short name T374
Test name
Test status
Simulation time 475049009 ps
CPU time 0.9 seconds
Started Feb 04 12:41:20 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 201132 kb
Host smart-2bdd87a3-46b5-46b4-888c-79add658e4eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108769266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2108769266
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3375323488
Short name T403
Test name
Test status
Simulation time 431244544 ps
CPU time 0.89 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:18 PM PST 24
Peak memory 201132 kb
Host smart-d93f2722-a90f-43aa-bf1f-fa4805cb2118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375323488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3375323488
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.830061561
Short name T77
Test name
Test status
Simulation time 426756523 ps
CPU time 1.92 seconds
Started Feb 04 12:40:16 PM PST 24
Finished Feb 04 12:40:30 PM PST 24
Peak memory 201560 kb
Host smart-42d20a22-e1db-4d8c-8de0-48a6f75dbd44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830061561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.830061561
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.419558980
Short name T85
Test name
Test status
Simulation time 41226695705 ps
CPU time 15.12 seconds
Started Feb 04 12:40:16 PM PST 24
Finished Feb 04 12:40:43 PM PST 24
Peak memory 201608 kb
Host smart-2ed6813d-362e-499a-8fb8-02eb658a38f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419558980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.419558980
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3335093984
Short name T382
Test name
Test status
Simulation time 835240728 ps
CPU time 2.65 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:34 PM PST 24
Peak memory 201256 kb
Host smart-bd0e548c-106c-492b-ac51-b0c813b1aa15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335093984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3335093984
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1327898436
Short name T407
Test name
Test status
Simulation time 398074953 ps
CPU time 1.2 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:33 PM PST 24
Peak memory 201408 kb
Host smart-32c79962-3468-4fd7-a489-48f1245d877d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327898436 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1327898436
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1943892759
Short name T76
Test name
Test status
Simulation time 456366147 ps
CPU time 1.14 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:32 PM PST 24
Peak memory 201256 kb
Host smart-c4805104-eacb-4ba9-bf5f-e4f1314c8a05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943892759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1943892759
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3954166838
Short name T376
Test name
Test status
Simulation time 428969167 ps
CPU time 1.12 seconds
Started Feb 04 12:40:18 PM PST 24
Finished Feb 04 12:40:32 PM PST 24
Peak memory 201076 kb
Host smart-e41a5764-0a59-4798-bae2-8993e5bf6a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954166838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3954166838
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.923413756
Short name T82
Test name
Test status
Simulation time 5577680891 ps
CPU time 4.64 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:39 PM PST 24
Peak memory 201564 kb
Host smart-4c087765-9d13-497a-8168-2f0d1b4e8bcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923413756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.923413756
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3397415587
Short name T910
Test name
Test status
Simulation time 426566132 ps
CPU time 2.93 seconds
Started Feb 04 12:40:17 PM PST 24
Finished Feb 04 12:40:31 PM PST 24
Peak memory 209804 kb
Host smart-87a3b9ce-d626-45d1-a3d5-c2fb5751d041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397415587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3397415587
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1761639605
Short name T898
Test name
Test status
Simulation time 7370600831 ps
CPU time 19.16 seconds
Started Feb 04 12:40:17 PM PST 24
Finished Feb 04 12:40:48 PM PST 24
Peak memory 201592 kb
Host smart-0f7e067f-199c-4df3-a13e-9b1c7e79687b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761639605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1761639605
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3344700485
Short name T190
Test name
Test status
Simulation time 530222458 ps
CPU time 0.95 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:19 PM PST 24
Peak memory 201300 kb
Host smart-1b76698a-9d57-4d90-8840-2d35ab898311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344700485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3344700485
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.70180750
Short name T388
Test name
Test status
Simulation time 374685615 ps
CPU time 1.1 seconds
Started Feb 04 12:41:13 PM PST 24
Finished Feb 04 12:41:17 PM PST 24
Peak memory 201192 kb
Host smart-d4b384f3-4fc8-41e0-b4a0-aa6d7a9757f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70180750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.70180750
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3863096510
Short name T427
Test name
Test status
Simulation time 433984088 ps
CPU time 1.47 seconds
Started Feb 04 12:41:10 PM PST 24
Finished Feb 04 12:41:14 PM PST 24
Peak memory 201116 kb
Host smart-1db54996-27bb-44db-835e-efbeeebc89ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863096510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3863096510
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2531880051
Short name T78
Test name
Test status
Simulation time 306749839 ps
CPU time 0.78 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:41:26 PM PST 24
Peak memory 201100 kb
Host smart-04532562-b49a-4a2b-89f4-b4855badad80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531880051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2531880051
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4273079984
Short name T914
Test name
Test status
Simulation time 353852569 ps
CPU time 1.46 seconds
Started Feb 04 12:41:12 PM PST 24
Finished Feb 04 12:41:16 PM PST 24
Peak memory 201292 kb
Host smart-1a6a5759-8f5e-41fe-ad7c-828b0b586228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273079984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4273079984
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3538327822
Short name T375
Test name
Test status
Simulation time 399579982 ps
CPU time 1.6 seconds
Started Feb 04 12:41:18 PM PST 24
Finished Feb 04 12:41:26 PM PST 24
Peak memory 201180 kb
Host smart-63d8a832-a254-4606-ad66-4d05181545f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538327822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3538327822
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.338965101
Short name T906
Test name
Test status
Simulation time 556922960 ps
CPU time 0.99 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:18 PM PST 24
Peak memory 201104 kb
Host smart-cf8e996a-1c01-4955-b233-d56f80c52437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338965101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.338965101
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.882586356
Short name T392
Test name
Test status
Simulation time 321207133 ps
CPU time 0.8 seconds
Started Feb 04 12:41:23 PM PST 24
Finished Feb 04 12:41:30 PM PST 24
Peak memory 201088 kb
Host smart-08883f72-8539-43f7-ad70-e78519c7c48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882586356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.882586356
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1463145758
Short name T373
Test name
Test status
Simulation time 319914057 ps
CPU time 0.79 seconds
Started Feb 04 12:41:14 PM PST 24
Finished Feb 04 12:41:18 PM PST 24
Peak memory 201300 kb
Host smart-a3b8268f-0c27-4368-b416-92c0a480f9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463145758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1463145758
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1229621979
Short name T398
Test name
Test status
Simulation time 487856853 ps
CPU time 0.8 seconds
Started Feb 04 12:41:19 PM PST 24
Finished Feb 04 12:41:27 PM PST 24
Peak memory 201116 kb
Host smart-10e36ca8-9f8e-4de8-b67a-8d0120692337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229621979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1229621979
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2947211289
Short name T189
Test name
Test status
Simulation time 467590951 ps
CPU time 1.15 seconds
Started Feb 04 12:40:19 PM PST 24
Finished Feb 04 12:40:34 PM PST 24
Peak memory 201376 kb
Host smart-d35b6e66-6297-45c9-adc6-82cdb8f7db16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947211289 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2947211289
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.666582025
Short name T11
Test name
Test status
Simulation time 431883507 ps
CPU time 1 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:35 PM PST 24
Peak memory 201272 kb
Host smart-b2b19f97-e0a0-4a2c-b334-cf93a13bcd4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666582025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.666582025
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3241939046
Short name T891
Test name
Test status
Simulation time 361536569 ps
CPU time 1.07 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:35 PM PST 24
Peak memory 201024 kb
Host smart-d25c68a3-ce16-411b-94c4-5823551c1ecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241939046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3241939046
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1858902468
Short name T420
Test name
Test status
Simulation time 553708364 ps
CPU time 3.25 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:37 PM PST 24
Peak memory 201544 kb
Host smart-0c609279-5a74-410b-954d-59f18c9a879b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858902468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1858902468
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.804884710
Short name T383
Test name
Test status
Simulation time 8197592409 ps
CPU time 5.82 seconds
Started Feb 04 12:40:20 PM PST 24
Finished Feb 04 12:40:39 PM PST 24
Peak memory 201500 kb
Host smart-82feb80e-8881-45ef-92d8-c5868e83d5c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804884710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.804884710
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.658413669
Short name T897
Test name
Test status
Simulation time 453986398 ps
CPU time 1.77 seconds
Started Feb 04 12:40:46 PM PST 24
Finished Feb 04 12:40:49 PM PST 24
Peak memory 201228 kb
Host smart-53b8e9c5-cf09-4d3c-9e2d-e2f5397a488c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658413669 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.658413669
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2688877657
Short name T32
Test name
Test status
Simulation time 482037293 ps
CPU time 2.01 seconds
Started Feb 04 12:40:31 PM PST 24
Finished Feb 04 12:40:40 PM PST 24
Peak memory 201344 kb
Host smart-2f47ad65-99dd-41b3-83ee-daa6d5022b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688877657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2688877657
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1083542777
Short name T380
Test name
Test status
Simulation time 403561435 ps
CPU time 1.11 seconds
Started Feb 04 12:40:37 PM PST 24
Finished Feb 04 12:40:42 PM PST 24
Peak memory 201080 kb
Host smart-0d8c545e-590d-4ea6-9166-846caed5ea5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083542777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1083542777
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1863893868
Short name T913
Test name
Test status
Simulation time 4333172361 ps
CPU time 3.04 seconds
Started Feb 04 12:40:41 PM PST 24
Finished Feb 04 12:40:46 PM PST 24
Peak memory 201644 kb
Host smart-494101cb-50c0-426a-a366-5cae9c33af46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863893868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1863893868
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1996743217
Short name T426
Test name
Test status
Simulation time 755935990 ps
CPU time 2.48 seconds
Started Feb 04 12:40:29 PM PST 24
Finished Feb 04 12:40:40 PM PST 24
Peak memory 217660 kb
Host smart-bba8cb79-a009-4839-b3db-f36bed6b2149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996743217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1996743217
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1314317907
Short name T31
Test name
Test status
Simulation time 8339093617 ps
CPU time 21.99 seconds
Started Feb 04 12:40:37 PM PST 24
Finished Feb 04 12:41:03 PM PST 24
Peak memory 201676 kb
Host smart-694648d7-5fd3-4baf-b57c-a70fc00e3573
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314317907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1314317907
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.498067572
Short name T886
Test name
Test status
Simulation time 597680629 ps
CPU time 1.61 seconds
Started Feb 04 12:40:27 PM PST 24
Finished Feb 04 12:40:39 PM PST 24
Peak memory 201424 kb
Host smart-b72e3f6c-4df5-4e16-a58f-a8015baf9640
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498067572 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.498067572
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.839992128
Short name T408
Test name
Test status
Simulation time 421475325 ps
CPU time 0.9 seconds
Started Feb 04 12:40:28 PM PST 24
Finished Feb 04 12:40:39 PM PST 24
Peak memory 201192 kb
Host smart-168a3e04-46ac-40c8-91eb-bf9b2c34e42b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839992128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.839992128
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.158823884
Short name T8
Test name
Test status
Simulation time 4788170958 ps
CPU time 10.07 seconds
Started Feb 04 12:40:37 PM PST 24
Finished Feb 04 12:40:51 PM PST 24
Peak memory 201108 kb
Host smart-f6df7064-4e07-46fd-b9c9-ce895a1b778e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158823884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.158823884
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2973728707
Short name T872
Test name
Test status
Simulation time 1215264401 ps
CPU time 1.6 seconds
Started Feb 04 12:40:25 PM PST 24
Finished Feb 04 12:40:39 PM PST 24
Peak memory 201540 kb
Host smart-6d9be648-1f84-4e1a-86cc-77831f56f75b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973728707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2973728707
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1375605795
Short name T903
Test name
Test status
Simulation time 341378522 ps
CPU time 1.52 seconds
Started Feb 04 12:40:37 PM PST 24
Finished Feb 04 12:40:42 PM PST 24
Peak memory 201392 kb
Host smart-9fff64ff-62fa-4ce0-8bde-3a727c3bcc35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375605795 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1375605795
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.840379925
Short name T885
Test name
Test status
Simulation time 656469635 ps
CPU time 0.83 seconds
Started Feb 04 12:40:46 PM PST 24
Finished Feb 04 12:40:48 PM PST 24
Peak memory 201232 kb
Host smart-f7dd3c54-4523-42a8-9270-3e6b0744b44d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840379925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.840379925
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1387534353
Short name T421
Test name
Test status
Simulation time 436223264 ps
CPU time 1.65 seconds
Started Feb 04 12:40:33 PM PST 24
Finished Feb 04 12:40:41 PM PST 24
Peak memory 201136 kb
Host smart-d01a8734-190c-4ffc-a96f-ab6ad39f16bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387534353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1387534353
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1270029615
Short name T874
Test name
Test status
Simulation time 4570544316 ps
CPU time 5.37 seconds
Started Feb 04 12:40:46 PM PST 24
Finished Feb 04 12:40:53 PM PST 24
Peak memory 201520 kb
Host smart-9541bb87-2221-4a15-a5a6-62f8555501d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270029615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1270029615
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3741953469
Short name T57
Test name
Test status
Simulation time 645165770 ps
CPU time 1.78 seconds
Started Feb 04 12:40:39 PM PST 24
Finished Feb 04 12:40:43 PM PST 24
Peak memory 201580 kb
Host smart-1ddd7f1d-3368-444f-a9ba-5a75870d858a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741953469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3741953469
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2082215127
Short name T877
Test name
Test status
Simulation time 4261831383 ps
CPU time 6.39 seconds
Started Feb 04 12:40:41 PM PST 24
Finished Feb 04 12:40:49 PM PST 24
Peak memory 201668 kb
Host smart-4026babf-db2e-42a5-898c-7ad419241629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082215127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2082215127
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1419819827
Short name T405
Test name
Test status
Simulation time 543638373 ps
CPU time 1.06 seconds
Started Feb 04 12:40:38 PM PST 24
Finished Feb 04 12:40:42 PM PST 24
Peak memory 201324 kb
Host smart-c3fd75a9-8490-4d38-a254-f57a333d5691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419819827 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1419819827
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3666616505
Short name T869
Test name
Test status
Simulation time 493165054 ps
CPU time 0.81 seconds
Started Feb 04 12:40:39 PM PST 24
Finished Feb 04 12:40:42 PM PST 24
Peak memory 201296 kb
Host smart-53854770-6928-40f2-a752-eae37b09818f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666616505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3666616505
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2110485747
Short name T397
Test name
Test status
Simulation time 500371243 ps
CPU time 0.91 seconds
Started Feb 04 12:40:27 PM PST 24
Finished Feb 04 12:40:38 PM PST 24
Peak memory 201108 kb
Host smart-7a388b9e-ba97-4a54-b127-774582559313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110485747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2110485747
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2406626910
Short name T7
Test name
Test status
Simulation time 4047171486 ps
CPU time 13.9 seconds
Started Feb 04 12:40:26 PM PST 24
Finished Feb 04 12:40:51 PM PST 24
Peak memory 201704 kb
Host smart-3e202d4a-f593-48c5-b3c4-1555fb146322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406626910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2406626910
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4722045
Short name T414
Test name
Test status
Simulation time 4035940456 ps
CPU time 6.29 seconds
Started Feb 04 12:40:46 PM PST 24
Finished Feb 04 12:40:53 PM PST 24
Peak memory 201516 kb
Host smart-fe5dd5d8-dff4-4b67-9452-6ad756f59120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4722045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_
err.4722045
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2937794476
Short name T865
Test name
Test status
Simulation time 312339613 ps
CPU time 0.82 seconds
Started Feb 04 01:03:11 PM PST 24
Finished Feb 04 01:03:13 PM PST 24
Peak memory 201256 kb
Host smart-24618e2d-4241-483a-b508-08882ee8800b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937794476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2937794476
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4066867752
Short name T826
Test name
Test status
Simulation time 162143523417 ps
CPU time 37.21 seconds
Started Feb 04 01:03:09 PM PST 24
Finished Feb 04 01:03:49 PM PST 24
Peak memory 201424 kb
Host smart-2edd0ee6-c857-4216-87e9-f578a649467a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066867752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4066867752
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1027414864
Short name T631
Test name
Test status
Simulation time 159859528238 ps
CPU time 97.97 seconds
Started Feb 04 01:03:05 PM PST 24
Finished Feb 04 01:04:47 PM PST 24
Peak memory 201664 kb
Host smart-ed37bef7-aef0-417d-82a8-0ddb4fba3f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027414864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1027414864
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2547068764
Short name T530
Test name
Test status
Simulation time 487462916780 ps
CPU time 1181.45 seconds
Started Feb 04 01:03:10 PM PST 24
Finished Feb 04 01:22:54 PM PST 24
Peak memory 201628 kb
Host smart-dc9bfd66-0135-40e1-9869-8dc4df5ac694
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547068764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2547068764
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.4111232008
Short name T642
Test name
Test status
Simulation time 159008404334 ps
CPU time 102.04 seconds
Started Feb 04 01:03:07 PM PST 24
Finished Feb 04 01:04:53 PM PST 24
Peak memory 201596 kb
Host smart-7ae83a32-e18c-4254-a5d2-b5c129b17a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111232008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.4111232008
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2149024538
Short name T863
Test name
Test status
Simulation time 167759160267 ps
CPU time 105.08 seconds
Started Feb 04 01:03:09 PM PST 24
Finished Feb 04 01:04:56 PM PST 24
Peak memory 201596 kb
Host smart-d3da178e-6cf4-46ff-b909-e1435a9c16ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149024538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2149024538
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2744784685
Short name T488
Test name
Test status
Simulation time 498200717047 ps
CPU time 1138.87 seconds
Started Feb 04 01:03:12 PM PST 24
Finished Feb 04 01:22:13 PM PST 24
Peak memory 201612 kb
Host smart-4dad3054-8e31-4dc8-b8b5-6e20f9d2a121
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744784685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2744784685
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3760876874
Short name T623
Test name
Test status
Simulation time 93589243072 ps
CPU time 299.82 seconds
Started Feb 04 01:03:15 PM PST 24
Finished Feb 04 01:08:16 PM PST 24
Peak memory 201328 kb
Host smart-5533ef81-07f7-4d30-9d8f-378b488fea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760876874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3760876874
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3310961301
Short name T124
Test name
Test status
Simulation time 34223054275 ps
CPU time 20.04 seconds
Started Feb 04 01:03:05 PM PST 24
Finished Feb 04 01:03:28 PM PST 24
Peak memory 201356 kb
Host smart-9b8ce89a-c874-4004-9231-76672b146cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310961301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3310961301
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4077051214
Short name T432
Test name
Test status
Simulation time 5192928082 ps
CPU time 5.68 seconds
Started Feb 04 01:03:09 PM PST 24
Finished Feb 04 01:03:17 PM PST 24
Peak memory 201324 kb
Host smart-11278f45-c5ab-4a9c-8184-e5b240d40c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077051214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4077051214
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1546954281
Short name T44
Test name
Test status
Simulation time 4505615691 ps
CPU time 11.58 seconds
Started Feb 04 01:03:12 PM PST 24
Finished Feb 04 01:03:25 PM PST 24
Peak memory 216748 kb
Host smart-6c35cbe2-4a27-4725-8ea4-a8b585fd7758
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546954281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1546954281
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3728601175
Short name T465
Test name
Test status
Simulation time 5927164406 ps
CPU time 3.04 seconds
Started Feb 04 01:03:05 PM PST 24
Finished Feb 04 01:03:11 PM PST 24
Peak memory 201332 kb
Host smart-1dd4d0b8-1212-4f3a-a4ca-7f0b71ba509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728601175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3728601175
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2063927697
Short name T276
Test name
Test status
Simulation time 488144232470 ps
CPU time 279.99 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:08:00 PM PST 24
Peak memory 201648 kb
Host smart-75fcc3ee-cf80-44a3-baef-6b16f890b812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063927697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2063927697
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2243167027
Short name T278
Test name
Test status
Simulation time 95832964598 ps
CPU time 40.26 seconds
Started Feb 04 01:03:09 PM PST 24
Finished Feb 04 01:03:52 PM PST 24
Peak memory 202096 kb
Host smart-da637cef-5859-44d2-a269-8d054383099d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243167027 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2243167027
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3691192904
Short name T527
Test name
Test status
Simulation time 384155963 ps
CPU time 0.88 seconds
Started Feb 04 01:03:15 PM PST 24
Finished Feb 04 01:03:18 PM PST 24
Peak memory 201272 kb
Host smart-0a932faa-5e60-4e1d-91cf-1eee190d6826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691192904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3691192904
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2080749972
Short name T128
Test name
Test status
Simulation time 502934647761 ps
CPU time 61.45 seconds
Started Feb 04 01:03:16 PM PST 24
Finished Feb 04 01:04:20 PM PST 24
Peak memory 201644 kb
Host smart-83873791-49c1-4b3c-a284-9bd748801ef0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080749972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2080749972
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3043806104
Short name T746
Test name
Test status
Simulation time 491085205403 ps
CPU time 178.22 seconds
Started Feb 04 01:03:16 PM PST 24
Finished Feb 04 01:06:17 PM PST 24
Peak memory 201672 kb
Host smart-52379430-6585-48e5-9c58-55145260dc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043806104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3043806104
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1218365789
Short name T150
Test name
Test status
Simulation time 163959125348 ps
CPU time 98.18 seconds
Started Feb 04 01:03:17 PM PST 24
Finished Feb 04 01:04:59 PM PST 24
Peak memory 201604 kb
Host smart-8ead2d38-5161-4a94-9035-05295b89533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218365789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1218365789
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3967996459
Short name T480
Test name
Test status
Simulation time 490923992000 ps
CPU time 1127.02 seconds
Started Feb 04 01:03:16 PM PST 24
Finished Feb 04 01:22:05 PM PST 24
Peak memory 201564 kb
Host smart-14ebb917-cefa-4263-be86-16ccc52e3ce5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967996459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3967996459
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2367247825
Short name T667
Test name
Test status
Simulation time 162242727924 ps
CPU time 392.1 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:09:53 PM PST 24
Peak memory 201604 kb
Host smart-7684e962-401a-4994-b8d7-7cf291379788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367247825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2367247825
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1351385677
Short name T643
Test name
Test status
Simulation time 334945708455 ps
CPU time 812.56 seconds
Started Feb 04 01:03:13 PM PST 24
Finished Feb 04 01:16:47 PM PST 24
Peak memory 201620 kb
Host smart-a460748c-8078-4433-813a-c3e0e8f3dcbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351385677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1351385677
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1527431312
Short name T329
Test name
Test status
Simulation time 162949217098 ps
CPU time 98.21 seconds
Started Feb 04 01:03:13 PM PST 24
Finished Feb 04 01:04:53 PM PST 24
Peak memory 201628 kb
Host smart-fe7ec90f-d8e2-4e84-a913-9f35535f9726
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527431312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1527431312
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2646241295
Short name T195
Test name
Test status
Simulation time 81789327219 ps
CPU time 325.43 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:08:46 PM PST 24
Peak memory 201720 kb
Host smart-54174b70-61b8-486b-a24c-ad56697a52a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646241295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2646241295
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.849093132
Short name T524
Test name
Test status
Simulation time 24420353662 ps
CPU time 29.99 seconds
Started Feb 04 01:03:15 PM PST 24
Finished Feb 04 01:03:46 PM PST 24
Peak memory 201384 kb
Host smart-e7c9fa7b-f244-4bb5-b097-672ee38bf9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849093132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.849093132
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3164128158
Short name T520
Test name
Test status
Simulation time 4779278528 ps
CPU time 2.38 seconds
Started Feb 04 01:03:15 PM PST 24
Finished Feb 04 01:03:19 PM PST 24
Peak memory 201404 kb
Host smart-d042f387-bca8-49a1-a778-d45438bab3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164128158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3164128158
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4281998459
Short name T46
Test name
Test status
Simulation time 4012355092 ps
CPU time 9.69 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:03:30 PM PST 24
Peak memory 216384 kb
Host smart-45bcc8d2-cd5c-420a-bae2-747c625c566d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281998459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4281998459
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.666482077
Short name T783
Test name
Test status
Simulation time 6209802663 ps
CPU time 2.6 seconds
Started Feb 04 01:03:08 PM PST 24
Finished Feb 04 01:03:14 PM PST 24
Peak memory 201380 kb
Host smart-926c61af-50ea-4a6a-8668-d70bf7076c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666482077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.666482077
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1259566198
Short name T586
Test name
Test status
Simulation time 167933452577 ps
CPU time 48.04 seconds
Started Feb 04 01:03:17 PM PST 24
Finished Feb 04 01:04:07 PM PST 24
Peak memory 201644 kb
Host smart-d8706034-cf04-4abe-9d59-bf0b6582d1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259566198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1259566198
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2018790584
Short name T691
Test name
Test status
Simulation time 29241691909 ps
CPU time 18.63 seconds
Started Feb 04 01:03:14 PM PST 24
Finished Feb 04 01:03:33 PM PST 24
Peak memory 209896 kb
Host smart-7c5e3df5-22ef-4a14-abb8-be7f63e00214
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018790584 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2018790584
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.25060205
Short name T561
Test name
Test status
Simulation time 429513091 ps
CPU time 1.05 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:04:23 PM PST 24
Peak memory 201124 kb
Host smart-ac1ef3be-30f8-4b5d-9d5c-9a038234109b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25060205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.25060205
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.854175621
Short name T264
Test name
Test status
Simulation time 162410951385 ps
CPU time 95.52 seconds
Started Feb 04 01:04:28 PM PST 24
Finished Feb 04 01:06:04 PM PST 24
Peak memory 201544 kb
Host smart-38cae555-9349-47e4-bff6-ca5c08c61e6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854175621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.854175621
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3989821008
Short name T252
Test name
Test status
Simulation time 162198410019 ps
CPU time 362.01 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:10:24 PM PST 24
Peak memory 201660 kb
Host smart-724df503-8cc6-41e5-8585-9e3b543e87d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989821008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3989821008
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.703356937
Short name T844
Test name
Test status
Simulation time 321692253101 ps
CPU time 196.08 seconds
Started Feb 04 01:04:14 PM PST 24
Finished Feb 04 01:07:32 PM PST 24
Peak memory 201664 kb
Host smart-b681331e-caf1-4336-b4c6-29cfc87968bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703356937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.703356937
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2434094108
Short name T540
Test name
Test status
Simulation time 333155803164 ps
CPU time 762.01 seconds
Started Feb 04 01:04:18 PM PST 24
Finished Feb 04 01:17:01 PM PST 24
Peak memory 201540 kb
Host smart-a77245e7-c6bb-4760-8b6e-6e5df1d6bd6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434094108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2434094108
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2669939915
Short name T658
Test name
Test status
Simulation time 167885616091 ps
CPU time 374.23 seconds
Started Feb 04 01:04:29 PM PST 24
Finished Feb 04 01:10:44 PM PST 24
Peak memory 201632 kb
Host smart-89e09bd8-c022-4679-ae50-62dd9b471711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669939915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2669939915
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1601051383
Short name T624
Test name
Test status
Simulation time 168582544615 ps
CPU time 104.95 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:06:06 PM PST 24
Peak memory 201652 kb
Host smart-bbf23441-16a2-4b62-8bba-065923233114
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601051383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1601051383
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3885206975
Short name T220
Test name
Test status
Simulation time 338060013092 ps
CPU time 314.69 seconds
Started Feb 04 01:04:21 PM PST 24
Finished Feb 04 01:09:37 PM PST 24
Peak memory 201688 kb
Host smart-093df1f4-c6a4-48a9-ab7a-51e8505b9dc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885206975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3885206975
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1480805966
Short name T544
Test name
Test status
Simulation time 492809224615 ps
CPU time 1228.73 seconds
Started Feb 04 01:04:31 PM PST 24
Finished Feb 04 01:25:02 PM PST 24
Peak memory 201528 kb
Host smart-9ba1c56d-f0ce-4c34-9044-2c0a7eea00ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480805966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1480805966
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1915158415
Short name T370
Test name
Test status
Simulation time 86935925220 ps
CPU time 509.59 seconds
Started Feb 04 01:04:15 PM PST 24
Finished Feb 04 01:12:46 PM PST 24
Peak memory 201864 kb
Host smart-195cebd1-7ce6-46f3-88f4-473bc8b5c4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915158415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1915158415
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2420569119
Short name T714
Test name
Test status
Simulation time 29847413622 ps
CPU time 69.59 seconds
Started Feb 04 01:04:19 PM PST 24
Finished Feb 04 01:05:30 PM PST 24
Peak memory 201248 kb
Host smart-1055378a-35b1-4810-8717-2032eb747309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420569119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2420569119
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1947645002
Short name T449
Test name
Test status
Simulation time 5239893793 ps
CPU time 3.82 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:04:24 PM PST 24
Peak memory 201248 kb
Host smart-80b64f39-f918-4aab-bf75-cb6862ce7d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947645002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1947645002
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.927540305
Short name T522
Test name
Test status
Simulation time 5781228356 ps
CPU time 1.5 seconds
Started Feb 04 01:04:17 PM PST 24
Finished Feb 04 01:04:19 PM PST 24
Peak memory 201336 kb
Host smart-fc78e7cf-ae7d-401a-8d42-289ce6222f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927540305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.927540305
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3536584493
Short name T169
Test name
Test status
Simulation time 29330287965 ps
CPU time 96.72 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:05:59 PM PST 24
Peak memory 210312 kb
Host smart-6ca76c58-badb-43b2-9a57-10045c82a88d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536584493 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3536584493
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2940269511
Short name T784
Test name
Test status
Simulation time 464337642 ps
CPU time 1.45 seconds
Started Feb 04 01:04:22 PM PST 24
Finished Feb 04 01:04:25 PM PST 24
Peak memory 201280 kb
Host smart-20d130c4-c8ec-4be8-a527-50cb216038af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940269511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2940269511
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3301995569
Short name T687
Test name
Test status
Simulation time 327980691357 ps
CPU time 153.7 seconds
Started Feb 04 01:04:31 PM PST 24
Finished Feb 04 01:07:06 PM PST 24
Peak memory 201588 kb
Host smart-b17bc820-c96e-4eba-b04b-b980633787d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301995569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3301995569
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1460600927
Short name T19
Test name
Test status
Simulation time 325680586304 ps
CPU time 775.3 seconds
Started Feb 04 01:04:23 PM PST 24
Finished Feb 04 01:17:19 PM PST 24
Peak memory 201484 kb
Host smart-ff31edc5-f9cf-452b-add7-5610ed66d8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460600927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1460600927
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3289739449
Short name T812
Test name
Test status
Simulation time 490216523119 ps
CPU time 296.87 seconds
Started Feb 04 01:04:23 PM PST 24
Finished Feb 04 01:09:21 PM PST 24
Peak memory 201400 kb
Host smart-3e123d4e-22bd-45e3-af88-58051274ed80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289739449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3289739449
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1965411608
Short name T54
Test name
Test status
Simulation time 332044858881 ps
CPU time 193.8 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:07:36 PM PST 24
Peak memory 201644 kb
Host smart-b6b2c0bb-0273-4af3-841d-446226ce1f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965411608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1965411608
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2747247835
Short name T437
Test name
Test status
Simulation time 159061804313 ps
CPU time 183.69 seconds
Started Feb 04 01:04:23 PM PST 24
Finished Feb 04 01:07:28 PM PST 24
Peak memory 201468 kb
Host smart-4701528f-f570-4c1b-b806-344ff234b261
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747247835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2747247835
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2427612546
Short name T272
Test name
Test status
Simulation time 329245941042 ps
CPU time 769.56 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:17:11 PM PST 24
Peak memory 201644 kb
Host smart-7f991159-7cab-41eb-af5b-4fef79e55cf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427612546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2427612546
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3728162225
Short name T864
Test name
Test status
Simulation time 496325162082 ps
CPU time 1239.21 seconds
Started Feb 04 01:04:32 PM PST 24
Finished Feb 04 01:25:12 PM PST 24
Peak memory 201548 kb
Host smart-8c70705e-35cc-4a42-b4cc-c752acf86e85
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728162225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3728162225
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1536008485
Short name T827
Test name
Test status
Simulation time 84841643551 ps
CPU time 456.39 seconds
Started Feb 04 01:04:31 PM PST 24
Finished Feb 04 01:12:09 PM PST 24
Peak memory 201916 kb
Host smart-bb4b7f8f-c9f2-42f3-95ab-07bf7077aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536008485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1536008485
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1014738057
Short name T684
Test name
Test status
Simulation time 34341916196 ps
CPU time 41.99 seconds
Started Feb 04 01:04:23 PM PST 24
Finished Feb 04 01:05:06 PM PST 24
Peak memory 201220 kb
Host smart-ddbdac1c-229e-42a8-ad3d-c6a441f6e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014738057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1014738057
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.116078506
Short name T705
Test name
Test status
Simulation time 4370541692 ps
CPU time 3.15 seconds
Started Feb 04 01:04:18 PM PST 24
Finished Feb 04 01:04:23 PM PST 24
Peak memory 201432 kb
Host smart-56ef668b-10c4-4949-8f91-e883be932205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116078506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.116078506
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.4000840622
Short name T556
Test name
Test status
Simulation time 5648383154 ps
CPU time 6.57 seconds
Started Feb 04 01:04:19 PM PST 24
Finished Feb 04 01:04:27 PM PST 24
Peak memory 201244 kb
Host smart-9c52a89a-bee9-4e6b-8916-9e57b3266918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000840622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4000840622
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3362624452
Short name T511
Test name
Test status
Simulation time 307732767 ps
CPU time 1.25 seconds
Started Feb 04 01:04:18 PM PST 24
Finished Feb 04 01:04:21 PM PST 24
Peak memory 201228 kb
Host smart-ff6bde0d-3730-425c-b0db-0ccd2741ea0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362624452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3362624452
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3194346934
Short name T233
Test name
Test status
Simulation time 166760916042 ps
CPU time 351.8 seconds
Started Feb 04 01:04:23 PM PST 24
Finished Feb 04 01:10:16 PM PST 24
Peak memory 201544 kb
Host smart-6b345f64-20b4-4569-84e6-031a2d00ae54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194346934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3194346934
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.370712527
Short name T265
Test name
Test status
Simulation time 167870986338 ps
CPU time 382.35 seconds
Started Feb 04 01:04:22 PM PST 24
Finished Feb 04 01:10:46 PM PST 24
Peak memory 201484 kb
Host smart-b87db73f-28fe-41e7-bcbf-ca3ba2c86640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370712527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.370712527
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3026594804
Short name T770
Test name
Test status
Simulation time 498953128041 ps
CPU time 288.58 seconds
Started Feb 04 01:04:22 PM PST 24
Finished Feb 04 01:09:12 PM PST 24
Peak memory 201404 kb
Host smart-d87498ad-70ee-4c58-ac91-2ceca1150a14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026594804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3026594804
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2464960354
Short name T549
Test name
Test status
Simulation time 171215364691 ps
CPU time 411.31 seconds
Started Feb 04 01:04:22 PM PST 24
Finished Feb 04 01:11:15 PM PST 24
Peak memory 201512 kb
Host smart-466f3201-cd46-48a1-bee3-4192e3e5b175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464960354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2464960354
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3807746467
Short name T837
Test name
Test status
Simulation time 161876161426 ps
CPU time 410.17 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:11:12 PM PST 24
Peak memory 201664 kb
Host smart-85b3a347-cb66-44cf-96d3-d919c0af72bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807746467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3807746467
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2291977633
Short name T286
Test name
Test status
Simulation time 173554907212 ps
CPU time 378.05 seconds
Started Feb 04 01:04:22 PM PST 24
Finished Feb 04 01:10:41 PM PST 24
Peak memory 201648 kb
Host smart-6628dde4-3e22-4099-8bfe-3edafe381ff6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291977633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2291977633
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3410089058
Short name T467
Test name
Test status
Simulation time 166449277490 ps
CPU time 78.22 seconds
Started Feb 04 01:04:18 PM PST 24
Finished Feb 04 01:05:38 PM PST 24
Peak memory 201604 kb
Host smart-356b6b2f-a60a-4b0f-bb41-8770507df334
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410089058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3410089058
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.142535687
Short name T457
Test name
Test status
Simulation time 38642028496 ps
CPU time 23.16 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:04:44 PM PST 24
Peak memory 201340 kb
Host smart-9167b5b2-5b84-4a59-af23-4094f18740e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142535687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.142535687
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2883765405
Short name T450
Test name
Test status
Simulation time 2851020455 ps
CPU time 2.28 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:04:24 PM PST 24
Peak memory 201172 kb
Host smart-bac87459-99b9-4879-b828-0d99e5efdba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883765405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2883765405
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1572067193
Short name T797
Test name
Test status
Simulation time 5774684029 ps
CPU time 12.9 seconds
Started Feb 04 01:04:22 PM PST 24
Finished Feb 04 01:04:36 PM PST 24
Peak memory 201196 kb
Host smart-6ab6baf1-c9b3-4efc-9465-c101cae3bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572067193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1572067193
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1001765122
Short name T291
Test name
Test status
Simulation time 493029091139 ps
CPU time 1069.25 seconds
Started Feb 04 01:04:13 PM PST 24
Finished Feb 04 01:22:05 PM PST 24
Peak memory 201560 kb
Host smart-5d431a5f-292b-4b6a-a965-375b1a879996
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001765122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1001765122
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.133153385
Short name T504
Test name
Test status
Simulation time 164881854573 ps
CPU time 197.99 seconds
Started Feb 04 01:04:14 PM PST 24
Finished Feb 04 01:07:34 PM PST 24
Peak memory 201672 kb
Host smart-dbeacf97-8ead-49e9-802c-d8ee13d21a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133153385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.133153385
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3070344826
Short name T121
Test name
Test status
Simulation time 332292949787 ps
CPU time 355.44 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:10:17 PM PST 24
Peak memory 201592 kb
Host smart-4eae32cc-ba35-4563-b4b1-be7457cded8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070344826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3070344826
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1913930016
Short name T724
Test name
Test status
Simulation time 324124638322 ps
CPU time 172.91 seconds
Started Feb 04 01:04:18 PM PST 24
Finished Feb 04 01:07:12 PM PST 24
Peak memory 201544 kb
Host smart-b731851c-3907-415c-9f74-3fd9c5276f8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913930016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1913930016
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2482059380
Short name T652
Test name
Test status
Simulation time 492372871296 ps
CPU time 277.09 seconds
Started Feb 04 01:04:30 PM PST 24
Finished Feb 04 01:09:08 PM PST 24
Peak memory 201592 kb
Host smart-8a6379ba-805d-4582-9c00-5d3b5fc8e140
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482059380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2482059380
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2724107884
Short name T366
Test name
Test status
Simulation time 80406489900 ps
CPU time 436.98 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:12:12 PM PST 24
Peak memory 201920 kb
Host smart-d3835321-cb0c-4d47-8808-bbc3e8ae29e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724107884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2724107884
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1783856304
Short name T455
Test name
Test status
Simulation time 38904323344 ps
CPU time 10.31 seconds
Started Feb 04 01:04:45 PM PST 24
Finished Feb 04 01:05:06 PM PST 24
Peak memory 201400 kb
Host smart-c377c4a5-c1a4-4c68-8711-5b3b7962de9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783856304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1783856304
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1368326876
Short name T692
Test name
Test status
Simulation time 5474201912 ps
CPU time 4.08 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:04:59 PM PST 24
Peak memory 201384 kb
Host smart-36d5bc55-282a-4d04-a3f9-2e5539f57ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368326876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1368326876
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.361960341
Short name T755
Test name
Test status
Simulation time 5677359137 ps
CPU time 4.05 seconds
Started Feb 04 01:04:29 PM PST 24
Finished Feb 04 01:04:34 PM PST 24
Peak memory 201308 kb
Host smart-f3601ae8-5c22-4041-ad35-669feb684c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361960341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.361960341
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2982891821
Short name T271
Test name
Test status
Simulation time 462769473833 ps
CPU time 156.99 seconds
Started Feb 04 01:04:41 PM PST 24
Finished Feb 04 01:07:26 PM PST 24
Peak memory 210072 kb
Host smart-37d5610e-e561-41e8-a81d-6e1274dfcf79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982891821 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2982891821
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2387111183
Short name T584
Test name
Test status
Simulation time 480630803 ps
CPU time 0.89 seconds
Started Feb 04 01:04:38 PM PST 24
Finished Feb 04 01:04:44 PM PST 24
Peak memory 201256 kb
Host smart-2db43dba-17a4-414e-bbcd-f6676d2b665b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387111183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2387111183
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1442344553
Short name T620
Test name
Test status
Simulation time 164690196095 ps
CPU time 371.44 seconds
Started Feb 04 01:04:42 PM PST 24
Finished Feb 04 01:11:02 PM PST 24
Peak memory 201588 kb
Host smart-e5c671b4-b05c-4703-b6d8-e0f63823eee1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442344553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1442344553
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2025353617
Short name T567
Test name
Test status
Simulation time 163109945224 ps
CPU time 366.91 seconds
Started Feb 04 01:04:40 PM PST 24
Finished Feb 04 01:10:51 PM PST 24
Peak memory 201644 kb
Host smart-7ed83e22-2c56-4944-ba8f-fd4c03eec341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025353617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2025353617
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2613989164
Short name T762
Test name
Test status
Simulation time 161118163241 ps
CPU time 346.06 seconds
Started Feb 04 01:04:41 PM PST 24
Finished Feb 04 01:10:35 PM PST 24
Peak memory 201704 kb
Host smart-100fd9bb-7611-4a83-885c-88ddf822661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613989164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2613989164
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.134247403
Short name T593
Test name
Test status
Simulation time 324037364890 ps
CPU time 208.91 seconds
Started Feb 04 01:04:37 PM PST 24
Finished Feb 04 01:08:11 PM PST 24
Peak memory 201516 kb
Host smart-e11ce045-8a63-4d30-bb23-4e4406999adb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=134247403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.134247403
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1236296869
Short name T322
Test name
Test status
Simulation time 160116162711 ps
CPU time 389.46 seconds
Started Feb 04 01:04:39 PM PST 24
Finished Feb 04 01:11:13 PM PST 24
Peak memory 201440 kb
Host smart-77712acf-62cf-4743-be47-5e1cefcf5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236296869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1236296869
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1229243881
Short name T785
Test name
Test status
Simulation time 169707664630 ps
CPU time 101.29 seconds
Started Feb 04 01:04:36 PM PST 24
Finished Feb 04 01:06:23 PM PST 24
Peak memory 201592 kb
Host smart-f5091709-f2d6-472d-8883-68163f9910bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229243881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1229243881
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2917298416
Short name T614
Test name
Test status
Simulation time 494313256962 ps
CPU time 76.18 seconds
Started Feb 04 01:04:45 PM PST 24
Finished Feb 04 01:06:12 PM PST 24
Peak memory 201392 kb
Host smart-3bf9f12e-4ace-4e91-881c-0f537b284aba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917298416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2917298416
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1458169778
Short name T634
Test name
Test status
Simulation time 29649850706 ps
CPU time 17.57 seconds
Started Feb 04 01:04:41 PM PST 24
Finished Feb 04 01:05:07 PM PST 24
Peak memory 201244 kb
Host smart-0238a517-5f92-4d61-94e0-21d5634ac26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458169778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1458169778
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.128631285
Short name T451
Test name
Test status
Simulation time 3566278700 ps
CPU time 1.13 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:04:54 PM PST 24
Peak memory 201404 kb
Host smart-1bcda6de-9018-4437-96e2-83dac995a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128631285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.128631285
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3023610857
Short name T492
Test name
Test status
Simulation time 6057562559 ps
CPU time 4.65 seconds
Started Feb 04 01:04:42 PM PST 24
Finished Feb 04 01:04:55 PM PST 24
Peak memory 201356 kb
Host smart-4b3ad3d1-66c4-4ea4-9c31-95992ddd91e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023610857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3023610857
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.783943919
Short name T749
Test name
Test status
Simulation time 6058227891 ps
CPU time 3.87 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:04:58 PM PST 24
Peak memory 201348 kb
Host smart-e28c680d-82a5-476c-b6d1-79fd8386cb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783943919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
783943919
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2369731576
Short name T815
Test name
Test status
Simulation time 416004582 ps
CPU time 0.67 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:04:53 PM PST 24
Peak memory 201224 kb
Host smart-10c3760c-af29-48c8-b347-ed05fd2ea171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369731576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2369731576
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3632760479
Short name T171
Test name
Test status
Simulation time 493783529535 ps
CPU time 91.75 seconds
Started Feb 04 01:04:37 PM PST 24
Finished Feb 04 01:06:14 PM PST 24
Peak memory 201660 kb
Host smart-773db82d-abd6-44d4-9da8-51343ee95712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632760479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3632760479
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1757074581
Short name T857
Test name
Test status
Simulation time 485728235257 ps
CPU time 471.38 seconds
Started Feb 04 01:04:35 PM PST 24
Finished Feb 04 01:12:29 PM PST 24
Peak memory 201568 kb
Host smart-7434a34f-2417-4357-9c33-76bbdc98e56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757074581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1757074581
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2396257858
Short name T801
Test name
Test status
Simulation time 497499519736 ps
CPU time 324.35 seconds
Started Feb 04 01:04:45 PM PST 24
Finished Feb 04 01:10:20 PM PST 24
Peak memory 201564 kb
Host smart-b89252a8-a9ab-4c46-a0f1-6343a8501d19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396257858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2396257858
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.672757240
Short name T362
Test name
Test status
Simulation time 324623847097 ps
CPU time 173.04 seconds
Started Feb 04 01:04:40 PM PST 24
Finished Feb 04 01:07:37 PM PST 24
Peak memory 201680 kb
Host smart-2a685e74-ec2b-4118-9e2c-62c016f98546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672757240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.672757240
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.116374563
Short name T503
Test name
Test status
Simulation time 329073789460 ps
CPU time 759.34 seconds
Started Feb 04 01:04:39 PM PST 24
Finished Feb 04 01:17:23 PM PST 24
Peak memory 201520 kb
Host smart-a2a053e2-d0e7-43c0-a2ec-47efbcd6d7ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=116374563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.116374563
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.857923469
Short name T305
Test name
Test status
Simulation time 164887161492 ps
CPU time 301 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:09:56 PM PST 24
Peak memory 201628 kb
Host smart-b303fd37-4bbf-4414-908b-c3bd3f4d0459
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857923469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.857923469
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1640751771
Short name T499
Test name
Test status
Simulation time 165990697724 ps
CPU time 200.87 seconds
Started Feb 04 01:04:35 PM PST 24
Finished Feb 04 01:07:59 PM PST 24
Peak memory 201596 kb
Host smart-bc532a62-4f14-439d-a8dd-c58671e9afe5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640751771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1640751771
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1435346791
Short name T758
Test name
Test status
Simulation time 104044047607 ps
CPU time 470.42 seconds
Started Feb 04 01:04:40 PM PST 24
Finished Feb 04 01:12:39 PM PST 24
Peak memory 201948 kb
Host smart-eed67438-e387-4539-bcd6-82672be40236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435346791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1435346791
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2979862450
Short name T668
Test name
Test status
Simulation time 46331076173 ps
CPU time 9.07 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:05:01 PM PST 24
Peak memory 201236 kb
Host smart-83f9e5db-dac1-4d65-84ba-25d1b7db7986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979862450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2979862450
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1555175758
Short name T516
Test name
Test status
Simulation time 3899088097 ps
CPU time 9.94 seconds
Started Feb 04 01:04:39 PM PST 24
Finished Feb 04 01:04:53 PM PST 24
Peak memory 201196 kb
Host smart-bb9f7137-0d9b-471a-b347-146a3389b1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555175758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1555175758
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3743270742
Short name T519
Test name
Test status
Simulation time 5694066681 ps
CPU time 3.97 seconds
Started Feb 04 01:04:45 PM PST 24
Finished Feb 04 01:04:59 PM PST 24
Peak memory 201248 kb
Host smart-a2cec7de-45fb-4dcf-9cd9-417ed79cb286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743270742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3743270742
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.724515184
Short name T187
Test name
Test status
Simulation time 96677082188 ps
CPU time 137.16 seconds
Started Feb 04 01:04:38 PM PST 24
Finished Feb 04 01:07:00 PM PST 24
Peak memory 210256 kb
Host smart-95de528a-951a-408d-b0fe-8eb7398cd000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724515184 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.724515184
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1831357099
Short name T470
Test name
Test status
Simulation time 322698001 ps
CPU time 1.32 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:04:53 PM PST 24
Peak memory 201280 kb
Host smart-fb19f8e0-6007-4488-8a70-d3128c7d5af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831357099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1831357099
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1422911724
Short name T790
Test name
Test status
Simulation time 157735365340 ps
CPU time 60.22 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:05:53 PM PST 24
Peak memory 201520 kb
Host smart-8c72ab85-0252-4456-8c65-816fa82615fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422911724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1422911724
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3745503013
Short name T734
Test name
Test status
Simulation time 495919255019 ps
CPU time 284.8 seconds
Started Feb 04 01:04:37 PM PST 24
Finished Feb 04 01:09:27 PM PST 24
Peak memory 201504 kb
Host smart-b703f18c-f944-45b2-988d-145d61288fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745503013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3745503013
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2025487655
Short name T458
Test name
Test status
Simulation time 327050845670 ps
CPU time 80.2 seconds
Started Feb 04 01:04:37 PM PST 24
Finished Feb 04 01:06:02 PM PST 24
Peak memory 201148 kb
Host smart-5ec14196-194c-4c63-8092-10d825eeacb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025487655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2025487655
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2785860155
Short name T122
Test name
Test status
Simulation time 333411455626 ps
CPU time 127.33 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:07:03 PM PST 24
Peak memory 201636 kb
Host smart-a5a3a4db-a77e-4bcc-b372-6f45be50971c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785860155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2785860155
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3972982209
Short name T261
Test name
Test status
Simulation time 326091041822 ps
CPU time 355.32 seconds
Started Feb 04 01:04:36 PM PST 24
Finished Feb 04 01:10:37 PM PST 24
Peak memory 201648 kb
Host smart-d2783042-1873-4127-a925-541198294663
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972982209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3972982209
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2425168898
Short name T174
Test name
Test status
Simulation time 325505986144 ps
CPU time 714.76 seconds
Started Feb 04 01:04:37 PM PST 24
Finished Feb 04 01:16:37 PM PST 24
Peak memory 201244 kb
Host smart-d947bd44-8d76-4bb4-94f3-a2d1364b05ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425168898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2425168898
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1139895871
Short name T798
Test name
Test status
Simulation time 25649898411 ps
CPU time 59.05 seconds
Started Feb 04 01:04:39 PM PST 24
Finished Feb 04 01:05:42 PM PST 24
Peak memory 201436 kb
Host smart-4db5af16-4095-4b5b-a347-51bc8032c762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139895871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1139895871
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1202669990
Short name T452
Test name
Test status
Simulation time 4414819180 ps
CPU time 11.15 seconds
Started Feb 04 01:04:46 PM PST 24
Finished Feb 04 01:05:06 PM PST 24
Peak memory 201128 kb
Host smart-8a350cde-2d7e-46a6-ba2e-1d3b5314de17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202669990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1202669990
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.479147978
Short name T820
Test name
Test status
Simulation time 6084560063 ps
CPU time 14.97 seconds
Started Feb 04 01:04:40 PM PST 24
Finished Feb 04 01:04:59 PM PST 24
Peak memory 201428 kb
Host smart-492e49d5-53a1-42e7-a6bb-1c88d3d36d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479147978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.479147978
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1243556605
Short name T824
Test name
Test status
Simulation time 123047632733 ps
CPU time 50.29 seconds
Started Feb 04 01:04:46 PM PST 24
Finished Feb 04 01:05:46 PM PST 24
Peak memory 218200 kb
Host smart-4e153e27-807f-45b7-a3dc-2a64ae8a5ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243556605 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1243556605
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2947991063
Short name T439
Test name
Test status
Simulation time 364306035 ps
CPU time 0.72 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:04:54 PM PST 24
Peak memory 201216 kb
Host smart-9918d1a4-3e89-46eb-854e-07effeaedd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947991063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2947991063
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.624611198
Short name T100
Test name
Test status
Simulation time 332987955639 ps
CPU time 213.79 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:08:29 PM PST 24
Peak memory 201520 kb
Host smart-09f75e6f-3245-4212-bdcd-7cef955fcf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624611198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.624611198
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1562699249
Short name T706
Test name
Test status
Simulation time 492811909188 ps
CPU time 620.04 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:15:14 PM PST 24
Peak memory 201584 kb
Host smart-02fc618a-2022-4b76-93bb-ab87af2027c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562699249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1562699249
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2139602400
Short name T834
Test name
Test status
Simulation time 333591024622 ps
CPU time 850.6 seconds
Started Feb 04 01:04:48 PM PST 24
Finished Feb 04 01:19:06 PM PST 24
Peak memory 201500 kb
Host smart-8667dbd5-9499-4c69-b655-9d01acc6f1ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139602400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2139602400
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.728640584
Short name T579
Test name
Test status
Simulation time 501194244022 ps
CPU time 1244.45 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:25:40 PM PST 24
Peak memory 201588 kb
Host smart-80d04e0f-4063-4d40-aad2-a731ad13b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728640584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.728640584
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1794567749
Short name T505
Test name
Test status
Simulation time 326670572991 ps
CPU time 195.6 seconds
Started Feb 04 01:04:46 PM PST 24
Finished Feb 04 01:08:11 PM PST 24
Peak memory 201632 kb
Host smart-480b8fce-2ea4-4129-9819-61acdfa5ee7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794567749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1794567749
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.329347815
Short name T357
Test name
Test status
Simulation time 333386202052 ps
CPU time 738.16 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:17:12 PM PST 24
Peak memory 201652 kb
Host smart-77d430a1-04a4-46de-8442-89f69ad497e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329347815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.329347815
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3580693317
Short name T633
Test name
Test status
Simulation time 159092720689 ps
CPU time 56.22 seconds
Started Feb 04 01:04:48 PM PST 24
Finished Feb 04 01:05:52 PM PST 24
Peak memory 201568 kb
Host smart-2afecc0d-e8c5-48d1-840e-0373477fe95c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580693317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3580693317
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.190536946
Short name T772
Test name
Test status
Simulation time 72888027529 ps
CPU time 257.53 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:09:13 PM PST 24
Peak memory 201880 kb
Host smart-aa09597e-891b-4e79-a48d-2c30748ea85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190536946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.190536946
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4271223707
Short name T468
Test name
Test status
Simulation time 32051684315 ps
CPU time 22.59 seconds
Started Feb 04 01:04:47 PM PST 24
Finished Feb 04 01:05:18 PM PST 24
Peak memory 201336 kb
Host smart-0858b7d1-c674-4301-a26a-17246b5384d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271223707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4271223707
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1738649837
Short name T787
Test name
Test status
Simulation time 5172648622 ps
CPU time 12.48 seconds
Started Feb 04 01:04:48 PM PST 24
Finished Feb 04 01:05:08 PM PST 24
Peak memory 201332 kb
Host smart-6a6127c9-47d8-443d-9828-bd74a31e1df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738649837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1738649837
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2783502864
Short name T185
Test name
Test status
Simulation time 5754612777 ps
CPU time 8.37 seconds
Started Feb 04 01:04:45 PM PST 24
Finished Feb 04 01:05:04 PM PST 24
Peak memory 201264 kb
Host smart-9b2ac4f3-3d93-4bc7-8068-1e194eee2b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783502864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2783502864
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3687674134
Short name T618
Test name
Test status
Simulation time 330793730 ps
CPU time 0.82 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:05:08 PM PST 24
Peak memory 201240 kb
Host smart-540b5f49-01ba-4ced-b79c-0107aa643787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687674134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3687674134
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.473862533
Short name T731
Test name
Test status
Simulation time 159308031332 ps
CPU time 100.55 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:06:49 PM PST 24
Peak memory 201648 kb
Host smart-dc4ac004-2a8a-4a6b-8c93-b22176806869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473862533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.473862533
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.514269525
Short name T129
Test name
Test status
Simulation time 490891041534 ps
CPU time 727.03 seconds
Started Feb 04 01:04:50 PM PST 24
Finished Feb 04 01:17:04 PM PST 24
Peak memory 201648 kb
Host smart-d3c316fa-9bca-46e7-8cfd-f095d76c636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514269525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.514269525
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3991855504
Short name T640
Test name
Test status
Simulation time 328418190330 ps
CPU time 537.3 seconds
Started Feb 04 01:04:42 PM PST 24
Finished Feb 04 01:13:48 PM PST 24
Peak memory 201540 kb
Host smart-6df4555d-e18b-439a-acf4-fecf0e175d5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991855504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3991855504
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4282794112
Short name T145
Test name
Test status
Simulation time 321658501342 ps
CPU time 47.22 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:05:43 PM PST 24
Peak memory 201580 kb
Host smart-ec004de1-dac1-44d6-bde3-e0a9e8753f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282794112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4282794112
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3862060993
Short name T335
Test name
Test status
Simulation time 490722018938 ps
CPU time 896.12 seconds
Started Feb 04 01:04:48 PM PST 24
Finished Feb 04 01:19:52 PM PST 24
Peak memory 201580 kb
Host smart-832e1cc7-8f26-4604-b7d6-6024fad30da5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862060993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3862060993
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1592441640
Short name T559
Test name
Test status
Simulation time 493669162422 ps
CPU time 256.87 seconds
Started Feb 04 01:04:48 PM PST 24
Finished Feb 04 01:09:12 PM PST 24
Peak memory 201568 kb
Host smart-d13e7cde-dc3b-48be-b103-21c01d554450
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592441640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1592441640
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2804599485
Short name T18
Test name
Test status
Simulation time 117848569266 ps
CPU time 382.41 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:11:29 PM PST 24
Peak memory 201868 kb
Host smart-88eec31b-1cce-4bec-9e0e-230a52159a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804599485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2804599485
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3585112630
Short name T769
Test name
Test status
Simulation time 21147811908 ps
CPU time 12.9 seconds
Started Feb 04 01:04:50 PM PST 24
Finished Feb 04 01:05:10 PM PST 24
Peak memory 201232 kb
Host smart-d59da1d1-ada4-41b0-8738-d707ca7e01fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585112630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3585112630
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1274670703
Short name T720
Test name
Test status
Simulation time 3474206432 ps
CPU time 2.71 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:05:10 PM PST 24
Peak memory 201384 kb
Host smart-d5fec530-7129-4046-ac37-015016b23551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274670703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1274670703
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3027984913
Short name T430
Test name
Test status
Simulation time 5585340807 ps
CPU time 7.4 seconds
Started Feb 04 01:04:48 PM PST 24
Finished Feb 04 01:05:03 PM PST 24
Peak memory 201280 kb
Host smart-48caec3d-c193-47dd-9673-2866a0e33cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027984913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3027984913
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.947470729
Short name T796
Test name
Test status
Simulation time 208467278247 ps
CPU time 453.21 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:12:41 PM PST 24
Peak memory 201352 kb
Host smart-26ccff9a-b50c-44af-92bd-916729c8c98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947470729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
947470729
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1273114341
Short name T825
Test name
Test status
Simulation time 123928085090 ps
CPU time 179.09 seconds
Started Feb 04 01:04:50 PM PST 24
Finished Feb 04 01:07:56 PM PST 24
Peak memory 210304 kb
Host smart-f7ebc3ba-5996-44a9-8eac-cef6471f901b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273114341 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1273114341
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2764115036
Short name T151
Test name
Test status
Simulation time 363777137 ps
CPU time 0.88 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:05:09 PM PST 24
Peak memory 201392 kb
Host smart-a8f04f46-ce32-4525-9e0c-71bb22251735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764115036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2764115036
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3119797524
Short name T224
Test name
Test status
Simulation time 169710330355 ps
CPU time 94.58 seconds
Started Feb 04 01:04:54 PM PST 24
Finished Feb 04 01:06:33 PM PST 24
Peak memory 201648 kb
Host smart-6e386dd0-e26d-4cf9-a757-3c7b1accb7fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119797524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3119797524
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2392487938
Short name T179
Test name
Test status
Simulation time 179618678007 ps
CPU time 76.09 seconds
Started Feb 04 01:04:54 PM PST 24
Finished Feb 04 01:06:14 PM PST 24
Peak memory 201656 kb
Host smart-f1cf75d3-c68d-4ac0-911c-15019d676881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392487938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2392487938
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.212889114
Short name T661
Test name
Test status
Simulation time 491968860639 ps
CPU time 1123.01 seconds
Started Feb 04 01:04:50 PM PST 24
Finished Feb 04 01:23:40 PM PST 24
Peak memory 201652 kb
Host smart-2afd458e-6df0-4466-b049-2ca8b531943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212889114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.212889114
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2924645722
Short name T537
Test name
Test status
Simulation time 494090440031 ps
CPU time 1076.4 seconds
Started Feb 04 01:04:54 PM PST 24
Finished Feb 04 01:22:55 PM PST 24
Peak memory 201544 kb
Host smart-55cd58a8-0729-4169-8412-14b65f40899e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924645722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2924645722
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3105904070
Short name T740
Test name
Test status
Simulation time 325252429624 ps
CPU time 342.12 seconds
Started Feb 04 01:04:50 PM PST 24
Finished Feb 04 01:10:39 PM PST 24
Peak memory 201528 kb
Host smart-40aa6fb8-05a4-4d77-a383-2ec3c1ddd5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105904070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3105904070
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2322200219
Short name T750
Test name
Test status
Simulation time 331463474062 ps
CPU time 45.76 seconds
Started Feb 04 01:04:50 PM PST 24
Finished Feb 04 01:05:43 PM PST 24
Peak memory 201636 kb
Host smart-da3a516e-cd48-498c-a027-d82c89801011
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322200219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2322200219
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3763804323
Short name T654
Test name
Test status
Simulation time 331643035039 ps
CPU time 193.59 seconds
Started Feb 04 01:04:54 PM PST 24
Finished Feb 04 01:08:12 PM PST 24
Peak memory 201640 kb
Host smart-7704ccca-a6ce-4723-8703-1451260e5d91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763804323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3763804323
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1074506556
Short name T721
Test name
Test status
Simulation time 121468892129 ps
CPU time 561.9 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:14:15 PM PST 24
Peak memory 201840 kb
Host smart-a49f33fa-1d19-44ab-94d4-fc525e13d614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074506556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1074506556
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2973510384
Short name T695
Test name
Test status
Simulation time 44018809612 ps
CPU time 20.34 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:05:14 PM PST 24
Peak memory 201380 kb
Host smart-b915ee49-7bea-4482-8e7c-35cb9599cf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973510384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2973510384
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2351993792
Short name T843
Test name
Test status
Simulation time 3210266990 ps
CPU time 3.1 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:05:11 PM PST 24
Peak memory 201116 kb
Host smart-87ac9e08-5cdd-4291-b7d3-e95f5df00c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351993792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2351993792
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3007158569
Short name T486
Test name
Test status
Simulation time 5915298951 ps
CPU time 14.81 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:05:22 PM PST 24
Peak memory 201380 kb
Host smart-4e2c96f5-4faa-486e-bba0-c4b5f68abeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007158569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3007158569
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1302726218
Short name T201
Test name
Test status
Simulation time 1000234370379 ps
CPU time 1053.1 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:22:41 PM PST 24
Peak memory 210208 kb
Host smart-a39a93d1-03a1-4408-b00b-2855e298d2f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302726218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1302726218
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2291204872
Short name T782
Test name
Test status
Simulation time 532749175 ps
CPU time 0.89 seconds
Started Feb 04 01:03:13 PM PST 24
Finished Feb 04 01:03:15 PM PST 24
Peak memory 201264 kb
Host smart-fc9ec813-6293-48b3-861c-810c1d7ca662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291204872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2291204872
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.157679018
Short name T309
Test name
Test status
Simulation time 167658534002 ps
CPU time 76.92 seconds
Started Feb 04 01:03:17 PM PST 24
Finished Feb 04 01:04:37 PM PST 24
Peak memory 201660 kb
Host smart-658b2f20-c558-44cd-8c96-cb837faefd18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157679018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.157679018
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3849297744
Short name T269
Test name
Test status
Simulation time 164262209003 ps
CPU time 356.34 seconds
Started Feb 04 01:03:14 PM PST 24
Finished Feb 04 01:09:12 PM PST 24
Peak memory 201600 kb
Host smart-5d7370ab-d299-42ea-945e-ddf73f48a3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849297744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3849297744
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1477892130
Short name T659
Test name
Test status
Simulation time 325951302336 ps
CPU time 388.98 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:09:49 PM PST 24
Peak memory 201652 kb
Host smart-5cfe7b5c-6403-4195-b85d-2599e81726e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477892130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1477892130
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.4005711584
Short name T306
Test name
Test status
Simulation time 160766489732 ps
CPU time 348.38 seconds
Started Feb 04 01:03:17 PM PST 24
Finished Feb 04 01:09:09 PM PST 24
Peak memory 201556 kb
Host smart-4d95090b-f379-495d-bea9-6fd418ca7275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005711584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.4005711584
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2419035533
Short name T577
Test name
Test status
Simulation time 333980040489 ps
CPU time 81.83 seconds
Started Feb 04 01:03:16 PM PST 24
Finished Feb 04 01:04:40 PM PST 24
Peak memory 201572 kb
Host smart-5aefa2e6-fd3d-472c-8baf-9db8b672aa6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419035533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2419035533
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1407382281
Short name T237
Test name
Test status
Simulation time 324717906951 ps
CPU time 716.61 seconds
Started Feb 04 01:03:13 PM PST 24
Finished Feb 04 01:15:11 PM PST 24
Peak memory 201576 kb
Host smart-2bf612c7-d081-4f71-abda-16a0ecbced41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407382281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1407382281
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4117464767
Short name T545
Test name
Test status
Simulation time 166670619074 ps
CPU time 378.39 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:09:39 PM PST 24
Peak memory 201076 kb
Host smart-4dc96c35-4e06-46a8-9207-18c0c1953d39
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117464767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.4117464767
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1314308002
Short name T742
Test name
Test status
Simulation time 115694543918 ps
CPU time 582.9 seconds
Started Feb 04 01:03:19 PM PST 24
Finished Feb 04 01:13:04 PM PST 24
Peak memory 201860 kb
Host smart-78aeea5a-e99d-4b76-86a0-694bc929c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314308002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1314308002
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.133721081
Short name T594
Test name
Test status
Simulation time 27566672382 ps
CPU time 64.08 seconds
Started Feb 04 01:03:21 PM PST 24
Finished Feb 04 01:04:26 PM PST 24
Peak memory 201372 kb
Host smart-d806fc5b-5ec5-4112-8ddb-2aac79e6b705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133721081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.133721081
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3097612798
Short name T515
Test name
Test status
Simulation time 4698721705 ps
CPU time 3.31 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:03:24 PM PST 24
Peak memory 201396 kb
Host smart-16c4e355-4d10-4aa0-9dd8-30e603bfb899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097612798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3097612798
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2967981989
Short name T45
Test name
Test status
Simulation time 4340833164 ps
CPU time 3.23 seconds
Started Feb 04 01:03:18 PM PST 24
Finished Feb 04 01:03:24 PM PST 24
Peak memory 216636 kb
Host smart-156c7513-9212-44d0-b069-91c9b33b3b1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967981989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2967981989
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4054515869
Short name T690
Test name
Test status
Simulation time 5688105841 ps
CPU time 12.22 seconds
Started Feb 04 01:03:16 PM PST 24
Finished Feb 04 01:03:31 PM PST 24
Peak memory 201372 kb
Host smart-47647db8-170b-4b11-8ffc-11220faeb8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054515869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4054515869
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.329026557
Short name T789
Test name
Test status
Simulation time 74470509299 ps
CPU time 45.17 seconds
Started Feb 04 01:03:17 PM PST 24
Finished Feb 04 01:04:06 PM PST 24
Peak memory 210024 kb
Host smart-a7aca53a-67b5-4585-b7f3-14285ec12dc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329026557 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.329026557
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2192900288
Short name T557
Test name
Test status
Simulation time 336624544 ps
CPU time 0.73 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:05:04 PM PST 24
Peak memory 201212 kb
Host smart-7a223a37-0ff0-4e17-9099-9c42a8c64aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192900288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2192900288
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1677309878
Short name T802
Test name
Test status
Simulation time 156658533597 ps
CPU time 36.96 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:05:40 PM PST 24
Peak memory 201616 kb
Host smart-a7c74dff-cb15-4b86-a1d2-298fe8589d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677309878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1677309878
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3185085693
Short name T811
Test name
Test status
Simulation time 326513315440 ps
CPU time 185.39 seconds
Started Feb 04 01:04:57 PM PST 24
Finished Feb 04 01:08:06 PM PST 24
Peak memory 201580 kb
Host smart-c6ae97c8-b506-4310-a1eb-55566a54017c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185085693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3185085693
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.4229610129
Short name T576
Test name
Test status
Simulation time 329923899611 ps
CPU time 189.51 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:08:13 PM PST 24
Peak memory 201548 kb
Host smart-c79cea30-7c6a-48f3-8435-71d262b15b5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229610129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.4229610129
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1937301178
Short name T868
Test name
Test status
Simulation time 160479005214 ps
CPU time 208.3 seconds
Started Feb 04 01:04:47 PM PST 24
Finished Feb 04 01:08:24 PM PST 24
Peak memory 201608 kb
Host smart-ddbe7555-4f85-4068-ae1a-8332471e9de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937301178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1937301178
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3273110548
Short name T466
Test name
Test status
Simulation time 484878512111 ps
CPU time 1042.16 seconds
Started Feb 04 01:04:54 PM PST 24
Finished Feb 04 01:22:21 PM PST 24
Peak memory 201584 kb
Host smart-0f200bda-ce3f-43ba-a586-a1b24fa7146a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273110548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3273110548
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2565186742
Short name T297
Test name
Test status
Simulation time 335989952387 ps
CPU time 216.19 seconds
Started Feb 04 01:05:00 PM PST 24
Finished Feb 04 01:08:41 PM PST 24
Peak memory 201744 kb
Host smart-b7634e51-6b7a-4b75-ac28-73748960f65a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565186742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2565186742
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1421573369
Short name T663
Test name
Test status
Simulation time 493277435700 ps
CPU time 260.31 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:09:13 PM PST 24
Peak memory 201652 kb
Host smart-b6793365-bbcf-497e-9aaf-ab9566817409
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421573369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1421573369
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.135721009
Short name T197
Test name
Test status
Simulation time 111954813957 ps
CPU time 464.42 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:12:47 PM PST 24
Peak memory 201868 kb
Host smart-e61277ef-a905-4ff7-b5eb-92efc6e774f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135721009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.135721009
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1285344432
Short name T509
Test name
Test status
Simulation time 33366221076 ps
CPU time 18.87 seconds
Started Feb 04 01:04:53 PM PST 24
Finished Feb 04 01:05:16 PM PST 24
Peak memory 201412 kb
Host smart-09afc73d-f123-4d1b-8b4b-0d6cce5c9ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285344432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1285344432
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.121155793
Short name T551
Test name
Test status
Simulation time 4052704625 ps
CPU time 10.06 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:05:18 PM PST 24
Peak memory 201376 kb
Host smart-e683290d-8629-4edf-92ba-14d8b0c64835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121155793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.121155793
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.241282590
Short name T752
Test name
Test status
Simulation time 5830595472 ps
CPU time 4.25 seconds
Started Feb 04 01:04:56 PM PST 24
Finished Feb 04 01:05:05 PM PST 24
Peak memory 201332 kb
Host smart-c4992d8b-8002-4542-af87-4149b2794810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241282590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.241282590
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.225303764
Short name T347
Test name
Test status
Simulation time 527810089577 ps
CPU time 317.77 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:10:21 PM PST 24
Peak memory 201524 kb
Host smart-c9ba9451-b395-462a-964b-880316d1fb9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225303764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
225303764
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2945304640
Short name T521
Test name
Test status
Simulation time 68339146653 ps
CPU time 265.64 seconds
Started Feb 04 01:04:57 PM PST 24
Finished Feb 04 01:09:28 PM PST 24
Peak memory 210244 kb
Host smart-8a43fad1-c305-451b-afc3-b93cbbe3007f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945304640 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2945304640
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2986272917
Short name T741
Test name
Test status
Simulation time 330071094 ps
CPU time 0.79 seconds
Started Feb 04 01:04:57 PM PST 24
Finished Feb 04 01:05:02 PM PST 24
Peak memory 201280 kb
Host smart-b2a296a6-61ac-4cf4-8b1e-bb0bb64da9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986272917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2986272917
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3534856239
Short name T161
Test name
Test status
Simulation time 362848727281 ps
CPU time 153.09 seconds
Started Feb 04 01:04:57 PM PST 24
Finished Feb 04 01:07:35 PM PST 24
Peak memory 201516 kb
Host smart-34c8f6a0-8e57-49f7-9621-5a6b797cf74c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534856239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3534856239
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.303072351
Short name T146
Test name
Test status
Simulation time 333932781094 ps
CPU time 150.53 seconds
Started Feb 04 01:05:00 PM PST 24
Finished Feb 04 01:07:36 PM PST 24
Peak memory 201788 kb
Host smart-4aae56a6-ce1c-45c6-89fa-eade619159bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303072351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.303072351
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.742336802
Short name T725
Test name
Test status
Simulation time 161481837251 ps
CPU time 413.33 seconds
Started Feb 04 01:05:00 PM PST 24
Finished Feb 04 01:11:59 PM PST 24
Peak memory 201696 kb
Host smart-04a5fc7a-ea51-4cd4-9198-118d89d9f270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742336802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.742336802
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1341042087
Short name T447
Test name
Test status
Simulation time 326208730216 ps
CPU time 355.17 seconds
Started Feb 04 01:05:00 PM PST 24
Finished Feb 04 01:11:00 PM PST 24
Peak memory 201684 kb
Host smart-21a4fcf6-c6fb-4dc5-adbc-64022886c4b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341042087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1341042087
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2034450113
Short name T595
Test name
Test status
Simulation time 157519929608 ps
CPU time 363.92 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:11:12 PM PST 24
Peak memory 201756 kb
Host smart-edd140e1-8f59-4b60-9878-1281f08b9e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034450113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2034450113
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1526831823
Short name T489
Test name
Test status
Simulation time 494746565156 ps
CPU time 253.72 seconds
Started Feb 04 01:04:54 PM PST 24
Finished Feb 04 01:09:12 PM PST 24
Peak memory 201580 kb
Host smart-b3e04e21-780f-43f8-9cfb-f1e3bf03de9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526831823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1526831823
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.511994377
Short name T674
Test name
Test status
Simulation time 166847330216 ps
CPU time 188.83 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:08:17 PM PST 24
Peak memory 201612 kb
Host smart-26ba5d91-d396-42eb-954c-7c5e9e2bc181
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511994377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.511994377
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.527604712
Short name T715
Test name
Test status
Simulation time 101703919506 ps
CPU time 569.83 seconds
Started Feb 04 01:04:42 PM PST 24
Finished Feb 04 01:14:20 PM PST 24
Peak memory 201852 kb
Host smart-00d11e4b-8211-4a99-a809-8bf48850eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527604712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.527604712
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1676460560
Short name T123
Test name
Test status
Simulation time 43706603150 ps
CPU time 38.86 seconds
Started Feb 04 01:04:57 PM PST 24
Finished Feb 04 01:05:40 PM PST 24
Peak memory 201412 kb
Host smart-01626f3e-9feb-4e22-adff-131d1ccb9428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676460560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1676460560
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.82434933
Short name T523
Test name
Test status
Simulation time 4799431533 ps
CPU time 2.84 seconds
Started Feb 04 01:05:02 PM PST 24
Finished Feb 04 01:05:11 PM PST 24
Peak memory 200844 kb
Host smart-42edadb3-b957-4bf4-a49b-00ba765dc0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82434933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.82434933
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1870851275
Short name T833
Test name
Test status
Simulation time 5898367453 ps
CPU time 14.28 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:05:07 PM PST 24
Peak memory 201376 kb
Host smart-ce9e6d8a-df53-4dba-8453-4fa30c7c3de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870851275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1870851275
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2209095399
Short name T840
Test name
Test status
Simulation time 115925491488 ps
CPU time 577.68 seconds
Started Feb 04 01:05:02 PM PST 24
Finished Feb 04 01:14:46 PM PST 24
Peak memory 201680 kb
Host smart-e5e5c3c4-d8ed-4b36-9588-fe9918716f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209095399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2209095399
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2438098032
Short name T166
Test name
Test status
Simulation time 62405571469 ps
CPU time 160.82 seconds
Started Feb 04 01:04:57 PM PST 24
Finished Feb 04 01:07:41 PM PST 24
Peak memory 217620 kb
Host smart-44050653-c86f-4963-8aa0-8858a4f75510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438098032 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2438098032
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.182164438
Short name T813
Test name
Test status
Simulation time 496666844 ps
CPU time 1.19 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:05:09 PM PST 24
Peak memory 201288 kb
Host smart-63efcab2-c77b-4eb1-a0da-014df0f0ff46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182164438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.182164438
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1062102002
Short name T601
Test name
Test status
Simulation time 164615148282 ps
CPU time 78.48 seconds
Started Feb 04 01:04:57 PM PST 24
Finished Feb 04 01:06:20 PM PST 24
Peak memory 201648 kb
Host smart-75586e25-93c0-46a0-b70e-f5a680f10233
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062102002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1062102002
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2078243646
Short name T260
Test name
Test status
Simulation time 488459380863 ps
CPU time 568.01 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:14:36 PM PST 24
Peak memory 201624 kb
Host smart-de0c4820-e078-4e16-b1eb-135628aaa615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078243646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2078243646
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2655314407
Short name T464
Test name
Test status
Simulation time 166277762779 ps
CPU time 184.76 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:08:08 PM PST 24
Peak memory 201608 kb
Host smart-51cac63c-9161-466d-98d3-4eddb59d0454
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655314407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2655314407
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1351546363
Short name T97
Test name
Test status
Simulation time 501915751065 ps
CPU time 1182.67 seconds
Started Feb 04 01:05:02 PM PST 24
Finished Feb 04 01:24:51 PM PST 24
Peak memory 201564 kb
Host smart-3ce663c7-159c-47c5-b812-fd7b84321dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351546363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1351546363
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1192655538
Short name T495
Test name
Test status
Simulation time 160601363977 ps
CPU time 96.24 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:06:39 PM PST 24
Peak memory 201640 kb
Host smart-f6015eed-c456-4383-b727-14388ae21b0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192655538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1192655538
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.282865581
Short name T334
Test name
Test status
Simulation time 513560708254 ps
CPU time 582.74 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:14:46 PM PST 24
Peak memory 201620 kb
Host smart-ccb7ed6f-0eaa-4bff-aef6-7fc0a72dbae0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282865581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.282865581
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1377558002
Short name T617
Test name
Test status
Simulation time 322662745375 ps
CPU time 354.96 seconds
Started Feb 04 01:04:57 PM PST 24
Finished Feb 04 01:10:57 PM PST 24
Peak memory 201580 kb
Host smart-e3670bcd-540a-429a-a54d-98c6d5bb7015
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377558002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1377558002
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3581058824
Short name T491
Test name
Test status
Simulation time 113538825247 ps
CPU time 641.01 seconds
Started Feb 04 01:04:44 PM PST 24
Finished Feb 04 01:15:36 PM PST 24
Peak memory 201876 kb
Host smart-68c616ec-00b4-4805-9c52-ef2ffd46bac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581058824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3581058824
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.161518417
Short name T630
Test name
Test status
Simulation time 27373982119 ps
CPU time 15.32 seconds
Started Feb 04 01:04:43 PM PST 24
Finished Feb 04 01:05:09 PM PST 24
Peak memory 201424 kb
Host smart-7115922e-72cf-4479-a190-69539a251071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161518417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.161518417
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3417883759
Short name T585
Test name
Test status
Simulation time 3383166569 ps
CPU time 8.3 seconds
Started Feb 04 01:04:56 PM PST 24
Finished Feb 04 01:05:08 PM PST 24
Peak memory 201412 kb
Host smart-d3b0027f-6b09-4d90-a63d-5d6efcd5d5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417883759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3417883759
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3023566345
Short name T608
Test name
Test status
Simulation time 5650868625 ps
CPU time 12.9 seconds
Started Feb 04 01:04:58 PM PST 24
Finished Feb 04 01:05:16 PM PST 24
Peak memory 201336 kb
Host smart-8b32c3f9-b7b3-4172-935f-e75e56384462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023566345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3023566345
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.4265907702
Short name T589
Test name
Test status
Simulation time 174248847272 ps
CPU time 427.9 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:12:16 PM PST 24
Peak memory 201616 kb
Host smart-12623c98-4927-4f47-9762-e290d11c48bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265907702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.4265907702
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1096460293
Short name T39
Test name
Test status
Simulation time 317698064 ps
CPU time 0.79 seconds
Started Feb 04 01:05:22 PM PST 24
Finished Feb 04 01:05:25 PM PST 24
Peak memory 201264 kb
Host smart-46f9d48e-b091-4f72-a743-4917b378d9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096460293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1096460293
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3269481591
Short name T328
Test name
Test status
Simulation time 331106037488 ps
CPU time 182.83 seconds
Started Feb 04 01:05:05 PM PST 24
Finished Feb 04 01:08:17 PM PST 24
Peak memory 201644 kb
Host smart-dc515763-0e76-4f7f-b56f-0144d94f5941
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269481591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3269481591
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2919243390
Short name T747
Test name
Test status
Simulation time 162177331693 ps
CPU time 333.91 seconds
Started Feb 04 01:05:06 PM PST 24
Finished Feb 04 01:10:48 PM PST 24
Peak memory 201592 kb
Host smart-28c6ce55-3252-4a83-957d-eae2a8922f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919243390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2919243390
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1956781368
Short name T51
Test name
Test status
Simulation time 321630340140 ps
CPU time 734.16 seconds
Started Feb 04 01:05:03 PM PST 24
Finished Feb 04 01:17:27 PM PST 24
Peak memory 201644 kb
Host smart-d0b344b7-3c82-42c3-b4f5-564cb79ff1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956781368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1956781368
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2456361451
Short name T622
Test name
Test status
Simulation time 490464471248 ps
CPU time 479.2 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:13:07 PM PST 24
Peak memory 201568 kb
Host smart-7ff03275-4ba8-450e-b7fb-92eed3ad06d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456361451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2456361451
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2243781758
Short name T262
Test name
Test status
Simulation time 489564400131 ps
CPU time 515.23 seconds
Started Feb 04 01:05:13 PM PST 24
Finished Feb 04 01:13:51 PM PST 24
Peak memory 201652 kb
Host smart-f6563098-e085-48b3-be25-e52fa0ff7fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243781758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2243781758
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1901024970
Short name T693
Test name
Test status
Simulation time 490933956940 ps
CPU time 548.34 seconds
Started Feb 04 01:05:02 PM PST 24
Finished Feb 04 01:14:17 PM PST 24
Peak memory 201628 kb
Host smart-a1afdbf6-49a1-4fdc-843f-e9221dbf269c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901024970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1901024970
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2646331325
Short name T250
Test name
Test status
Simulation time 493766594446 ps
CPU time 683.73 seconds
Started Feb 04 01:05:22 PM PST 24
Finished Feb 04 01:16:48 PM PST 24
Peak memory 201568 kb
Host smart-af9ffc0c-e9fd-4809-b2e2-2ec0cf5dfaf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646331325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2646331325
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2634100158
Short name T444
Test name
Test status
Simulation time 324358624153 ps
CPU time 162.35 seconds
Started Feb 04 01:05:04 PM PST 24
Finished Feb 04 01:07:56 PM PST 24
Peak memory 201596 kb
Host smart-b66d412d-95ab-435e-aac9-ddab8bdb0df8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634100158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2634100158
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1785331351
Short name T792
Test name
Test status
Simulation time 110167480193 ps
CPU time 609.76 seconds
Started Feb 04 01:05:02 PM PST 24
Finished Feb 04 01:15:18 PM PST 24
Peak memory 201840 kb
Host smart-c3d55694-3167-41a7-9766-f3c4c1540573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785331351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1785331351
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3483121589
Short name T573
Test name
Test status
Simulation time 46386809976 ps
CPU time 6.17 seconds
Started Feb 04 01:05:01 PM PST 24
Finished Feb 04 01:05:13 PM PST 24
Peak memory 201388 kb
Host smart-6b2bd110-5dbe-4290-ad38-b79a2c20a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483121589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3483121589
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3340099549
Short name T628
Test name
Test status
Simulation time 4943257526 ps
CPU time 1.41 seconds
Started Feb 04 01:05:00 PM PST 24
Finished Feb 04 01:05:07 PM PST 24
Peak memory 201404 kb
Host smart-2c66f5f2-525c-4bda-9d73-c96a28de8434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340099549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3340099549
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3496259697
Short name T610
Test name
Test status
Simulation time 5852006821 ps
CPU time 15.97 seconds
Started Feb 04 01:05:02 PM PST 24
Finished Feb 04 01:05:24 PM PST 24
Peak memory 201408 kb
Host smart-bb77df17-48fe-4077-aa34-e2627c0a550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496259697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3496259697
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1614687067
Short name T167
Test name
Test status
Simulation time 270596135592 ps
CPU time 410.75 seconds
Started Feb 04 01:05:24 PM PST 24
Finished Feb 04 01:12:17 PM PST 24
Peak memory 211932 kb
Host smart-26724e61-887c-4832-b8ed-07319bb46c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614687067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1614687067
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3958260432
Short name T361
Test name
Test status
Simulation time 72262766198 ps
CPU time 40.59 seconds
Started Feb 04 01:05:26 PM PST 24
Finished Feb 04 01:06:07 PM PST 24
Peak memory 201808 kb
Host smart-dd09b2f6-cf0e-4267-ab3f-f8d27a384b85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958260432 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3958260432
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3104323641
Short name T583
Test name
Test status
Simulation time 488630274 ps
CPU time 0.9 seconds
Started Feb 04 01:05:24 PM PST 24
Finished Feb 04 01:05:27 PM PST 24
Peak memory 201156 kb
Host smart-6c76f870-0ce4-407c-8374-ff6bebff7405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104323641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3104323641
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.57391931
Short name T555
Test name
Test status
Simulation time 165576718131 ps
CPU time 157.81 seconds
Started Feb 04 01:05:24 PM PST 24
Finished Feb 04 01:08:04 PM PST 24
Peak memory 201584 kb
Host smart-f4e58165-959d-4109-beeb-08f846fe1657
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57391931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gatin
g.57391931
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1102548754
Short name T673
Test name
Test status
Simulation time 486398022637 ps
CPU time 82.9 seconds
Started Feb 04 01:05:26 PM PST 24
Finished Feb 04 01:06:50 PM PST 24
Peak memory 201624 kb
Host smart-04335769-64c5-4df8-b918-54b7a831df9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102548754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1102548754
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3028924954
Short name T570
Test name
Test status
Simulation time 337831249588 ps
CPU time 202.51 seconds
Started Feb 04 01:05:19 PM PST 24
Finished Feb 04 01:08:42 PM PST 24
Peak memory 201660 kb
Host smart-30877bdc-b665-43f3-8903-a906d54e72b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028924954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3028924954
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.435136100
Short name T677
Test name
Test status
Simulation time 168717657872 ps
CPU time 93.9 seconds
Started Feb 04 01:05:24 PM PST 24
Finished Feb 04 01:07:00 PM PST 24
Peak memory 201644 kb
Host smart-c6ccd570-c308-4cee-aa76-d49d56bd57c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=435136100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.435136100
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3593688130
Short name T170
Test name
Test status
Simulation time 496461422980 ps
CPU time 286.74 seconds
Started Feb 04 01:05:21 PM PST 24
Finished Feb 04 01:10:11 PM PST 24
Peak memory 201536 kb
Host smart-56fe46a7-2433-413a-a2bf-e969cefca317
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593688130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3593688130
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3487787136
Short name T682
Test name
Test status
Simulation time 487990649237 ps
CPU time 579.28 seconds
Started Feb 04 01:05:16 PM PST 24
Finished Feb 04 01:14:56 PM PST 24
Peak memory 201504 kb
Host smart-ece88897-cd3b-42a2-8d4e-b75699fb481d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487787136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3487787136
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1454328620
Short name T526
Test name
Test status
Simulation time 46164579173 ps
CPU time 27.15 seconds
Started Feb 04 01:05:21 PM PST 24
Finished Feb 04 01:05:52 PM PST 24
Peak memory 201424 kb
Host smart-96d74014-9dd0-4537-b611-7958076839a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454328620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1454328620
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3619932853
Short name T52
Test name
Test status
Simulation time 3279663442 ps
CPU time 4.43 seconds
Started Feb 04 01:05:24 PM PST 24
Finished Feb 04 01:05:30 PM PST 24
Peak memory 201244 kb
Host smart-e06f7add-3721-4cd8-9009-262a43eff7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619932853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3619932853
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2976306006
Short name T664
Test name
Test status
Simulation time 5921802666 ps
CPU time 15.35 seconds
Started Feb 04 01:05:24 PM PST 24
Finished Feb 04 01:05:41 PM PST 24
Peak memory 201300 kb
Host smart-41460aa0-645e-4b78-a91a-59e634400014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976306006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2976306006
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3550808343
Short name T761
Test name
Test status
Simulation time 253386990302 ps
CPU time 803.06 seconds
Started Feb 04 01:05:21 PM PST 24
Finished Feb 04 01:18:47 PM PST 24
Peak memory 211148 kb
Host smart-37983dcb-93ea-40c2-8a7b-8382d68d44e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550808343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3550808343
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3276930642
Short name T319
Test name
Test status
Simulation time 80912008521 ps
CPU time 99.48 seconds
Started Feb 04 01:05:22 PM PST 24
Finished Feb 04 01:07:04 PM PST 24
Peak memory 201864 kb
Host smart-0319432d-e04f-4a4c-a603-89b0ea8852b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276930642 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3276930642
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3364816001
Short name T766
Test name
Test status
Simulation time 340764530 ps
CPU time 0.88 seconds
Started Feb 04 01:05:22 PM PST 24
Finished Feb 04 01:05:26 PM PST 24
Peak memory 201240 kb
Host smart-efde78b1-eb80-4cd8-b4c4-671a6e61b3ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364816001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3364816001
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3872389365
Short name T336
Test name
Test status
Simulation time 165323288612 ps
CPU time 152.1 seconds
Started Feb 04 01:05:20 PM PST 24
Finished Feb 04 01:07:55 PM PST 24
Peak memory 201612 kb
Host smart-00ba4b02-9d0e-4d66-aa80-ff50634e9048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872389365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3872389365
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2718812423
Short name T670
Test name
Test status
Simulation time 347930145184 ps
CPU time 69.35 seconds
Started Feb 04 01:05:24 PM PST 24
Finished Feb 04 01:06:35 PM PST 24
Peak memory 201656 kb
Host smart-a04f6a7b-5cc5-429d-91d5-9590356f816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718812423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2718812423
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2159834844
Short name T475
Test name
Test status
Simulation time 328804432934 ps
CPU time 752.61 seconds
Started Feb 04 01:05:22 PM PST 24
Finished Feb 04 01:17:57 PM PST 24
Peak memory 201572 kb
Host smart-aa8f69c3-7f8b-4375-9456-3912ef71eaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159834844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2159834844
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3186330692
Short name T744
Test name
Test status
Simulation time 165523165476 ps
CPU time 400.35 seconds
Started Feb 04 01:05:19 PM PST 24
Finished Feb 04 01:12:01 PM PST 24
Peak memory 201540 kb
Host smart-cccdd021-ef52-4a7e-8142-943c95bf1b29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186330692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3186330692
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2905582090
Short name T799
Test name
Test status
Simulation time 489645297137 ps
CPU time 575.21 seconds
Started Feb 04 01:05:17 PM PST 24
Finished Feb 04 01:14:54 PM PST 24
Peak memory 201560 kb
Host smart-722d9dc5-b32d-4116-ba0a-081061be2d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905582090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2905582090
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3744207761
Short name T672
Test name
Test status
Simulation time 492655815999 ps
CPU time 602.58 seconds
Started Feb 04 01:05:22 PM PST 24
Finished Feb 04 01:15:27 PM PST 24
Peak memory 201624 kb
Host smart-37e443b2-81e4-4518-800e-3f591673ad72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744207761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3744207761
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2731541121
Short name T281
Test name
Test status
Simulation time 489290391932 ps
CPU time 273.77 seconds
Started Feb 04 01:05:21 PM PST 24
Finished Feb 04 01:09:58 PM PST 24
Peak memory 201664 kb
Host smart-be95b2e3-49c9-4078-ad5b-edddb655fb20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731541121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2731541121
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2770008783
Short name T619
Test name
Test status
Simulation time 487060368171 ps
CPU time 274.29 seconds
Started Feb 04 01:05:23 PM PST 24
Finished Feb 04 01:09:59 PM PST 24
Peak memory 201588 kb
Host smart-8a50e3bf-c97b-4b1e-8d7e-9d01fee4ffba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770008783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2770008783
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.885323823
Short name T737
Test name
Test status
Simulation time 75086932860 ps
CPU time 260.19 seconds
Started Feb 04 01:05:17 PM PST 24
Finished Feb 04 01:09:39 PM PST 24
Peak memory 201880 kb
Host smart-9871e5ad-b9ea-4a59-af05-de8ffc5db6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885323823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.885323823
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3642500724
Short name T776
Test name
Test status
Simulation time 33053678048 ps
CPU time 18.84 seconds
Started Feb 04 01:05:15 PM PST 24
Finished Feb 04 01:05:35 PM PST 24
Peak memory 201336 kb
Host smart-246bff31-15de-473a-87d5-f5b3890d1594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642500724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3642500724
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2557474446
Short name T606
Test name
Test status
Simulation time 5098177566 ps
CPU time 2.29 seconds
Started Feb 04 01:05:18 PM PST 24
Finished Feb 04 01:05:22 PM PST 24
Peak memory 201244 kb
Host smart-078694e5-0661-4bd2-92ee-503e53779f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557474446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2557474446
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.101884398
Short name T736
Test name
Test status
Simulation time 5593337414 ps
CPU time 3.72 seconds
Started Feb 04 01:05:23 PM PST 24
Finished Feb 04 01:05:29 PM PST 24
Peak memory 200932 kb
Host smart-2f3b78fd-75a9-43c6-ab6d-92ac31631daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101884398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.101884398
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1300234032
Short name T199
Test name
Test status
Simulation time 186299382095 ps
CPU time 826.02 seconds
Started Feb 04 01:05:21 PM PST 24
Finished Feb 04 01:19:11 PM PST 24
Peak memory 201932 kb
Host smart-395b78a6-6f8c-4df4-bbaf-c10f9751d0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300234032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1300234032
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3937328685
Short name T611
Test name
Test status
Simulation time 144122484484 ps
CPU time 88.39 seconds
Started Feb 04 01:05:21 PM PST 24
Finished Feb 04 01:06:53 PM PST 24
Peak memory 210372 kb
Host smart-e411f80b-7157-4acc-9496-e4ddfca9142a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937328685 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3937328685
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1455668403
Short name T836
Test name
Test status
Simulation time 447541133 ps
CPU time 1.49 seconds
Started Feb 04 01:05:31 PM PST 24
Finished Feb 04 01:05:39 PM PST 24
Peak memory 201312 kb
Host smart-ac7612f5-b79a-4a1d-9bb4-e89e168e4261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455668403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1455668403
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3307936365
Short name T283
Test name
Test status
Simulation time 324072969693 ps
CPU time 722.14 seconds
Started Feb 04 01:05:29 PM PST 24
Finished Feb 04 01:17:34 PM PST 24
Peak memory 201628 kb
Host smart-b3887fee-5abf-43ca-9387-8ea2c7d4daae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307936365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3307936365
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1281788854
Short name T126
Test name
Test status
Simulation time 167328158321 ps
CPU time 102.91 seconds
Started Feb 04 01:05:28 PM PST 24
Finished Feb 04 01:07:11 PM PST 24
Peak memory 201568 kb
Host smart-2910a86a-01a9-41d1-bd10-4e607207e56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281788854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1281788854
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.276861328
Short name T759
Test name
Test status
Simulation time 495178281798 ps
CPU time 295.96 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:10:42 PM PST 24
Peak memory 201556 kb
Host smart-8829abe7-179a-4bfd-b566-0fdd67526ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276861328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.276861328
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2965723505
Short name T180
Test name
Test status
Simulation time 159901417854 ps
CPU time 54.43 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:06:41 PM PST 24
Peak memory 201472 kb
Host smart-a1bfc7dd-4c36-4b34-a557-4aea545dc0c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965723505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2965723505
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.816939206
Short name T343
Test name
Test status
Simulation time 332114786841 ps
CPU time 803.76 seconds
Started Feb 04 01:05:20 PM PST 24
Finished Feb 04 01:18:47 PM PST 24
Peak memory 201612 kb
Host smart-8cb22ac7-28ab-4345-b8b3-516c63066bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816939206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.816939206
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.412740267
Short name T529
Test name
Test status
Simulation time 499643182248 ps
CPU time 1170.13 seconds
Started Feb 04 01:05:22 PM PST 24
Finished Feb 04 01:24:55 PM PST 24
Peak memory 201452 kb
Host smart-8577723b-126d-4609-a547-d60837b46327
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412740267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.412740267
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3175500771
Short name T244
Test name
Test status
Simulation time 336959200190 ps
CPU time 731.18 seconds
Started Feb 04 01:05:27 PM PST 24
Finished Feb 04 01:17:39 PM PST 24
Peak memory 201648 kb
Host smart-683edece-f4df-4bcb-b912-ddcb56b7c0d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175500771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3175500771
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2130053765
Short name T582
Test name
Test status
Simulation time 157318599183 ps
CPU time 104.75 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:07:30 PM PST 24
Peak memory 201532 kb
Host smart-08e0130a-48f3-4d8c-ac63-01545452a932
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130053765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2130053765
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2941083242
Short name T853
Test name
Test status
Simulation time 99394475845 ps
CPU time 596.61 seconds
Started Feb 04 01:05:29 PM PST 24
Finished Feb 04 01:15:30 PM PST 24
Peak memory 201948 kb
Host smart-01c42ff5-6329-404a-a72e-52ecd9152457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941083242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2941083242
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2433208588
Short name T688
Test name
Test status
Simulation time 34085470729 ps
CPU time 40.68 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:06:27 PM PST 24
Peak memory 201312 kb
Host smart-5298acf1-df58-402a-81c8-cd970c346680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433208588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2433208588
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2120551616
Short name T482
Test name
Test status
Simulation time 3955210322 ps
CPU time 9.46 seconds
Started Feb 04 01:05:29 PM PST 24
Finished Feb 04 01:05:41 PM PST 24
Peak memory 201456 kb
Host smart-189954ad-b082-40b0-a4fb-2eead47f4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120551616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2120551616
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4266297766
Short name T47
Test name
Test status
Simulation time 5672432318 ps
CPU time 14.34 seconds
Started Feb 04 01:05:25 PM PST 24
Finished Feb 04 01:05:41 PM PST 24
Peak memory 201408 kb
Host smart-5d091432-feeb-4eb7-a026-2c3b21214cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266297766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4266297766
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3817102447
Short name T565
Test name
Test status
Simulation time 168159548569 ps
CPU time 387.43 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:12:13 PM PST 24
Peak memory 201496 kb
Host smart-53cb7194-2372-4e30-ba93-0cae4aaae333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817102447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3817102447
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3430651113
Short name T295
Test name
Test status
Simulation time 221513896771 ps
CPU time 205.94 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:09:12 PM PST 24
Peak memory 210560 kb
Host smart-413d36af-dc87-4298-bc60-99534bd89c51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430651113 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3430651113
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1528096704
Short name T649
Test name
Test status
Simulation time 385167054 ps
CPU time 0.81 seconds
Started Feb 04 01:05:48 PM PST 24
Finished Feb 04 01:05:50 PM PST 24
Peak memory 201276 kb
Host smart-fb53918b-e8ef-492d-a387-a5061962bc0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528096704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1528096704
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3679392836
Short name T810
Test name
Test status
Simulation time 334812258157 ps
CPU time 431.38 seconds
Started Feb 04 01:05:32 PM PST 24
Finished Feb 04 01:12:49 PM PST 24
Peak memory 201616 kb
Host smart-63da9770-44ad-432a-9cda-a1a421de8ba8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679392836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3679392836
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4131609576
Short name T858
Test name
Test status
Simulation time 166341113746 ps
CPU time 102.92 seconds
Started Feb 04 01:05:46 PM PST 24
Finished Feb 04 01:07:30 PM PST 24
Peak memory 201588 kb
Host smart-e7cdefc1-93d4-4943-b23a-c3e474dc1b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131609576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4131609576
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2360606666
Short name T223
Test name
Test status
Simulation time 324481492280 ps
CPU time 743.62 seconds
Started Feb 04 01:05:28 PM PST 24
Finished Feb 04 01:17:52 PM PST 24
Peak memory 201560 kb
Host smart-03d62523-aeda-47bf-89b6-c1e0dd691479
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360606666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2360606666
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.281317211
Short name T178
Test name
Test status
Simulation time 327697225522 ps
CPU time 391.11 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:12:18 PM PST 24
Peak memory 201496 kb
Host smart-0fedbfbb-d7f1-465b-a2a8-573d9d823586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281317211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.281317211
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2733342920
Short name T671
Test name
Test status
Simulation time 164442092785 ps
CPU time 358.13 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:11:43 PM PST 24
Peak memory 201484 kb
Host smart-ca11fc13-0a5d-4c1a-89a5-b3e855f09076
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733342920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2733342920
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1804954482
Short name T312
Test name
Test status
Simulation time 333910235169 ps
CPU time 193.77 seconds
Started Feb 04 01:05:46 PM PST 24
Finished Feb 04 01:09:01 PM PST 24
Peak memory 201524 kb
Host smart-67a176d4-a4a8-4973-a318-df9541476244
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804954482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1804954482
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.912651866
Short name T446
Test name
Test status
Simulation time 325742613205 ps
CPU time 735.23 seconds
Started Feb 04 01:05:30 PM PST 24
Finished Feb 04 01:17:52 PM PST 24
Peak memory 201612 kb
Host smart-d99286fd-479b-4824-8cf0-359da26d9f41
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912651866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.912651866
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1492172699
Short name T597
Test name
Test status
Simulation time 88726252350 ps
CPU time 304.56 seconds
Started Feb 04 01:05:43 PM PST 24
Finished Feb 04 01:10:49 PM PST 24
Peak memory 201824 kb
Host smart-877d9f96-4711-4496-a230-ed494298f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492172699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1492172699
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1244093251
Short name T558
Test name
Test status
Simulation time 34748995547 ps
CPU time 8.98 seconds
Started Feb 04 01:05:42 PM PST 24
Finished Feb 04 01:05:53 PM PST 24
Peak memory 201428 kb
Host smart-cdac2627-16e5-40ea-b77d-bec5c1f6b8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244093251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1244093251
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1278112425
Short name T493
Test name
Test status
Simulation time 4543603836 ps
CPU time 10.06 seconds
Started Feb 04 01:05:42 PM PST 24
Finished Feb 04 01:05:54 PM PST 24
Peak memory 201372 kb
Host smart-0307e39f-4830-4380-8595-bd2d400a25f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278112425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1278112425
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3954476956
Short name T726
Test name
Test status
Simulation time 5523027994 ps
CPU time 12.43 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:05:59 PM PST 24
Peak memory 201256 kb
Host smart-c3b74439-5aba-4109-9002-de0eb2345767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954476956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3954476956
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3394487088
Short name T91
Test name
Test status
Simulation time 209166672616 ps
CPU time 317.48 seconds
Started Feb 04 01:05:42 PM PST 24
Finished Feb 04 01:11:02 PM PST 24
Peak memory 210312 kb
Host smart-2d9c99bd-c2ca-4956-abc1-b1332fdaea32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394487088 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3394487088
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.993648780
Short name T651
Test name
Test status
Simulation time 367583103 ps
CPU time 1.02 seconds
Started Feb 04 01:05:42 PM PST 24
Finished Feb 04 01:05:45 PM PST 24
Peak memory 201200 kb
Host smart-08dabe6a-e8c9-4a32-93b3-d163f073a817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993648780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.993648780
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3457526857
Short name T332
Test name
Test status
Simulation time 164120795038 ps
CPU time 387.65 seconds
Started Feb 04 01:05:50 PM PST 24
Finished Feb 04 01:12:18 PM PST 24
Peak memory 201680 kb
Host smart-7e1d4a4c-87f3-4bef-af3e-f54259ea593e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457526857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3457526857
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.850128114
Short name T50
Test name
Test status
Simulation time 166710584482 ps
CPU time 422.25 seconds
Started Feb 04 01:05:52 PM PST 24
Finished Feb 04 01:12:55 PM PST 24
Peak memory 201600 kb
Host smart-7974c2d6-0f71-402c-8d62-791445f8b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850128114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.850128114
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.28403468
Short name T176
Test name
Test status
Simulation time 329723505293 ps
CPU time 711.87 seconds
Started Feb 04 01:05:41 PM PST 24
Finished Feb 04 01:17:36 PM PST 24
Peak memory 201488 kb
Host smart-925f43b6-7ae6-4640-821e-2a4e82d9af37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=28403468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt
_fixed.28403468
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.848871609
Short name T349
Test name
Test status
Simulation time 487614520457 ps
CPU time 273.07 seconds
Started Feb 04 01:05:42 PM PST 24
Finished Feb 04 01:10:17 PM PST 24
Peak memory 201668 kb
Host smart-1269b2f0-dc18-4b83-8314-95f66ccce916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848871609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.848871609
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3248723612
Short name T604
Test name
Test status
Simulation time 161568311300 ps
CPU time 366.69 seconds
Started Feb 04 01:05:43 PM PST 24
Finished Feb 04 01:11:51 PM PST 24
Peak memory 201612 kb
Host smart-6730b1e9-6cf1-415e-8a2f-8bff0b78d931
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248723612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3248723612
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.812178758
Short name T587
Test name
Test status
Simulation time 166130410496 ps
CPU time 406.95 seconds
Started Feb 04 01:05:41 PM PST 24
Finished Feb 04 01:12:31 PM PST 24
Peak memory 201668 kb
Host smart-ef10f401-6221-44cc-b60b-3ad9185175c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812178758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.812178758
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3622153332
Short name T481
Test name
Test status
Simulation time 333795763376 ps
CPU time 846.28 seconds
Started Feb 04 01:05:41 PM PST 24
Finished Feb 04 01:19:51 PM PST 24
Peak memory 201612 kb
Host smart-1c5ab3e4-5865-4fcd-889d-5f821da9d619
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622153332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3622153332
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.783729210
Short name T15
Test name
Test status
Simulation time 127415331044 ps
CPU time 442.61 seconds
Started Feb 04 01:05:44 PM PST 24
Finished Feb 04 01:13:07 PM PST 24
Peak memory 201832 kb
Host smart-94129c0b-3261-4cfe-b1d3-f4959260868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783729210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.783729210
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.718474447
Short name T779
Test name
Test status
Simulation time 29513220623 ps
CPU time 31.08 seconds
Started Feb 04 01:05:44 PM PST 24
Finished Feb 04 01:06:16 PM PST 24
Peak memory 201316 kb
Host smart-d90b8151-08f9-42a9-bcb4-969c913f3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718474447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.718474447
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1803059906
Short name T554
Test name
Test status
Simulation time 4028398771 ps
CPU time 5.37 seconds
Started Feb 04 01:05:45 PM PST 24
Finished Feb 04 01:05:51 PM PST 24
Peak memory 201404 kb
Host smart-02dc6634-baa7-4265-b5e7-951fd78d50b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803059906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1803059906
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2159279343
Short name T574
Test name
Test status
Simulation time 5971261658 ps
CPU time 3.91 seconds
Started Feb 04 01:05:44 PM PST 24
Finished Feb 04 01:05:49 PM PST 24
Peak memory 201372 kb
Host smart-e0ce6902-14f2-406a-b7bd-52a0f180b4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159279343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2159279343
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1785969930
Short name T719
Test name
Test status
Simulation time 63931752909 ps
CPU time 132.33 seconds
Started Feb 04 01:05:43 PM PST 24
Finished Feb 04 01:07:57 PM PST 24
Peak memory 201372 kb
Host smart-0f463abd-8d1a-4b11-b291-4555764e2402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785969930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1785969930
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1926985240
Short name T27
Test name
Test status
Simulation time 421809331 ps
CPU time 1.06 seconds
Started Feb 04 01:06:08 PM PST 24
Finished Feb 04 01:06:18 PM PST 24
Peak memory 201128 kb
Host smart-3f403c38-b969-407c-a0b9-b2acffc9e8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926985240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1926985240
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3342969095
Short name T866
Test name
Test status
Simulation time 162353604042 ps
CPU time 397.19 seconds
Started Feb 04 01:06:04 PM PST 24
Finished Feb 04 01:12:44 PM PST 24
Peak memory 201672 kb
Host smart-b7dd10b6-a324-47b0-a46f-8a2f01a56283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342969095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3342969095
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.475301871
Short name T14
Test name
Test status
Simulation time 168378241783 ps
CPU time 97.67 seconds
Started Feb 04 01:06:05 PM PST 24
Finished Feb 04 01:07:50 PM PST 24
Peak memory 201652 kb
Host smart-6ec8286b-6130-4830-b559-e0a8384ca526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475301871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.475301871
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.599954918
Short name T697
Test name
Test status
Simulation time 485874180585 ps
CPU time 1186.24 seconds
Started Feb 04 01:06:12 PM PST 24
Finished Feb 04 01:26:03 PM PST 24
Peak memory 201672 kb
Host smart-d5afbc9c-a06b-4eda-a840-7c07e68ad2a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=599954918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.599954918
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3527007993
Short name T131
Test name
Test status
Simulation time 493512958125 ps
CPU time 68.57 seconds
Started Feb 04 01:06:09 PM PST 24
Finished Feb 04 01:07:25 PM PST 24
Peak memory 201600 kb
Host smart-e53f60d8-0082-429c-938c-2f0ee349c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527007993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3527007993
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1350194921
Short name T777
Test name
Test status
Simulation time 490337159400 ps
CPU time 346.26 seconds
Started Feb 04 01:06:13 PM PST 24
Finished Feb 04 01:12:04 PM PST 24
Peak memory 201552 kb
Host smart-9090a16f-0831-4cde-87c8-9902c467df6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350194921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1350194921
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2395982223
Short name T807
Test name
Test status
Simulation time 328964651108 ps
CPU time 210.25 seconds
Started Feb 04 01:06:16 PM PST 24
Finished Feb 04 01:09:49 PM PST 24
Peak memory 201600 kb
Host smart-13447a1b-f586-4361-b0bb-a3faa73cb0fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395982223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2395982223
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1262585876
Short name T461
Test name
Test status
Simulation time 158421292198 ps
CPU time 351.22 seconds
Started Feb 04 01:06:05 PM PST 24
Finished Feb 04 01:11:58 PM PST 24
Peak memory 201616 kb
Host smart-881dcc0a-b30b-4cdc-b07f-9a02e994acd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262585876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1262585876
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4282777936
Short name T164
Test name
Test status
Simulation time 109278989348 ps
CPU time 508.06 seconds
Started Feb 04 01:06:09 PM PST 24
Finished Feb 04 01:14:45 PM PST 24
Peak memory 201880 kb
Host smart-4e5cacbb-2ac4-4872-ac8b-30843b354119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282777936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4282777936
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.789311343
Short name T805
Test name
Test status
Simulation time 21928064114 ps
CPU time 29.76 seconds
Started Feb 04 01:06:06 PM PST 24
Finished Feb 04 01:06:44 PM PST 24
Peak memory 201404 kb
Host smart-28a0684c-bc71-40e8-8d66-e47667f358d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789311343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.789311343
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2755200671
Short name T598
Test name
Test status
Simulation time 4404451140 ps
CPU time 6.56 seconds
Started Feb 04 01:06:13 PM PST 24
Finished Feb 04 01:06:24 PM PST 24
Peak memory 201216 kb
Host smart-e1184b90-0ef7-46d1-abce-7ed3b10596c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755200671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2755200671
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.630396078
Short name T513
Test name
Test status
Simulation time 6090831695 ps
CPU time 4.24 seconds
Started Feb 04 01:06:05 PM PST 24
Finished Feb 04 01:06:11 PM PST 24
Peak memory 201368 kb
Host smart-75d6f83a-ba8b-4eab-aa18-0b3b75ac64d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630396078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.630396078
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3102721122
Short name T517
Test name
Test status
Simulation time 427656085819 ps
CPU time 486.52 seconds
Started Feb 04 01:06:17 PM PST 24
Finished Feb 04 01:14:26 PM PST 24
Peak memory 209984 kb
Host smart-721e923e-fd08-4bef-9e4b-d7487f735e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102721122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3102721122
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1689614487
Short name T803
Test name
Test status
Simulation time 52117723415 ps
CPU time 79.43 seconds
Started Feb 04 01:06:14 PM PST 24
Finished Feb 04 01:07:37 PM PST 24
Peak memory 210000 kb
Host smart-5b661e37-87d1-47c6-a986-81568cf39cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689614487 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1689614487
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2073266239
Short name T177
Test name
Test status
Simulation time 435251299 ps
CPU time 1.65 seconds
Started Feb 04 01:03:34 PM PST 24
Finished Feb 04 01:03:40 PM PST 24
Peak memory 201284 kb
Host smart-6606677d-14c3-4508-9bc1-f074cf67a83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073266239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2073266239
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2953899290
Short name T243
Test name
Test status
Simulation time 163829582870 ps
CPU time 69.46 seconds
Started Feb 04 01:03:51 PM PST 24
Finished Feb 04 01:05:02 PM PST 24
Peak memory 201568 kb
Host smart-45dd987d-f443-4f0d-b25b-20624652cc24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953899290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2953899290
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.612473786
Short name T106
Test name
Test status
Simulation time 331705652586 ps
CPU time 89.22 seconds
Started Feb 04 01:03:51 PM PST 24
Finished Feb 04 01:05:21 PM PST 24
Peak memory 201492 kb
Host smart-69625597-a12e-4ca1-bbef-6b6ff03ca07c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=612473786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.612473786
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.637381215
Short name T132
Test name
Test status
Simulation time 161901273084 ps
CPU time 77 seconds
Started Feb 04 01:03:15 PM PST 24
Finished Feb 04 01:04:34 PM PST 24
Peak memory 201644 kb
Host smart-c7d397de-c7af-4917-beb7-dac54f0f1d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637381215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.637381215
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3313536828
Short name T821
Test name
Test status
Simulation time 326998605967 ps
CPU time 193.1 seconds
Started Feb 04 01:03:53 PM PST 24
Finished Feb 04 01:07:07 PM PST 24
Peak memory 201556 kb
Host smart-5adc3938-0017-42ce-b5fb-16cd52039411
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313536828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3313536828
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3041649301
Short name T780
Test name
Test status
Simulation time 330727583738 ps
CPU time 760.13 seconds
Started Feb 04 01:03:35 PM PST 24
Finished Feb 04 01:16:24 PM PST 24
Peak memory 201580 kb
Host smart-1fb1d5ae-7cc5-407c-a4ba-78e661093d85
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041649301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3041649301
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3981739361
Short name T727
Test name
Test status
Simulation time 46084981201 ps
CPU time 113.04 seconds
Started Feb 04 01:03:34 PM PST 24
Finished Feb 04 01:05:30 PM PST 24
Peak memory 201352 kb
Host smart-f3840580-f1e1-4f5c-a710-1c34785191a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981739361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3981739361
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3143328052
Short name T152
Test name
Test status
Simulation time 5462676351 ps
CPU time 13.23 seconds
Started Feb 04 01:03:35 PM PST 24
Finished Feb 04 01:03:57 PM PST 24
Peak memory 201372 kb
Host smart-4416041e-eadb-4465-aed6-670a0f268ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143328052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3143328052
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3562467409
Short name T542
Test name
Test status
Simulation time 6090333392 ps
CPU time 3.26 seconds
Started Feb 04 01:03:13 PM PST 24
Finished Feb 04 01:03:18 PM PST 24
Peak memory 201396 kb
Host smart-0a112edb-58ae-4cdc-af28-99f82a8f7501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562467409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3562467409
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2578561685
Short name T851
Test name
Test status
Simulation time 80718368325 ps
CPU time 154.78 seconds
Started Feb 04 01:03:31 PM PST 24
Finished Feb 04 01:06:10 PM PST 24
Peak memory 217740 kb
Host smart-74560f90-a2c0-41c6-b588-9062c768d11a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578561685 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2578561685
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1232425500
Short name T818
Test name
Test status
Simulation time 493659253 ps
CPU time 1.63 seconds
Started Feb 04 01:06:10 PM PST 24
Finished Feb 04 01:06:18 PM PST 24
Peak memory 201200 kb
Host smart-b93d4d2b-c10b-4581-9e01-72358683c7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232425500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1232425500
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1949601213
Short name T317
Test name
Test status
Simulation time 163143825306 ps
CPU time 185.98 seconds
Started Feb 04 01:06:19 PM PST 24
Finished Feb 04 01:09:26 PM PST 24
Peak memory 201612 kb
Host smart-78523eb3-f375-449b-90f1-10f31b04c672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949601213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1949601213
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.56334155
Short name T358
Test name
Test status
Simulation time 331095807865 ps
CPU time 216.47 seconds
Started Feb 04 01:06:08 PM PST 24
Finished Feb 04 01:09:53 PM PST 24
Peak memory 201504 kb
Host smart-50365f6b-9e1b-40f2-91c2-085c9dd67db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56334155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.56334155
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1889781195
Short name T471
Test name
Test status
Simulation time 504566790276 ps
CPU time 302.43 seconds
Started Feb 04 01:06:27 PM PST 24
Finished Feb 04 01:11:30 PM PST 24
Peak memory 201552 kb
Host smart-690653a5-174d-4fbb-9e15-f0b074079d6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889781195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1889781195
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.51032803
Short name T839
Test name
Test status
Simulation time 165314812391 ps
CPU time 66.56 seconds
Started Feb 04 01:06:09 PM PST 24
Finished Feb 04 01:07:23 PM PST 24
Peak memory 201552 kb
Host smart-572c70ea-3728-4891-a8b8-29f7084bcdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51032803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.51032803
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1768060343
Short name T636
Test name
Test status
Simulation time 162715809837 ps
CPU time 96.5 seconds
Started Feb 04 01:06:09 PM PST 24
Finished Feb 04 01:07:53 PM PST 24
Peak memory 201516 kb
Host smart-dcf0eda7-409c-4a37-95fe-8a4ff724ef7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768060343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1768060343
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.81849163
Short name T845
Test name
Test status
Simulation time 498861632323 ps
CPU time 1183.21 seconds
Started Feb 04 01:06:10 PM PST 24
Finished Feb 04 01:26:00 PM PST 24
Peak memory 201580 kb
Host smart-d984def7-8d43-4f89-ab5e-7d1bc26e9e35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81849163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_w
akeup.81849163
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1134653527
Short name T709
Test name
Test status
Simulation time 167485018455 ps
CPU time 60.45 seconds
Started Feb 04 01:06:41 PM PST 24
Finished Feb 04 01:07:47 PM PST 24
Peak memory 201652 kb
Host smart-80d28580-aefe-4746-ba53-9c1830a91a57
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134653527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1134653527
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3131627655
Short name T859
Test name
Test status
Simulation time 92788663084 ps
CPU time 536.81 seconds
Started Feb 04 01:06:11 PM PST 24
Finished Feb 04 01:15:14 PM PST 24
Peak memory 201888 kb
Host smart-73ff53ff-0c9b-418a-8a81-bec47f2476dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131627655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3131627655
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.672169968
Short name T666
Test name
Test status
Simulation time 43707444801 ps
CPU time 22.78 seconds
Started Feb 04 01:06:11 PM PST 24
Finished Feb 04 01:06:40 PM PST 24
Peak memory 201308 kb
Host smart-cc091592-21ab-4d5e-be6b-709997db47ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672169968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.672169968
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.789330168
Short name T675
Test name
Test status
Simulation time 4996968394 ps
CPU time 6.77 seconds
Started Feb 04 01:06:23 PM PST 24
Finished Feb 04 01:06:31 PM PST 24
Peak memory 201332 kb
Host smart-2bb52895-208d-426d-a5d9-c77637a8a096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789330168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.789330168
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2531610854
Short name T578
Test name
Test status
Simulation time 6057499929 ps
CPU time 3.09 seconds
Started Feb 04 01:06:08 PM PST 24
Finished Feb 04 01:06:20 PM PST 24
Peak memory 201304 kb
Host smart-a19d0a04-b63b-4e5b-b9b8-fde2b5d3b69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531610854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2531610854
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.96269737
Short name T341
Test name
Test status
Simulation time 168856450752 ps
CPU time 94.33 seconds
Started Feb 04 01:06:13 PM PST 24
Finished Feb 04 01:07:52 PM PST 24
Peak memory 201588 kb
Host smart-07992674-4abf-4358-8628-130dec0c1e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96269737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.96269737
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3135789073
Short name T698
Test name
Test status
Simulation time 245277255225 ps
CPU time 202.78 seconds
Started Feb 04 01:06:19 PM PST 24
Finished Feb 04 01:09:43 PM PST 24
Peak memory 217440 kb
Host smart-7d725a6a-4737-4cbb-bc13-112039168b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135789073 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3135789073
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2949213385
Short name T436
Test name
Test status
Simulation time 386455336 ps
CPU time 1.55 seconds
Started Feb 04 01:06:12 PM PST 24
Finished Feb 04 01:06:18 PM PST 24
Peak memory 201260 kb
Host smart-a20bfe0a-d3dd-4330-8cf3-ce457d00fa50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949213385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2949213385
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3731519163
Short name T316
Test name
Test status
Simulation time 327334396664 ps
CPU time 93.44 seconds
Started Feb 04 01:06:12 PM PST 24
Finished Feb 04 01:07:50 PM PST 24
Peak memory 201588 kb
Host smart-e672915b-0e00-486b-af48-7501188bd9ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731519163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3731519163
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3926466710
Short name T279
Test name
Test status
Simulation time 325308778587 ps
CPU time 761.25 seconds
Started Feb 04 01:06:12 PM PST 24
Finished Feb 04 01:18:58 PM PST 24
Peak memory 201588 kb
Host smart-d77c3aa3-5aec-4f92-acfd-6797ca482164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926466710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3926466710
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1117416519
Short name T225
Test name
Test status
Simulation time 488906531410 ps
CPU time 1106.66 seconds
Started Feb 04 01:06:17 PM PST 24
Finished Feb 04 01:24:46 PM PST 24
Peak memory 201596 kb
Host smart-61031640-e349-44d6-bd49-23a854008ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117416519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1117416519
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3449565247
Short name T104
Test name
Test status
Simulation time 335293766405 ps
CPU time 695.69 seconds
Started Feb 04 01:06:13 PM PST 24
Finished Feb 04 01:17:53 PM PST 24
Peak memory 201456 kb
Host smart-2120f68d-6f42-4df3-b4f3-474d14e15075
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449565247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3449565247
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3596469743
Short name T119
Test name
Test status
Simulation time 327745808449 ps
CPU time 182.34 seconds
Started Feb 04 01:06:09 PM PST 24
Finished Feb 04 01:09:19 PM PST 24
Peak memory 201564 kb
Host smart-92adbdab-e6a0-46b0-b0b3-2a7d8c899386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596469743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3596469743
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3767321380
Short name T156
Test name
Test status
Simulation time 334600331694 ps
CPU time 372.53 seconds
Started Feb 04 01:06:12 PM PST 24
Finished Feb 04 01:12:29 PM PST 24
Peak memory 201444 kb
Host smart-27696ba9-c83f-414f-8c8e-6d018e7832e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767321380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3767321380
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3736427747
Short name T221
Test name
Test status
Simulation time 161878579274 ps
CPU time 205.94 seconds
Started Feb 04 01:06:09 PM PST 24
Finished Feb 04 01:09:43 PM PST 24
Peak memory 201616 kb
Host smart-f51eb264-1779-4085-bbad-4e01b263d864
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736427747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3736427747
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2590585173
Short name T712
Test name
Test status
Simulation time 162339836857 ps
CPU time 355.92 seconds
Started Feb 04 01:06:07 PM PST 24
Finished Feb 04 01:12:11 PM PST 24
Peak memory 201628 kb
Host smart-3cbb061b-2a96-4ab0-86a4-0a90a044b6a9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590585173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2590585173
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1240810902
Short name T212
Test name
Test status
Simulation time 106053121428 ps
CPU time 376.88 seconds
Started Feb 04 01:06:12 PM PST 24
Finished Feb 04 01:12:34 PM PST 24
Peak memory 201780 kb
Host smart-a440a6d6-9eca-4295-970e-5235a346d6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240810902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1240810902
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2259574776
Short name T163
Test name
Test status
Simulation time 37216168369 ps
CPU time 20.01 seconds
Started Feb 04 01:06:08 PM PST 24
Finished Feb 04 01:06:37 PM PST 24
Peak memory 201320 kb
Host smart-27336bf9-4016-4fca-8f2d-bb1e706bc73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259574776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2259574776
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3991969866
Short name T141
Test name
Test status
Simulation time 4163356690 ps
CPU time 10.13 seconds
Started Feb 04 01:06:12 PM PST 24
Finished Feb 04 01:06:27 PM PST 24
Peak memory 201408 kb
Host smart-45720de7-0049-4600-ad64-2b7f5f149d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991969866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3991969866
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2015514824
Short name T689
Test name
Test status
Simulation time 5765832143 ps
CPU time 14.57 seconds
Started Feb 04 01:06:09 PM PST 24
Finished Feb 04 01:06:31 PM PST 24
Peak memory 201352 kb
Host smart-d0c09710-13bd-4d96-8846-dbd5c258f282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015514824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2015514824
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2224564121
Short name T501
Test name
Test status
Simulation time 35350714105 ps
CPU time 76.78 seconds
Started Feb 04 01:06:05 PM PST 24
Finished Feb 04 01:07:24 PM PST 24
Peak memory 201424 kb
Host smart-b563db1d-bc74-4c6a-9b1a-f3a6691a3c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224564121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2224564121
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.56359233
Short name T656
Test name
Test status
Simulation time 366245401 ps
CPU time 1.4 seconds
Started Feb 04 01:06:21 PM PST 24
Finished Feb 04 01:06:23 PM PST 24
Peak memory 201296 kb
Host smart-5d8a0129-37f9-450e-bae2-2ee387ad5c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56359233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.56359233
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.686577121
Short name T125
Test name
Test status
Simulation time 490028015299 ps
CPU time 514.34 seconds
Started Feb 04 01:06:07 PM PST 24
Finished Feb 04 01:14:50 PM PST 24
Peak memory 201600 kb
Host smart-d85cc057-2e93-4194-8ef9-7327d0d9792b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686577121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.686577121
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.712322858
Short name T273
Test name
Test status
Simulation time 491563459802 ps
CPU time 1179.07 seconds
Started Feb 04 01:06:16 PM PST 24
Finished Feb 04 01:25:58 PM PST 24
Peak memory 201540 kb
Host smart-f77d7a3a-3395-4a4f-a4d9-cee9e5c16576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712322858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.712322858
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1482111515
Short name T566
Test name
Test status
Simulation time 165873536229 ps
CPU time 398.69 seconds
Started Feb 04 01:06:23 PM PST 24
Finished Feb 04 01:13:03 PM PST 24
Peak memory 201480 kb
Host smart-be3c526b-5cc6-4f18-be6e-435dea6482be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482111515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1482111515
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1014444820
Short name T543
Test name
Test status
Simulation time 504146664354 ps
CPU time 326.54 seconds
Started Feb 04 01:06:05 PM PST 24
Finished Feb 04 01:11:41 PM PST 24
Peak memory 201576 kb
Host smart-9d9167eb-dd9a-403d-b94e-a45c0ad5f463
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014444820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1014444820
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.649007596
Short name T862
Test name
Test status
Simulation time 326772175912 ps
CPU time 176.94 seconds
Started Feb 04 01:06:17 PM PST 24
Finished Feb 04 01:09:16 PM PST 24
Peak memory 201500 kb
Host smart-86d7a775-f32a-433a-92d5-66a38c3d1b1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649007596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.649007596
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.287868758
Short name T560
Test name
Test status
Simulation time 493661128837 ps
CPU time 966.42 seconds
Started Feb 04 01:06:11 PM PST 24
Finished Feb 04 01:22:23 PM PST 24
Peak memory 201668 kb
Host smart-0f45dfb9-5989-488f-900b-2f5738532f59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287868758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.287868758
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.808079217
Short name T771
Test name
Test status
Simulation time 125794999860 ps
CPU time 516.1 seconds
Started Feb 04 01:06:07 PM PST 24
Finished Feb 04 01:14:52 PM PST 24
Peak memory 201920 kb
Host smart-8d7aca92-6d05-429b-92f6-2bfd3978d4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808079217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.808079217
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2977279076
Short name T806
Test name
Test status
Simulation time 22657735386 ps
CPU time 55.49 seconds
Started Feb 04 01:06:12 PM PST 24
Finished Feb 04 01:07:12 PM PST 24
Peak memory 201428 kb
Host smart-4378a151-d457-4c0b-8632-9dc8baf52f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977279076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2977279076
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1378354092
Short name T506
Test name
Test status
Simulation time 2626373914 ps
CPU time 7.41 seconds
Started Feb 04 01:06:08 PM PST 24
Finished Feb 04 01:06:24 PM PST 24
Peak memory 201376 kb
Host smart-214f9bb1-397e-4495-afb9-874ec4635f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378354092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1378354092
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1385234387
Short name T459
Test name
Test status
Simulation time 5924006379 ps
CPU time 14.74 seconds
Started Feb 04 01:06:23 PM PST 24
Finished Feb 04 01:06:39 PM PST 24
Peak memory 201288 kb
Host smart-aa12a783-9737-4f69-9354-82b10c3dc2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385234387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1385234387
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2210826737
Short name T581
Test name
Test status
Simulation time 45671165636 ps
CPU time 28.3 seconds
Started Feb 04 01:06:07 PM PST 24
Finished Feb 04 01:06:44 PM PST 24
Peak memory 201296 kb
Host smart-468d4ae1-8fb9-4415-a96d-f4fe42c7685c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210826737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2210826737
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.976753395
Short name T621
Test name
Test status
Simulation time 71247553086 ps
CPU time 153.49 seconds
Started Feb 04 01:06:16 PM PST 24
Finished Feb 04 01:08:52 PM PST 24
Peak memory 210012 kb
Host smart-a790fbef-15be-4d09-82e6-ea7d6ca95b34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976753395 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.976753395
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.848741219
Short name T832
Test name
Test status
Simulation time 406351229 ps
CPU time 1.48 seconds
Started Feb 04 01:06:24 PM PST 24
Finished Feb 04 01:06:27 PM PST 24
Peak memory 201196 kb
Host smart-c579b66f-1b4e-4dd0-8ef6-0585548d9091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848741219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.848741219
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.385076716
Short name T354
Test name
Test status
Simulation time 485099575875 ps
CPU time 488.68 seconds
Started Feb 04 01:06:27 PM PST 24
Finished Feb 04 01:14:36 PM PST 24
Peak memory 201496 kb
Host smart-7617babe-60ba-42b2-af4c-c6a152a5fd18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385076716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.385076716
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.456535310
Short name T302
Test name
Test status
Simulation time 322098560038 ps
CPU time 215.22 seconds
Started Feb 04 01:06:27 PM PST 24
Finished Feb 04 01:10:03 PM PST 24
Peak memory 201604 kb
Host smart-4ef429b1-494f-416f-bd7b-c474aed0fe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456535310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.456535310
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4145056217
Short name T356
Test name
Test status
Simulation time 335595340958 ps
CPU time 226.54 seconds
Started Feb 04 01:06:28 PM PST 24
Finished Feb 04 01:10:15 PM PST 24
Peak memory 201708 kb
Host smart-71ba14c6-9a35-4894-8440-633b5409527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145056217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4145056217
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3523247969
Short name T856
Test name
Test status
Simulation time 490970460127 ps
CPU time 278.24 seconds
Started Feb 04 01:06:26 PM PST 24
Finished Feb 04 01:11:05 PM PST 24
Peak memory 201568 kb
Host smart-476c1fc3-ac8c-40f7-a6f4-e98e0cf7ae0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523247969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3523247969
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.945052248
Short name T184
Test name
Test status
Simulation time 320183007288 ps
CPU time 196.9 seconds
Started Feb 04 01:06:30 PM PST 24
Finished Feb 04 01:09:48 PM PST 24
Peak memory 201596 kb
Host smart-3d7fe824-6d56-4f70-9aaa-d895de020929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945052248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.945052248
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.965350970
Short name T751
Test name
Test status
Simulation time 161942934326 ps
CPU time 383.08 seconds
Started Feb 04 01:06:25 PM PST 24
Finished Feb 04 01:12:49 PM PST 24
Peak memory 201668 kb
Host smart-d2a83f2f-463b-4b10-a567-d01b4885c6a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=965350970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.965350970
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4209297648
Short name T564
Test name
Test status
Simulation time 163509643055 ps
CPU time 94 seconds
Started Feb 04 01:06:28 PM PST 24
Finished Feb 04 01:08:03 PM PST 24
Peak memory 201676 kb
Host smart-339b3332-5bca-430b-8321-c9365011c558
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209297648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4209297648
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.580351300
Short name T735
Test name
Test status
Simulation time 166547430865 ps
CPU time 362.84 seconds
Started Feb 04 01:06:25 PM PST 24
Finished Feb 04 01:12:28 PM PST 24
Peak memory 201556 kb
Host smart-7e3aabee-c268-4db1-92f3-d3e5a6cf19d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580351300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.580351300
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3627236655
Short name T648
Test name
Test status
Simulation time 92984875256 ps
CPU time 270.32 seconds
Started Feb 04 01:06:28 PM PST 24
Finished Feb 04 01:10:59 PM PST 24
Peak memory 201788 kb
Host smart-64277608-bed0-4f31-8ecf-0d2f665d8ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627236655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3627236655
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3920088182
Short name T120
Test name
Test status
Simulation time 25555433180 ps
CPU time 57.77 seconds
Started Feb 04 01:06:25 PM PST 24
Finished Feb 04 01:07:24 PM PST 24
Peak memory 201460 kb
Host smart-86cf8377-89ab-49f7-874a-11b6fed93846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920088182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3920088182
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1567160718
Short name T817
Test name
Test status
Simulation time 3907041556 ps
CPU time 1.47 seconds
Started Feb 04 01:06:28 PM PST 24
Finished Feb 04 01:06:30 PM PST 24
Peak memory 201332 kb
Host smart-f01b95ad-b35e-4193-a6ea-c9242ed32868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567160718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1567160718
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1920351691
Short name T172
Test name
Test status
Simulation time 5995111590 ps
CPU time 7.82 seconds
Started Feb 04 01:06:11 PM PST 24
Finished Feb 04 01:06:25 PM PST 24
Peak memory 201368 kb
Host smart-2ad8fa92-bf4c-4193-b531-d2d618817b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920351691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1920351691
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.599367111
Short name T534
Test name
Test status
Simulation time 244760074531 ps
CPU time 36.6 seconds
Started Feb 04 01:06:30 PM PST 24
Finished Feb 04 01:07:07 PM PST 24
Peak memory 201640 kb
Host smart-68b12aae-41f9-4d7a-8ec7-b8637f0bb601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599367111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
599367111
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2024990824
Short name T722
Test name
Test status
Simulation time 506469998 ps
CPU time 1.73 seconds
Started Feb 04 01:06:42 PM PST 24
Finished Feb 04 01:06:48 PM PST 24
Peak memory 201240 kb
Host smart-eb34dc0b-f389-44be-967c-b7974a0dfb61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024990824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2024990824
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1878025236
Short name T327
Test name
Test status
Simulation time 336815400790 ps
CPU time 80.58 seconds
Started Feb 04 01:06:50 PM PST 24
Finished Feb 04 01:08:12 PM PST 24
Peak memory 201648 kb
Host smart-89a30a80-1630-4a06-a6b5-206a4fd464cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878025236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1878025236
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.415242806
Short name T268
Test name
Test status
Simulation time 494192372102 ps
CPU time 287.67 seconds
Started Feb 04 01:06:39 PM PST 24
Finished Feb 04 01:11:34 PM PST 24
Peak memory 201632 kb
Host smart-4cf60140-91e8-47da-bd5f-9751dc174245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415242806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.415242806
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2712207042
Short name T788
Test name
Test status
Simulation time 323832309415 ps
CPU time 676.86 seconds
Started Feb 04 01:06:39 PM PST 24
Finished Feb 04 01:18:04 PM PST 24
Peak memory 201540 kb
Host smart-19c5ad0b-7fc1-4cb7-9a5b-eddf9ff41634
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712207042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2712207042
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.753171501
Short name T360
Test name
Test status
Simulation time 173834646197 ps
CPU time 144.38 seconds
Started Feb 04 01:06:42 PM PST 24
Finished Feb 04 01:09:11 PM PST 24
Peak memory 201496 kb
Host smart-d332fb97-c756-4d19-a1dc-dc637bbb7d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753171501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.753171501
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1584828741
Short name T107
Test name
Test status
Simulation time 334765143010 ps
CPU time 86.82 seconds
Started Feb 04 01:06:42 PM PST 24
Finished Feb 04 01:08:13 PM PST 24
Peak memory 201344 kb
Host smart-9dd3947d-7493-4e4f-8006-0582c5e00fd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584828741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1584828741
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2307676129
Short name T303
Test name
Test status
Simulation time 324904117858 ps
CPU time 706.97 seconds
Started Feb 04 01:06:40 PM PST 24
Finished Feb 04 01:18:34 PM PST 24
Peak memory 201596 kb
Host smart-93a67797-39e7-4122-9fec-ca0b542aadbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307676129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2307676129
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3326166784
Short name T456
Test name
Test status
Simulation time 488227082867 ps
CPU time 282.14 seconds
Started Feb 04 01:06:42 PM PST 24
Finished Feb 04 01:11:29 PM PST 24
Peak memory 201568 kb
Host smart-37e37fd8-eb9d-45b7-a007-116ca6a59572
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326166784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3326166784
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3407266273
Short name T603
Test name
Test status
Simulation time 105601729240 ps
CPU time 423.01 seconds
Started Feb 04 01:06:42 PM PST 24
Finished Feb 04 01:13:50 PM PST 24
Peak memory 201720 kb
Host smart-79a46193-30e8-4065-afd0-81f79aa02071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407266273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3407266273
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1970726592
Short name T760
Test name
Test status
Simulation time 38181732635 ps
CPU time 82.85 seconds
Started Feb 04 01:06:40 PM PST 24
Finished Feb 04 01:08:09 PM PST 24
Peak memory 201404 kb
Host smart-a780fd87-f555-460b-a46e-a371c97b2f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970726592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1970726592
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1063118834
Short name T850
Test name
Test status
Simulation time 4895542975 ps
CPU time 6.44 seconds
Started Feb 04 01:06:45 PM PST 24
Finished Feb 04 01:06:56 PM PST 24
Peak memory 201400 kb
Host smart-db5225a4-0660-4bc1-b075-2d1eb831bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063118834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1063118834
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3959072318
Short name T707
Test name
Test status
Simulation time 5837749636 ps
CPU time 4.69 seconds
Started Feb 04 01:06:28 PM PST 24
Finished Feb 04 01:06:34 PM PST 24
Peak memory 201352 kb
Host smart-7bdc2646-d938-4e8f-b230-e250012c1913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959072318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3959072318
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.431724507
Short name T683
Test name
Test status
Simulation time 329119546238 ps
CPU time 723.92 seconds
Started Feb 04 01:06:40 PM PST 24
Finished Feb 04 01:18:51 PM PST 24
Peak memory 201508 kb
Host smart-c0284c52-7ec8-489d-bf4d-7f642d1f77dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431724507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
431724507
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.774641064
Short name T222
Test name
Test status
Simulation time 180326751207 ps
CPU time 73.94 seconds
Started Feb 04 01:06:45 PM PST 24
Finished Feb 04 01:08:03 PM PST 24
Peak memory 210060 kb
Host smart-d71a7729-f5ec-4d02-a2bb-151dfbb2efc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774641064 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.774641064
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.4110057425
Short name T701
Test name
Test status
Simulation time 385916892 ps
CPU time 1.14 seconds
Started Feb 04 01:06:44 PM PST 24
Finished Feb 04 01:06:48 PM PST 24
Peak memory 201284 kb
Host smart-548cd376-6ba1-44eb-8e12-74473ea4fc39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110057425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.4110057425
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.45910865
Short name T228
Test name
Test status
Simulation time 488443696699 ps
CPU time 549.97 seconds
Started Feb 04 01:06:43 PM PST 24
Finished Feb 04 01:15:57 PM PST 24
Peak memory 201536 kb
Host smart-c05375b8-9a39-49a2-a224-404cc921cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45910865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.45910865
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2359039169
Short name T331
Test name
Test status
Simulation time 498662917977 ps
CPU time 301.9 seconds
Started Feb 04 01:06:39 PM PST 24
Finished Feb 04 01:11:49 PM PST 24
Peak memory 201652 kb
Host smart-462fd44d-9c59-469d-933a-494f3fcd30d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359039169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2359039169
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1382438775
Short name T730
Test name
Test status
Simulation time 164882325435 ps
CPU time 370.51 seconds
Started Feb 04 01:06:58 PM PST 24
Finished Feb 04 01:13:09 PM PST 24
Peak memory 201528 kb
Host smart-3c9af5c9-25fa-491f-995c-d197295167ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382438775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1382438775
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3345500823
Short name T108
Test name
Test status
Simulation time 164851270409 ps
CPU time 31.57 seconds
Started Feb 04 01:06:40 PM PST 24
Finished Feb 04 01:07:18 PM PST 24
Peak memory 201676 kb
Host smart-8d04a88a-0f9d-4771-87b4-5c110688e1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345500823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3345500823
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4014331277
Short name T867
Test name
Test status
Simulation time 158840774872 ps
CPU time 396.11 seconds
Started Feb 04 01:06:50 PM PST 24
Finished Feb 04 01:13:27 PM PST 24
Peak memory 201564 kb
Host smart-c3bad78f-d5ef-4ef0-8151-7091ac5d00c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014331277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4014331277
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.224826855
Short name T98
Test name
Test status
Simulation time 161522721654 ps
CPU time 158.43 seconds
Started Feb 04 01:06:39 PM PST 24
Finished Feb 04 01:09:25 PM PST 24
Peak memory 201608 kb
Host smart-23956d23-ec28-4789-841d-2564d0770854
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224826855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.224826855
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3230231700
Short name T588
Test name
Test status
Simulation time 159615610296 ps
CPU time 96.99 seconds
Started Feb 04 01:06:46 PM PST 24
Finished Feb 04 01:08:27 PM PST 24
Peak memory 201552 kb
Host smart-3d7f037a-695b-41c9-86ed-43697cd6adb0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230231700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3230231700
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.4044029644
Short name T204
Test name
Test status
Simulation time 109540669210 ps
CPU time 369.07 seconds
Started Feb 04 01:06:40 PM PST 24
Finished Feb 04 01:12:56 PM PST 24
Peak memory 201916 kb
Host smart-868eaf36-29cf-4e64-a0c6-aad501de1cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044029644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.4044029644
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2611633973
Short name T484
Test name
Test status
Simulation time 37414678825 ps
CPU time 12.25 seconds
Started Feb 04 01:06:45 PM PST 24
Finished Feb 04 01:07:02 PM PST 24
Peak memory 201420 kb
Host smart-e646dbae-ce75-4f65-911c-335929954e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611633973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2611633973
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2093139184
Short name T490
Test name
Test status
Simulation time 4485420851 ps
CPU time 5.92 seconds
Started Feb 04 01:06:41 PM PST 24
Finished Feb 04 01:06:53 PM PST 24
Peak memory 201388 kb
Host smart-1358cc79-ddb1-42db-8ec8-6c203d150eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093139184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2093139184
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3930007993
Short name T445
Test name
Test status
Simulation time 5869455737 ps
CPU time 4.26 seconds
Started Feb 04 01:06:41 PM PST 24
Finished Feb 04 01:06:51 PM PST 24
Peak memory 201232 kb
Host smart-cfc29003-754b-4ffc-88ca-f532b23699c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930007993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3930007993
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.627911477
Short name T296
Test name
Test status
Simulation time 26700681204 ps
CPU time 77.06 seconds
Started Feb 04 01:06:42 PM PST 24
Finished Feb 04 01:08:04 PM PST 24
Peak memory 210144 kb
Host smart-1776d524-f555-4312-91ef-f2cc75cbef20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627911477 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.627911477
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3013147995
Short name T154
Test name
Test status
Simulation time 402080730 ps
CPU time 1.55 seconds
Started Feb 04 01:06:50 PM PST 24
Finished Feb 04 01:06:53 PM PST 24
Peak memory 201256 kb
Host smart-8ec01f04-0f4a-438e-b09e-136fc2e2d477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013147995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3013147995
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2504557551
Short name T346
Test name
Test status
Simulation time 324729689132 ps
CPU time 753.63 seconds
Started Feb 04 01:06:55 PM PST 24
Finished Feb 04 01:19:30 PM PST 24
Peak memory 201592 kb
Host smart-84649aae-f2b3-4e5e-be14-c5e56e68b2ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504557551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2504557551
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2746297078
Short name T345
Test name
Test status
Simulation time 322867374154 ps
CPU time 230.64 seconds
Started Feb 04 01:06:57 PM PST 24
Finished Feb 04 01:10:48 PM PST 24
Peak memory 201508 kb
Host smart-29caf7ff-c60b-403f-b801-ec89833285f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746297078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2746297078
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2368084728
Short name T144
Test name
Test status
Simulation time 330996884676 ps
CPU time 366.77 seconds
Started Feb 04 01:06:51 PM PST 24
Finished Feb 04 01:12:59 PM PST 24
Peak memory 201656 kb
Host smart-e7b2a6ac-15ea-44f2-8753-b11a59b1f737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368084728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2368084728
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.919401297
Short name T829
Test name
Test status
Simulation time 495878525995 ps
CPU time 285.28 seconds
Started Feb 04 01:06:56 PM PST 24
Finished Feb 04 01:11:42 PM PST 24
Peak memory 201508 kb
Host smart-faac8512-587f-4960-8f50-ee52826e68be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=919401297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.919401297
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.694661365
Short name T563
Test name
Test status
Simulation time 163966871342 ps
CPU time 370.46 seconds
Started Feb 04 01:06:40 PM PST 24
Finished Feb 04 01:12:57 PM PST 24
Peak memory 201696 kb
Host smart-8492bdf4-35ad-453d-a094-91c02d9fdcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694661365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.694661365
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3412300363
Short name T756
Test name
Test status
Simulation time 487572231100 ps
CPU time 285.79 seconds
Started Feb 04 01:06:43 PM PST 24
Finished Feb 04 01:11:32 PM PST 24
Peak memory 201568 kb
Host smart-0da09697-7dc1-4957-9b31-68d3aaa31c68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412300363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3412300363
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1961264412
Short name T115
Test name
Test status
Simulation time 175857365821 ps
CPU time 47.47 seconds
Started Feb 04 01:06:57 PM PST 24
Finished Feb 04 01:07:46 PM PST 24
Peak memory 201564 kb
Host smart-cc14720e-ce57-4076-8d29-177d7deaebe0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961264412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1961264412
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1665314787
Short name T536
Test name
Test status
Simulation time 491336119267 ps
CPU time 1062.28 seconds
Started Feb 04 01:06:55 PM PST 24
Finished Feb 04 01:24:38 PM PST 24
Peak memory 201612 kb
Host smart-8032fde7-9a70-4d03-9521-c366e1a4c191
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665314787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1665314787
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.674847633
Short name T211
Test name
Test status
Simulation time 139358160315 ps
CPU time 407.15 seconds
Started Feb 04 01:06:59 PM PST 24
Finished Feb 04 01:13:48 PM PST 24
Peak memory 201900 kb
Host smart-edff0b8b-d752-4c38-8aff-2e407984dcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674847633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.674847633
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1753316338
Short name T795
Test name
Test status
Simulation time 31246542568 ps
CPU time 71.72 seconds
Started Feb 04 01:06:51 PM PST 24
Finished Feb 04 01:08:04 PM PST 24
Peak memory 201420 kb
Host smart-eb64a805-d5d0-47ee-9e99-511f538c09f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753316338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1753316338
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2069818156
Short name T808
Test name
Test status
Simulation time 3238108254 ps
CPU time 8.52 seconds
Started Feb 04 01:06:59 PM PST 24
Finished Feb 04 01:07:10 PM PST 24
Peak memory 201384 kb
Host smart-87e57f0c-391f-4d06-bdb7-178f39c872b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069818156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2069818156
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1130046387
Short name T655
Test name
Test status
Simulation time 6132714992 ps
CPU time 8.19 seconds
Started Feb 04 01:06:47 PM PST 24
Finished Feb 04 01:06:58 PM PST 24
Peak memory 201400 kb
Host smart-5d2ada9b-da8e-4bda-bc05-080931fbfa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130046387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1130046387
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3762015609
Short name T348
Test name
Test status
Simulation time 172280196147 ps
CPU time 403.65 seconds
Started Feb 04 01:07:01 PM PST 24
Finished Feb 04 01:13:46 PM PST 24
Peak memory 201588 kb
Host smart-1cb99271-6c23-4597-9c10-c0242c5ebe31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762015609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3762015609
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3954937286
Short name T285
Test name
Test status
Simulation time 342401601152 ps
CPU time 341.97 seconds
Started Feb 04 01:06:53 PM PST 24
Finished Feb 04 01:12:36 PM PST 24
Peak memory 218192 kb
Host smart-6d19b705-37bc-4578-92e0-6004b4ac46dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954937286 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3954937286
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2471746219
Short name T553
Test name
Test status
Simulation time 323226863 ps
CPU time 1.39 seconds
Started Feb 04 01:07:13 PM PST 24
Finished Feb 04 01:07:21 PM PST 24
Peak memory 201148 kb
Host smart-8092920f-b0d0-48a0-a35a-ef2b3dbc127e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471746219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2471746219
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.457298231
Short name T333
Test name
Test status
Simulation time 163139063968 ps
CPU time 81.43 seconds
Started Feb 04 01:06:52 PM PST 24
Finished Feb 04 01:08:15 PM PST 24
Peak memory 201532 kb
Host smart-71d22c60-968c-4704-9632-afc1cdfce2dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457298231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.457298231
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.851130275
Short name T669
Test name
Test status
Simulation time 565174431643 ps
CPU time 692.2 seconds
Started Feb 04 01:06:55 PM PST 24
Finished Feb 04 01:18:28 PM PST 24
Peak memory 201440 kb
Host smart-2cc27fcb-b8fb-4ec4-b474-199145c17d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851130275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.851130275
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.187465975
Short name T609
Test name
Test status
Simulation time 163013505622 ps
CPU time 111.55 seconds
Started Feb 04 01:06:54 PM PST 24
Finished Feb 04 01:08:46 PM PST 24
Peak memory 201564 kb
Host smart-ca1ab14e-56b1-4f8b-9f73-d9d81988429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187465975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.187465975
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4167737773
Short name T454
Test name
Test status
Simulation time 323143594971 ps
CPU time 741.57 seconds
Started Feb 04 01:06:57 PM PST 24
Finished Feb 04 01:19:19 PM PST 24
Peak memory 201504 kb
Host smart-b6a4e5a9-24cf-45f0-b79d-59b517ab4ec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167737773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.4167737773
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3845388674
Short name T157
Test name
Test status
Simulation time 327207144275 ps
CPU time 695.36 seconds
Started Feb 04 01:06:53 PM PST 24
Finished Feb 04 01:18:29 PM PST 24
Peak memory 201592 kb
Host smart-dca23dba-8ad4-4444-89af-146319125079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845388674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3845388674
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2887246100
Short name T168
Test name
Test status
Simulation time 333159498664 ps
CPU time 782.32 seconds
Started Feb 04 01:06:57 PM PST 24
Finished Feb 04 01:20:01 PM PST 24
Peak memory 201500 kb
Host smart-8d8d807e-3036-488f-be24-19437795d3d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887246100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2887246100
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3669572532
Short name T653
Test name
Test status
Simulation time 156368463520 ps
CPU time 67.55 seconds
Started Feb 04 01:06:55 PM PST 24
Finished Feb 04 01:08:04 PM PST 24
Peak memory 201588 kb
Host smart-6a27ffc9-a40c-491d-bc40-0ac3757cad2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669572532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3669572532
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2048749064
Short name T23
Test name
Test status
Simulation time 159677789375 ps
CPU time 346.44 seconds
Started Feb 04 01:06:59 PM PST 24
Finished Feb 04 01:12:48 PM PST 24
Peak memory 201560 kb
Host smart-d8d2c681-bcb8-4590-aaf3-dfd66b07ed73
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048749064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2048749064
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3386282745
Short name T764
Test name
Test status
Simulation time 113010786824 ps
CPU time 608.56 seconds
Started Feb 04 01:07:13 PM PST 24
Finished Feb 04 01:17:28 PM PST 24
Peak memory 201896 kb
Host smart-17920688-fe62-43c2-bab9-691e61d9109b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386282745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3386282745
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1335672778
Short name T448
Test name
Test status
Simulation time 31155849113 ps
CPU time 13.1 seconds
Started Feb 04 01:07:12 PM PST 24
Finished Feb 04 01:07:32 PM PST 24
Peak memory 201384 kb
Host smart-82a9267b-fb82-4c2f-a623-6a09cbbc573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335672778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1335672778
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1478420449
Short name T494
Test name
Test status
Simulation time 3919141668 ps
CPU time 3.03 seconds
Started Feb 04 01:07:17 PM PST 24
Finished Feb 04 01:07:28 PM PST 24
Peak memory 201328 kb
Host smart-8db6180a-e159-429f-8076-4f12a15be16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478420449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1478420449
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2179164987
Short name T95
Test name
Test status
Simulation time 5893999343 ps
CPU time 15.14 seconds
Started Feb 04 01:06:57 PM PST 24
Finished Feb 04 01:07:14 PM PST 24
Peak memory 201324 kb
Host smart-1eb7a6ee-4707-4caa-86b5-598f368ef8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179164987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2179164987
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.248207688
Short name T763
Test name
Test status
Simulation time 233713703422 ps
CPU time 758.31 seconds
Started Feb 04 01:07:16 PM PST 24
Finished Feb 04 01:20:04 PM PST 24
Peak memory 210156 kb
Host smart-f7b214aa-52e9-4fd5-a389-eafcce677dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248207688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
248207688
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1108755014
Short name T775
Test name
Test status
Simulation time 165723617872 ps
CPU time 58.77 seconds
Started Feb 04 01:07:11 PM PST 24
Finished Feb 04 01:08:16 PM PST 24
Peak memory 210036 kb
Host smart-59b4e4b0-83da-4fcd-b589-286667ca5f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108755014 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1108755014
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.233407210
Short name T40
Test name
Test status
Simulation time 577834473 ps
CPU time 0.71 seconds
Started Feb 04 01:07:29 PM PST 24
Finished Feb 04 01:07:33 PM PST 24
Peak memory 201216 kb
Host smart-456843f5-ef53-491a-b006-dba9e9da33e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233407210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.233407210
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.126423162
Short name T288
Test name
Test status
Simulation time 334037618367 ps
CPU time 688.45 seconds
Started Feb 04 01:07:13 PM PST 24
Finished Feb 04 01:18:49 PM PST 24
Peak memory 201696 kb
Host smart-d27ef6b4-19e0-4d6d-8490-4416fb4cc598
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126423162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.126423162
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.83243276
Short name T685
Test name
Test status
Simulation time 163876898250 ps
CPU time 78.84 seconds
Started Feb 04 01:07:16 PM PST 24
Finished Feb 04 01:08:44 PM PST 24
Peak memory 201568 kb
Host smart-1e46e7bb-9418-4c7c-b9ff-92a1d527b150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83243276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.83243276
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1462252916
Short name T254
Test name
Test status
Simulation time 330814860018 ps
CPU time 719.07 seconds
Started Feb 04 01:07:13 PM PST 24
Finished Feb 04 01:19:19 PM PST 24
Peak memory 201500 kb
Host smart-40786faa-75e4-4f51-88aa-6ab2f4d6272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462252916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1462252916
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.4113281254
Short name T686
Test name
Test status
Simulation time 496492417000 ps
CPU time 307.68 seconds
Started Feb 04 01:07:11 PM PST 24
Finished Feb 04 01:12:26 PM PST 24
Peak memory 201564 kb
Host smart-9ab6db4c-a7fc-463d-ab50-a0e261908990
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113281254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.4113281254
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.503201718
Short name T231
Test name
Test status
Simulation time 494716741861 ps
CPU time 1046.18 seconds
Started Feb 04 01:07:11 PM PST 24
Finished Feb 04 01:24:45 PM PST 24
Peak memory 201564 kb
Host smart-abdcea06-5c14-4c22-9ff1-ef4369755259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503201718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.503201718
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1090539205
Short name T429
Test name
Test status
Simulation time 166400549879 ps
CPU time 331.89 seconds
Started Feb 04 01:07:12 PM PST 24
Finished Feb 04 01:12:51 PM PST 24
Peak memory 201640 kb
Host smart-f9f01eb0-6da7-4546-a9e9-95801f6a0e27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090539205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1090539205
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3092767311
Short name T754
Test name
Test status
Simulation time 497297100340 ps
CPU time 550.64 seconds
Started Feb 04 01:07:15 PM PST 24
Finished Feb 04 01:16:31 PM PST 24
Peak memory 201472 kb
Host smart-da27ef2e-a262-427d-b43f-be81c1a4d22a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092767311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3092767311
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3275359756
Short name T173
Test name
Test status
Simulation time 95307452349 ps
CPU time 538.1 seconds
Started Feb 04 01:07:22 PM PST 24
Finished Feb 04 01:16:30 PM PST 24
Peak memory 201864 kb
Host smart-04dc5757-bb41-4284-8e15-3b8d47aee80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275359756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3275359756
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2471330913
Short name T460
Test name
Test status
Simulation time 23346913830 ps
CPU time 12.81 seconds
Started Feb 04 01:07:22 PM PST 24
Finished Feb 04 01:07:44 PM PST 24
Peak memory 201328 kb
Host smart-5fb25433-070a-46ea-a36f-dfd88452e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471330913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2471330913
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1100483805
Short name T814
Test name
Test status
Simulation time 5490615120 ps
CPU time 8.23 seconds
Started Feb 04 01:07:13 PM PST 24
Finished Feb 04 01:07:28 PM PST 24
Peak memory 201416 kb
Host smart-d7c276f9-eb2c-40ac-9600-b32ca76ffd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100483805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1100483805
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1698721956
Short name T541
Test name
Test status
Simulation time 5640740227 ps
CPU time 13.62 seconds
Started Feb 04 01:07:15 PM PST 24
Finished Feb 04 01:07:34 PM PST 24
Peak memory 201360 kb
Host smart-3ef96a60-9b3a-4f7b-9ad6-7a377a353d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698721956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1698721956
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.487827433
Short name T130
Test name
Test status
Simulation time 167748879173 ps
CPU time 96.51 seconds
Started Feb 04 01:07:37 PM PST 24
Finished Feb 04 01:09:14 PM PST 24
Peak memory 201520 kb
Host smart-fc9ec1fd-c54d-4500-8814-3ebdf313a957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487827433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
487827433
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.579996427
Short name T433
Test name
Test status
Simulation time 431456649 ps
CPU time 0.67 seconds
Started Feb 04 01:07:26 PM PST 24
Finished Feb 04 01:07:33 PM PST 24
Peak memory 201308 kb
Host smart-aa6fedca-ac53-4780-8bbf-68e33c5c9280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579996427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.579996427
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3821150492
Short name T823
Test name
Test status
Simulation time 163961770049 ps
CPU time 350.96 seconds
Started Feb 04 01:07:36 PM PST 24
Finished Feb 04 01:13:28 PM PST 24
Peak memory 201580 kb
Host smart-4ff94f30-0ea4-4172-b138-fef90db46eec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821150492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3821150492
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3867137694
Short name T308
Test name
Test status
Simulation time 329700620959 ps
CPU time 126.69 seconds
Started Feb 04 01:07:27 PM PST 24
Finished Feb 04 01:09:39 PM PST 24
Peak memory 201660 kb
Host smart-b4fd72d2-a386-414d-9b34-568c4828db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867137694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3867137694
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.933350644
Short name T678
Test name
Test status
Simulation time 156354905049 ps
CPU time 190.88 seconds
Started Feb 04 01:07:25 PM PST 24
Finished Feb 04 01:10:43 PM PST 24
Peak memory 201564 kb
Host smart-4d7265bc-6421-4477-abc5-e46cab58ba71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=933350644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.933350644
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3997313866
Short name T158
Test name
Test status
Simulation time 334701934108 ps
CPU time 201.32 seconds
Started Feb 04 01:07:31 PM PST 24
Finished Feb 04 01:10:54 PM PST 24
Peak memory 201612 kb
Host smart-0882cd65-c8bb-497b-9ddb-060595c7ed6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997313866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3997313866
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1530178180
Short name T605
Test name
Test status
Simulation time 491066567334 ps
CPU time 1137.86 seconds
Started Feb 04 01:07:27 PM PST 24
Finished Feb 04 01:26:31 PM PST 24
Peak memory 201692 kb
Host smart-9be77049-36b5-4835-9e07-38e9a1455ae0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530178180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1530178180
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2338246145
Short name T337
Test name
Test status
Simulation time 489995410115 ps
CPU time 1184.59 seconds
Started Feb 04 01:07:24 PM PST 24
Finished Feb 04 01:27:16 PM PST 24
Peak memory 201560 kb
Host smart-d5c1b693-d50f-4dd5-8c98-3b4da016cdf3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338246145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2338246145
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2406789994
Short name T852
Test name
Test status
Simulation time 323157074052 ps
CPU time 684.04 seconds
Started Feb 04 01:07:27 PM PST 24
Finished Feb 04 01:18:57 PM PST 24
Peak memory 201644 kb
Host smart-b6eb07d8-aa8e-470a-8353-ce1c4bddb51e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406789994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2406789994
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2751457134
Short name T500
Test name
Test status
Simulation time 126782456999 ps
CPU time 421.28 seconds
Started Feb 04 01:07:24 PM PST 24
Finished Feb 04 01:14:33 PM PST 24
Peak memory 201960 kb
Host smart-f941721d-278f-423c-b97f-df60abb5d1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751457134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2751457134
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3654035019
Short name T717
Test name
Test status
Simulation time 33709384026 ps
CPU time 40.6 seconds
Started Feb 04 01:07:23 PM PST 24
Finished Feb 04 01:08:12 PM PST 24
Peak memory 201420 kb
Host smart-b6dda40e-0f8a-4e97-a890-81b1b66abe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654035019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3654035019
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.813464825
Short name T846
Test name
Test status
Simulation time 4626383267 ps
CPU time 10.65 seconds
Started Feb 04 01:07:25 PM PST 24
Finished Feb 04 01:07:43 PM PST 24
Peak memory 201316 kb
Host smart-0c3e25fd-a49b-40a6-a631-8b0b3ace1e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813464825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.813464825
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3295125160
Short name T550
Test name
Test status
Simulation time 6116338049 ps
CPU time 4.47 seconds
Started Feb 04 01:07:29 PM PST 24
Finished Feb 04 01:07:37 PM PST 24
Peak memory 201404 kb
Host smart-79e8f9d6-37be-4799-9ef7-fca09574e7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295125160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3295125160
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.643608322
Short name T580
Test name
Test status
Simulation time 176743234469 ps
CPU time 101.29 seconds
Started Feb 04 01:07:25 PM PST 24
Finished Feb 04 01:09:13 PM PST 24
Peak memory 201564 kb
Host smart-5c2906d1-7770-43b5-bda8-f6461531a435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643608322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
643608322
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3947645452
Short name T860
Test name
Test status
Simulation time 68451314383 ps
CPU time 43.91 seconds
Started Feb 04 01:07:37 PM PST 24
Finished Feb 04 01:08:22 PM PST 24
Peak memory 201768 kb
Host smart-257d8c63-c160-4dbd-af5c-b604fca83b92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947645452 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3947645452
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2912102332
Short name T487
Test name
Test status
Simulation time 354654193 ps
CPU time 0.86 seconds
Started Feb 04 01:03:52 PM PST 24
Finished Feb 04 01:03:54 PM PST 24
Peak memory 201296 kb
Host smart-c3424cd1-cf5c-499e-be3a-d0724ec26897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912102332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2912102332
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2936349699
Short name T216
Test name
Test status
Simulation time 158936816346 ps
CPU time 338.3 seconds
Started Feb 04 01:03:37 PM PST 24
Finished Feb 04 01:09:23 PM PST 24
Peak memory 201604 kb
Host smart-06ab8282-f1bf-4bac-8d05-adbf75782bb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936349699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2936349699
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1464497862
Short name T696
Test name
Test status
Simulation time 161417831122 ps
CPU time 92.69 seconds
Started Feb 04 01:03:42 PM PST 24
Finished Feb 04 01:05:18 PM PST 24
Peak memory 201592 kb
Host smart-ed1dd347-2187-4234-8327-e473ea70cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464497862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1464497862
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1013237511
Short name T162
Test name
Test status
Simulation time 334058568261 ps
CPU time 200.33 seconds
Started Feb 04 01:03:51 PM PST 24
Finished Feb 04 01:07:12 PM PST 24
Peak memory 201504 kb
Host smart-5b8bd826-f14a-48cf-996d-f5182bd3a02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013237511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1013237511
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1451187011
Short name T434
Test name
Test status
Simulation time 166614658790 ps
CPU time 112.86 seconds
Started Feb 04 01:03:51 PM PST 24
Finished Feb 04 01:05:45 PM PST 24
Peak memory 201604 kb
Host smart-2a3bb1c7-2e82-400b-8f3f-e7321e10b91e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451187011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1451187011
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2618371754
Short name T159
Test name
Test status
Simulation time 502408850266 ps
CPU time 303.4 seconds
Started Feb 04 01:03:55 PM PST 24
Finished Feb 04 01:09:00 PM PST 24
Peak memory 201572 kb
Host smart-49caa176-7f24-4d87-a3cb-0030b5f4ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618371754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2618371754
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3714233920
Short name T55
Test name
Test status
Simulation time 164783959738 ps
CPU time 94.93 seconds
Started Feb 04 01:03:43 PM PST 24
Finished Feb 04 01:05:20 PM PST 24
Peak memory 201652 kb
Host smart-f151cad0-1804-4a83-963d-9decaf2952c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714233920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3714233920
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1438272672
Short name T301
Test name
Test status
Simulation time 168785000088 ps
CPU time 96.11 seconds
Started Feb 04 01:03:48 PM PST 24
Finished Feb 04 01:05:27 PM PST 24
Peak memory 201664 kb
Host smart-64daa908-28ff-488f-90b3-8d9f9e8ba1cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438272672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1438272672
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3953333148
Short name T599
Test name
Test status
Simulation time 168006399557 ps
CPU time 207.01 seconds
Started Feb 04 01:03:32 PM PST 24
Finished Feb 04 01:07:03 PM PST 24
Peak memory 201508 kb
Host smart-a4302e2a-eecf-476d-889f-2feede4ace16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953333148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3953333148
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.458822746
Short name T208
Test name
Test status
Simulation time 128145804603 ps
CPU time 458.72 seconds
Started Feb 04 01:03:35 PM PST 24
Finished Feb 04 01:11:23 PM PST 24
Peak memory 201940 kb
Host smart-4937fd2c-cabd-47dd-9a0b-ddf95eb7ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458822746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.458822746
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3234425401
Short name T512
Test name
Test status
Simulation time 32585975788 ps
CPU time 20.12 seconds
Started Feb 04 01:03:36 PM PST 24
Finished Feb 04 01:04:04 PM PST 24
Peak memory 201420 kb
Host smart-cdaaec9e-6336-4591-8971-c73b58dbe57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234425401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3234425401
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3140093710
Short name T645
Test name
Test status
Simulation time 3383028902 ps
CPU time 2.81 seconds
Started Feb 04 01:03:32 PM PST 24
Finished Feb 04 01:03:39 PM PST 24
Peak memory 201376 kb
Host smart-c9fed079-a98d-4a1e-a6d5-3713cb37add5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140093710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3140093710
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.954143522
Short name T43
Test name
Test status
Simulation time 8177290037 ps
CPU time 3.19 seconds
Started Feb 04 01:03:33 PM PST 24
Finished Feb 04 01:03:41 PM PST 24
Peak memory 217848 kb
Host smart-6fd98074-fdc3-4a4c-b61c-e717aa4b847c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954143522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.954143522
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3499610114
Short name T508
Test name
Test status
Simulation time 6001142131 ps
CPU time 13.62 seconds
Started Feb 04 01:03:33 PM PST 24
Finished Feb 04 01:03:51 PM PST 24
Peak memory 201300 kb
Host smart-de5e7461-4183-422d-a0fc-18df48627bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499610114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3499610114
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3973953721
Short name T248
Test name
Test status
Simulation time 337815151472 ps
CPU time 787.21 seconds
Started Feb 04 01:03:37 PM PST 24
Finished Feb 04 01:16:52 PM PST 24
Peak memory 201588 kb
Host smart-7b990ef2-e1e4-4988-9c98-d622d55b7968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973953721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3973953721
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3074321825
Short name T854
Test name
Test status
Simulation time 268948955693 ps
CPU time 156.15 seconds
Started Feb 04 01:03:35 PM PST 24
Finished Feb 04 01:06:20 PM PST 24
Peak memory 210392 kb
Host smart-cfc868c2-4f99-4733-96e1-e16363cba6ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074321825 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3074321825
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2235038590
Short name T602
Test name
Test status
Simulation time 344853911 ps
CPU time 0.79 seconds
Started Feb 04 01:07:37 PM PST 24
Finished Feb 04 01:07:39 PM PST 24
Peak memory 201284 kb
Host smart-127cd82c-5adf-4741-ab8c-7183250817c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235038590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2235038590
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2975595185
Short name T699
Test name
Test status
Simulation time 329473841566 ps
CPU time 198.65 seconds
Started Feb 04 01:07:33 PM PST 24
Finished Feb 04 01:10:52 PM PST 24
Peak memory 201580 kb
Host smart-84308971-834b-4ca1-9a8a-e1871725e2eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975595185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2975595185
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1658678598
Short name T325
Test name
Test status
Simulation time 324728080920 ps
CPU time 710.07 seconds
Started Feb 04 01:07:33 PM PST 24
Finished Feb 04 01:19:25 PM PST 24
Peak memory 201624 kb
Host smart-e0752a4f-997c-4617-8ea3-61c379b2b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658678598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1658678598
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3088058347
Short name T274
Test name
Test status
Simulation time 160410409953 ps
CPU time 90.55 seconds
Started Feb 04 01:07:34 PM PST 24
Finished Feb 04 01:09:06 PM PST 24
Peak memory 201572 kb
Host smart-2a12f887-bc35-4793-b61b-6aba0b32b43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088058347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3088058347
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.4140870395
Short name T435
Test name
Test status
Simulation time 494080738896 ps
CPU time 327.16 seconds
Started Feb 04 01:07:35 PM PST 24
Finished Feb 04 01:13:03 PM PST 24
Peak memory 201552 kb
Host smart-4bf10dad-e255-4ba5-b490-da933978b1f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140870395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.4140870395
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3301216904
Short name T324
Test name
Test status
Simulation time 494970983276 ps
CPU time 1143.14 seconds
Started Feb 04 01:07:25 PM PST 24
Finished Feb 04 01:26:35 PM PST 24
Peak memory 201624 kb
Host smart-6794e3e6-7d63-4f5c-abf8-21252dd21840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301216904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3301216904
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2809042939
Short name T514
Test name
Test status
Simulation time 330299532003 ps
CPU time 194.59 seconds
Started Feb 04 01:07:34 PM PST 24
Finished Feb 04 01:10:50 PM PST 24
Peak memory 201608 kb
Host smart-1a3c68f4-223e-45f6-952f-80b8fe801d48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809042939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2809042939
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1420186224
Short name T242
Test name
Test status
Simulation time 160373088458 ps
CPU time 384.71 seconds
Started Feb 04 01:07:34 PM PST 24
Finished Feb 04 01:14:01 PM PST 24
Peak memory 201592 kb
Host smart-3c547e85-7245-4369-b772-e326261eb960
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420186224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1420186224
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3357192396
Short name T143
Test name
Test status
Simulation time 497283732166 ps
CPU time 241.47 seconds
Started Feb 04 01:07:33 PM PST 24
Finished Feb 04 01:11:36 PM PST 24
Peak memory 201600 kb
Host smart-2405d4da-8067-4a52-87ff-5a9b25bf8219
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357192396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3357192396
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2972299092
Short name T679
Test name
Test status
Simulation time 104100993072 ps
CPU time 563.67 seconds
Started Feb 04 01:07:37 PM PST 24
Finished Feb 04 01:17:02 PM PST 24
Peak memory 201888 kb
Host smart-8bc0d392-b9fa-454e-a2db-7141db242f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972299092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2972299092
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3641574798
Short name T568
Test name
Test status
Simulation time 41051540500 ps
CPU time 85.8 seconds
Started Feb 04 01:07:34 PM PST 24
Finished Feb 04 01:09:01 PM PST 24
Peak memory 201404 kb
Host smart-9d83ca35-fe67-4fd7-af0b-834f193fb299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641574798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3641574798
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4213861774
Short name T627
Test name
Test status
Simulation time 3050537070 ps
CPU time 8.05 seconds
Started Feb 04 01:07:36 PM PST 24
Finished Feb 04 01:07:45 PM PST 24
Peak memory 201388 kb
Host smart-85aab563-6c41-4e24-9524-655f85a4fa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213861774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4213861774
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2526254945
Short name T478
Test name
Test status
Simulation time 6042939685 ps
CPU time 3.49 seconds
Started Feb 04 01:07:29 PM PST 24
Finished Feb 04 01:07:36 PM PST 24
Peak memory 201272 kb
Host smart-9408d0c2-b5cd-43db-ae11-afdbd3a30b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526254945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2526254945
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2771447747
Short name T443
Test name
Test status
Simulation time 86401571046 ps
CPU time 32.15 seconds
Started Feb 04 01:07:36 PM PST 24
Finished Feb 04 01:08:10 PM PST 24
Peak memory 201408 kb
Host smart-729a4b34-90c2-4986-8949-49cf741bb745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771447747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2771447747
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.401737694
Short name T615
Test name
Test status
Simulation time 225919471858 ps
CPU time 56.55 seconds
Started Feb 04 01:07:37 PM PST 24
Finished Feb 04 01:08:34 PM PST 24
Peak memory 217260 kb
Host smart-30ae4400-ba22-4b93-9751-acd45b7b20ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401737694 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.401737694
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3901525929
Short name T596
Test name
Test status
Simulation time 447277081 ps
CPU time 0.9 seconds
Started Feb 04 01:07:53 PM PST 24
Finished Feb 04 01:08:00 PM PST 24
Peak memory 201272 kb
Host smart-440f2832-e003-456e-ba90-d2d356ef0a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901525929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3901525929
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.468337739
Short name T729
Test name
Test status
Simulation time 503885862788 ps
CPU time 370.37 seconds
Started Feb 04 01:07:50 PM PST 24
Finished Feb 04 01:14:03 PM PST 24
Peak memory 201600 kb
Host smart-1513bda0-92c6-42f8-a5a5-9381145e0ea3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468337739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.468337739
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1055254151
Short name T809
Test name
Test status
Simulation time 168007185452 ps
CPU time 25.38 seconds
Started Feb 04 01:07:56 PM PST 24
Finished Feb 04 01:08:25 PM PST 24
Peak memory 201612 kb
Host smart-30d31874-6c77-49eb-8881-ed11464b4ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055254151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1055254151
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.553879526
Short name T234
Test name
Test status
Simulation time 161512149526 ps
CPU time 89.88 seconds
Started Feb 04 01:07:51 PM PST 24
Finished Feb 04 01:09:24 PM PST 24
Peak memory 201668 kb
Host smart-172b50c0-0e29-46b9-96df-64ddfc2aa74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553879526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.553879526
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3615442919
Short name T616
Test name
Test status
Simulation time 160531143074 ps
CPU time 90.96 seconds
Started Feb 04 01:07:51 PM PST 24
Finished Feb 04 01:09:25 PM PST 24
Peak memory 201548 kb
Host smart-00dd35bd-67f3-4589-b004-3ff46908553b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615442919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3615442919
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2451046390
Short name T847
Test name
Test status
Simulation time 489948897128 ps
CPU time 495.29 seconds
Started Feb 04 01:07:34 PM PST 24
Finished Feb 04 01:15:51 PM PST 24
Peak memory 201660 kb
Host smart-7d051761-7da0-4733-8320-8c2ea882e53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451046390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2451046390
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3534777555
Short name T453
Test name
Test status
Simulation time 164700226079 ps
CPU time 385.04 seconds
Started Feb 04 01:07:53 PM PST 24
Finished Feb 04 01:14:24 PM PST 24
Peak memory 201628 kb
Host smart-e7d6d50a-eea4-4862-ad86-663b46d4389f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534777555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3534777555
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1266663073
Short name T716
Test name
Test status
Simulation time 162365456970 ps
CPU time 360.49 seconds
Started Feb 04 01:07:53 PM PST 24
Finished Feb 04 01:13:59 PM PST 24
Peak memory 201640 kb
Host smart-ab368aba-fa4b-4c62-a4af-489c6a0ecc51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266663073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1266663073
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1270922833
Short name T438
Test name
Test status
Simulation time 496087509342 ps
CPU time 1204.37 seconds
Started Feb 04 01:07:48 PM PST 24
Finished Feb 04 01:27:56 PM PST 24
Peak memory 201640 kb
Host smart-985e6089-298b-475e-8d6a-d779307de4b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270922833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1270922833
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3845994836
Short name T200
Test name
Test status
Simulation time 135115138162 ps
CPU time 413.38 seconds
Started Feb 04 01:07:50 PM PST 24
Finished Feb 04 01:14:46 PM PST 24
Peak memory 201960 kb
Host smart-a59f04d7-31ed-4fe5-a6de-aad97e50ee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845994836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3845994836
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1179760193
Short name T831
Test name
Test status
Simulation time 32957354637 ps
CPU time 37.16 seconds
Started Feb 04 01:07:49 PM PST 24
Finished Feb 04 01:08:29 PM PST 24
Peak memory 201436 kb
Host smart-dac09cc0-b989-471a-b60b-a5181f53e15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179760193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1179760193
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2931731830
Short name T153
Test name
Test status
Simulation time 3979578687 ps
CPU time 10.33 seconds
Started Feb 04 01:07:50 PM PST 24
Finished Feb 04 01:08:03 PM PST 24
Peak memory 201336 kb
Host smart-d11bcff6-fe87-452f-8b24-672a43264aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931731830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2931731830
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.78548987
Short name T175
Test name
Test status
Simulation time 5698261784 ps
CPU time 14.03 seconds
Started Feb 04 01:07:33 PM PST 24
Finished Feb 04 01:07:49 PM PST 24
Peak memory 201380 kb
Host smart-ccb40093-e41c-4074-af1a-cc54f8a42f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78548987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.78548987
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1431433568
Short name T700
Test name
Test status
Simulation time 51982033958 ps
CPU time 189.9 seconds
Started Feb 04 01:07:50 PM PST 24
Finished Feb 04 01:11:02 PM PST 24
Peak memory 210300 kb
Host smart-bc572b08-0125-44d8-81ce-9c31429de5f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431433568 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1431433568
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1394832054
Short name T507
Test name
Test status
Simulation time 436234980 ps
CPU time 1.58 seconds
Started Feb 04 01:08:12 PM PST 24
Finished Feb 04 01:08:15 PM PST 24
Peak memory 201304 kb
Host smart-d49fb283-ac70-4cf0-845e-88c31e773456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394832054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1394832054
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2522303091
Short name T662
Test name
Test status
Simulation time 167696984484 ps
CPU time 271.27 seconds
Started Feb 04 01:08:12 PM PST 24
Finished Feb 04 01:12:45 PM PST 24
Peak memory 201616 kb
Host smart-eab70784-1b72-4b4f-ad96-319ea0d18685
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522303091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2522303091
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3776485777
Short name T304
Test name
Test status
Simulation time 168142303281 ps
CPU time 186.32 seconds
Started Feb 04 01:08:11 PM PST 24
Finished Feb 04 01:11:19 PM PST 24
Peak memory 201544 kb
Host smart-d0c25ae7-c9a0-4926-b37c-ac7d2deee357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776485777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3776485777
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.563811639
Short name T794
Test name
Test status
Simulation time 333002877292 ps
CPU time 760.34 seconds
Started Feb 04 01:07:49 PM PST 24
Finished Feb 04 01:20:32 PM PST 24
Peak memory 201516 kb
Host smart-9484c334-6e36-4549-a594-d5bb9b97b8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563811639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.563811639
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2164073032
Short name T773
Test name
Test status
Simulation time 331806625096 ps
CPU time 205.92 seconds
Started Feb 04 01:07:49 PM PST 24
Finished Feb 04 01:11:18 PM PST 24
Peak memory 201520 kb
Host smart-cb95117d-7524-4f01-a769-538c7fd009de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164073032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2164073032
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3952590307
Short name T137
Test name
Test status
Simulation time 170008718572 ps
CPU time 94.4 seconds
Started Feb 04 01:07:53 PM PST 24
Finished Feb 04 01:09:33 PM PST 24
Peak memory 201672 kb
Host smart-422b251d-d74b-402e-9f61-37ed4a4b4df9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952590307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3952590307
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1088116998
Short name T657
Test name
Test status
Simulation time 164962519922 ps
CPU time 383.84 seconds
Started Feb 04 01:07:48 PM PST 24
Finished Feb 04 01:14:15 PM PST 24
Peak memory 201552 kb
Host smart-5d73a21a-e62b-4403-854c-36f3e66860f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088116998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1088116998
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2265090715
Short name T546
Test name
Test status
Simulation time 331743727596 ps
CPU time 798.69 seconds
Started Feb 04 01:08:12 PM PST 24
Finished Feb 04 01:21:32 PM PST 24
Peak memory 201532 kb
Host smart-aa4c9baf-99de-46e7-a638-dc0896e68b4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265090715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2265090715
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3222512303
Short name T718
Test name
Test status
Simulation time 73114526737 ps
CPU time 317.53 seconds
Started Feb 04 01:08:12 PM PST 24
Finished Feb 04 01:13:30 PM PST 24
Peak memory 201940 kb
Host smart-0b18b767-c43e-4b78-a6e0-75eaaec9c8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222512303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3222512303
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.4008210591
Short name T477
Test name
Test status
Simulation time 37563012523 ps
CPU time 87.43 seconds
Started Feb 04 01:08:13 PM PST 24
Finished Feb 04 01:09:41 PM PST 24
Peak memory 201308 kb
Host smart-fad1a23e-f704-4e1d-9f07-d146cb8c4615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008210591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.4008210591
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2607519108
Short name T472
Test name
Test status
Simulation time 3947839898 ps
CPU time 9.85 seconds
Started Feb 04 01:08:13 PM PST 24
Finished Feb 04 01:08:25 PM PST 24
Peak memory 201388 kb
Host smart-e1cf7ad9-4290-469c-8dc8-668f25ebf6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607519108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2607519108
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.304961241
Short name T644
Test name
Test status
Simulation time 5750882514 ps
CPU time 3.79 seconds
Started Feb 04 01:07:49 PM PST 24
Finished Feb 04 01:07:55 PM PST 24
Peak memory 201384 kb
Host smart-68ec97d3-fca9-4f20-86c6-39deed84407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304961241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.304961241
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2118776990
Short name T632
Test name
Test status
Simulation time 3800257206 ps
CPU time 10.22 seconds
Started Feb 04 01:08:11 PM PST 24
Finished Feb 04 01:08:23 PM PST 24
Peak memory 201360 kb
Host smart-fc350637-98ec-4abb-80dc-502a320ede8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118776990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2118776990
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3135513794
Short name T711
Test name
Test status
Simulation time 503626825 ps
CPU time 1.77 seconds
Started Feb 04 01:08:13 PM PST 24
Finished Feb 04 01:08:16 PM PST 24
Peak memory 201264 kb
Host smart-3ae271ca-2c50-4960-a01e-0b7fce962f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135513794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3135513794
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.197599977
Short name T352
Test name
Test status
Simulation time 335259952476 ps
CPU time 511.44 seconds
Started Feb 04 01:08:19 PM PST 24
Finished Feb 04 01:16:53 PM PST 24
Peak memory 201644 kb
Host smart-c8d8ff37-6cee-4170-8a6f-29b295b5b56f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197599977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.197599977
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.978971576
Short name T330
Test name
Test status
Simulation time 329244890308 ps
CPU time 81.92 seconds
Started Feb 04 01:08:09 PM PST 24
Finished Feb 04 01:09:32 PM PST 24
Peak memory 201508 kb
Host smart-f33a1657-014c-46a3-929f-d8806b3760fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978971576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.978971576
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1145182567
Short name T230
Test name
Test status
Simulation time 162109606454 ps
CPU time 185.95 seconds
Started Feb 04 01:08:13 PM PST 24
Finished Feb 04 01:11:20 PM PST 24
Peak memory 201616 kb
Host smart-3d9a3ed4-cd05-4079-87c7-4bbd02026239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145182567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1145182567
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2279664596
Short name T800
Test name
Test status
Simulation time 161315656306 ps
CPU time 369.37 seconds
Started Feb 04 01:08:11 PM PST 24
Finished Feb 04 01:14:22 PM PST 24
Peak memory 201632 kb
Host smart-a8736a9f-c0e0-41c5-8c02-8643b9726432
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279664596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2279664596
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3204274341
Short name T266
Test name
Test status
Simulation time 494449412968 ps
CPU time 309.22 seconds
Started Feb 04 01:08:11 PM PST 24
Finished Feb 04 01:13:22 PM PST 24
Peak memory 201592 kb
Host smart-b18b544d-5d1d-4382-9314-58634461b6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204274341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3204274341
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.847997645
Short name T548
Test name
Test status
Simulation time 494214482933 ps
CPU time 167.43 seconds
Started Feb 04 01:08:11 PM PST 24
Finished Feb 04 01:11:00 PM PST 24
Peak memory 201636 kb
Host smart-059dfbea-c5e8-4810-9229-04b08171889e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=847997645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.847997645
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.566710388
Short name T240
Test name
Test status
Simulation time 332630513030 ps
CPU time 226.22 seconds
Started Feb 04 01:08:11 PM PST 24
Finished Feb 04 01:11:58 PM PST 24
Peak memory 201536 kb
Host smart-7bc2dd5d-8a64-401c-810a-20dc7355c4be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566710388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.566710388
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3220100151
Short name T479
Test name
Test status
Simulation time 482126385227 ps
CPU time 183.21 seconds
Started Feb 04 01:08:14 PM PST 24
Finished Feb 04 01:11:19 PM PST 24
Peak memory 201536 kb
Host smart-b99bb713-ee0c-4587-ada7-80491126c212
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220100151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3220100151
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2282186895
Short name T205
Test name
Test status
Simulation time 70052573563 ps
CPU time 260.92 seconds
Started Feb 04 01:08:12 PM PST 24
Finished Feb 04 01:12:34 PM PST 24
Peak memory 201904 kb
Host smart-3bed50fd-b579-4486-8111-73701bd64278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282186895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2282186895
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1346823238
Short name T591
Test name
Test status
Simulation time 38263768615 ps
CPU time 33.91 seconds
Started Feb 04 01:08:12 PM PST 24
Finished Feb 04 01:08:47 PM PST 24
Peak memory 201460 kb
Host smart-e14f6da4-c1ed-4987-be80-df59017a3f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346823238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1346823238
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1865989668
Short name T639
Test name
Test status
Simulation time 2727035605 ps
CPU time 2.19 seconds
Started Feb 04 01:08:14 PM PST 24
Finished Feb 04 01:08:19 PM PST 24
Peak memory 201304 kb
Host smart-3eba6fcc-5bac-4cf1-86fb-dc132bc4332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865989668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1865989668
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2361813956
Short name T607
Test name
Test status
Simulation time 6063967793 ps
CPU time 4.41 seconds
Started Feb 04 01:08:12 PM PST 24
Finished Feb 04 01:08:18 PM PST 24
Peak memory 201320 kb
Host smart-546ed84a-9b96-4def-ae5b-340646929bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361813956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2361813956
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2137498049
Short name T733
Test name
Test status
Simulation time 350585097 ps
CPU time 0.8 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:09:07 PM PST 24
Peak memory 201260 kb
Host smart-6bda4e57-8dc3-4171-b7cc-8d537aa2306b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137498049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2137498049
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2239774323
Short name T103
Test name
Test status
Simulation time 162429898839 ps
CPU time 188.05 seconds
Started Feb 04 01:09:01 PM PST 24
Finished Feb 04 01:12:10 PM PST 24
Peak memory 201644 kb
Host smart-dc82280b-c986-4388-aceb-c20e7c580ce4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239774323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2239774323
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1994802195
Short name T351
Test name
Test status
Simulation time 327212142508 ps
CPU time 104.09 seconds
Started Feb 04 01:08:45 PM PST 24
Finished Feb 04 01:10:30 PM PST 24
Peak memory 201636 kb
Host smart-7981346f-de3d-4744-b62c-a01cacf70019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994802195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1994802195
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3142381732
Short name T226
Test name
Test status
Simulation time 159718699571 ps
CPU time 188.79 seconds
Started Feb 04 01:09:01 PM PST 24
Finished Feb 04 01:12:11 PM PST 24
Peak memory 201760 kb
Host smart-6fccc9e4-c869-4b8a-8707-90c68847ad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142381732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3142381732
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1854974000
Short name T676
Test name
Test status
Simulation time 492745668353 ps
CPU time 88.61 seconds
Started Feb 04 01:08:56 PM PST 24
Finished Feb 04 01:10:27 PM PST 24
Peak memory 201568 kb
Host smart-a6c41ccc-9e24-4df0-bc53-e2e67b94e8a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854974000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1854974000
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2414563766
Short name T215
Test name
Test status
Simulation time 332832376629 ps
CPU time 408.37 seconds
Started Feb 04 01:08:45 PM PST 24
Finished Feb 04 01:15:34 PM PST 24
Peak memory 201628 kb
Host smart-dc3aae99-ba9a-43a1-8367-ae332e133561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414563766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2414563766
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3054901186
Short name T575
Test name
Test status
Simulation time 169388633325 ps
CPU time 101.81 seconds
Started Feb 04 01:08:45 PM PST 24
Finished Feb 04 01:10:28 PM PST 24
Peak memory 201548 kb
Host smart-112bd09f-8f22-4754-be30-3a9ad8824654
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054901186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3054901186
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1548972945
Short name T155
Test name
Test status
Simulation time 413757539086 ps
CPU time 364.46 seconds
Started Feb 04 01:09:02 PM PST 24
Finished Feb 04 01:15:07 PM PST 24
Peak memory 201648 kb
Host smart-0caaaf01-477e-4529-8257-14c0ad50029a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548972945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1548972945
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2961031287
Short name T53
Test name
Test status
Simulation time 157303545914 ps
CPU time 366.98 seconds
Started Feb 04 01:08:44 PM PST 24
Finished Feb 04 01:14:52 PM PST 24
Peak memory 201640 kb
Host smart-a5b8684e-01fd-42cf-a883-2914a5752739
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961031287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2961031287
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2404373093
Short name T194
Test name
Test status
Simulation time 90522243617 ps
CPU time 479.38 seconds
Started Feb 04 01:08:45 PM PST 24
Finished Feb 04 01:16:45 PM PST 24
Peak memory 201884 kb
Host smart-5f3f093a-7714-43ad-8821-735014c6c623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404373093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2404373093
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3561702900
Short name T625
Test name
Test status
Simulation time 42294424389 ps
CPU time 24.25 seconds
Started Feb 04 01:09:08 PM PST 24
Finished Feb 04 01:09:33 PM PST 24
Peak memory 201404 kb
Host smart-b4abbea1-7bf2-4957-81d6-463a1eb7dce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561702900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3561702900
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.4212683001
Short name T462
Test name
Test status
Simulation time 3159641629 ps
CPU time 4.4 seconds
Started Feb 04 01:09:07 PM PST 24
Finished Feb 04 01:09:13 PM PST 24
Peak memory 201388 kb
Host smart-de3659da-1230-43ec-acca-1590e26dfd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212683001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.4212683001
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.917679111
Short name T502
Test name
Test status
Simulation time 5558020757 ps
CPU time 7.58 seconds
Started Feb 04 01:08:47 PM PST 24
Finished Feb 04 01:08:57 PM PST 24
Peak memory 201100 kb
Host smart-f459eb8e-690c-4aa2-87f8-64bf011da927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917679111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.917679111
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.759698151
Short name T93
Test name
Test status
Simulation time 279789239230 ps
CPU time 276.51 seconds
Started Feb 04 01:08:44 PM PST 24
Finished Feb 04 01:13:21 PM PST 24
Peak memory 212312 kb
Host smart-88792643-7bd9-44d6-b104-22e40953dd7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759698151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
759698151
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2318940291
Short name T855
Test name
Test status
Simulation time 382299912253 ps
CPU time 204.68 seconds
Started Feb 04 01:09:00 PM PST 24
Finished Feb 04 01:12:26 PM PST 24
Peak memory 209908 kb
Host smart-aa0ed028-e886-4a62-90f4-d4ea8c2fd1a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318940291 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2318940291
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2196234848
Short name T473
Test name
Test status
Simulation time 381132100 ps
CPU time 1.45 seconds
Started Feb 04 01:09:15 PM PST 24
Finished Feb 04 01:09:18 PM PST 24
Peak memory 201288 kb
Host smart-3882fecb-be75-446c-b010-7510c8c08b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196234848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2196234848
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2469887765
Short name T738
Test name
Test status
Simulation time 326344579425 ps
CPU time 729.76 seconds
Started Feb 04 01:08:48 PM PST 24
Finished Feb 04 01:21:00 PM PST 24
Peak memory 201592 kb
Host smart-e33fe58a-4345-4974-bfa9-15f841972203
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469887765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2469887765
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3961724991
Short name T774
Test name
Test status
Simulation time 165765432179 ps
CPU time 393.48 seconds
Started Feb 04 01:09:03 PM PST 24
Finished Feb 04 01:15:38 PM PST 24
Peak memory 201648 kb
Host smart-8ef16a47-5925-47cc-a40c-ab5b19574262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961724991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3961724991
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2694372467
Short name T321
Test name
Test status
Simulation time 165026717158 ps
CPU time 98.45 seconds
Started Feb 04 01:09:00 PM PST 24
Finished Feb 04 01:10:40 PM PST 24
Peak memory 201648 kb
Host smart-8f170123-943a-408e-9877-94946f857fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694372467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2694372467
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1583006431
Short name T469
Test name
Test status
Simulation time 494375385347 ps
CPU time 296.85 seconds
Started Feb 04 01:09:03 PM PST 24
Finished Feb 04 01:14:01 PM PST 24
Peak memory 201536 kb
Host smart-30f96f16-ae20-479a-9182-dcf919b36c8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583006431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1583006431
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3876441285
Short name T320
Test name
Test status
Simulation time 489035799989 ps
CPU time 372.88 seconds
Started Feb 04 01:08:46 PM PST 24
Finished Feb 04 01:15:02 PM PST 24
Peak memory 201608 kb
Host smart-a42cd29d-7c9b-481b-8b33-91d831f9c178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876441285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3876441285
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2275804089
Short name T848
Test name
Test status
Simulation time 329147083341 ps
CPU time 735.75 seconds
Started Feb 04 01:09:03 PM PST 24
Finished Feb 04 01:21:20 PM PST 24
Peak memory 201492 kb
Host smart-d13273c2-2418-43cf-a826-bbee620c3b0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275804089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2275804089
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.496107066
Short name T110
Test name
Test status
Simulation time 329812538044 ps
CPU time 202.28 seconds
Started Feb 04 01:09:00 PM PST 24
Finished Feb 04 01:12:24 PM PST 24
Peak memory 201620 kb
Host smart-bdf92048-aac4-4e2b-9ed9-15156ad95e4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496107066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.496107066
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3662344905
Short name T22
Test name
Test status
Simulation time 167175460301 ps
CPU time 191.54 seconds
Started Feb 04 01:08:47 PM PST 24
Finished Feb 04 01:12:01 PM PST 24
Peak memory 201332 kb
Host smart-918f6c43-935e-42a7-91bb-7c69c6fe2966
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662344905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3662344905
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.4096106191
Short name T367
Test name
Test status
Simulation time 124726476251 ps
CPU time 660.42 seconds
Started Feb 04 01:09:04 PM PST 24
Finished Feb 04 01:20:05 PM PST 24
Peak memory 201740 kb
Host smart-0b802a9b-ec8c-49f6-9462-a2af8590d787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096106191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.4096106191
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3334877168
Short name T646
Test name
Test status
Simulation time 37626991815 ps
CPU time 22.93 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:09:29 PM PST 24
Peak memory 201436 kb
Host smart-6c777ed2-32bf-4652-85cf-00b89f945cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334877168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3334877168
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.786903132
Short name T841
Test name
Test status
Simulation time 3205465697 ps
CPU time 7.81 seconds
Started Feb 04 01:08:45 PM PST 24
Finished Feb 04 01:08:55 PM PST 24
Peak memory 201364 kb
Host smart-3b1803cd-2aa6-4c59-a951-3128da8d5f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786903132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.786903132
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1624886442
Short name T613
Test name
Test status
Simulation time 5822535002 ps
CPU time 4.12 seconds
Started Feb 04 01:08:47 PM PST 24
Finished Feb 04 01:08:54 PM PST 24
Peak memory 201320 kb
Host smart-d812a614-0036-4037-9c24-3e6deda2e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624886442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1624886442
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1802766352
Short name T245
Test name
Test status
Simulation time 198939795191 ps
CPU time 475.88 seconds
Started Feb 04 01:09:01 PM PST 24
Finished Feb 04 01:16:58 PM PST 24
Peak memory 210260 kb
Host smart-5af11138-7f69-4ee7-a419-7db37decd94e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802766352 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1802766352
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3262026187
Short name T708
Test name
Test status
Simulation time 431458132 ps
CPU time 1.02 seconds
Started Feb 04 01:09:06 PM PST 24
Finished Feb 04 01:09:08 PM PST 24
Peak memory 201152 kb
Host smart-7279768e-67b8-4ebd-b3ac-e841ca246529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262026187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3262026187
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3623172953
Short name T641
Test name
Test status
Simulation time 163112697773 ps
CPU time 392.74 seconds
Started Feb 04 01:09:11 PM PST 24
Finished Feb 04 01:15:45 PM PST 24
Peak memory 201556 kb
Host smart-337f9d54-107e-448e-b214-0202b3c7be5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623172953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3623172953
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2413049239
Short name T552
Test name
Test status
Simulation time 494716120810 ps
CPU time 1162.04 seconds
Started Feb 04 01:09:07 PM PST 24
Finished Feb 04 01:28:31 PM PST 24
Peak memory 201640 kb
Host smart-77585d33-473f-40ea-b593-7bf09ca51f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413049239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2413049239
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2022621644
Short name T135
Test name
Test status
Simulation time 163795656964 ps
CPU time 193.81 seconds
Started Feb 04 01:09:00 PM PST 24
Finished Feb 04 01:12:15 PM PST 24
Peak memory 201588 kb
Host smart-e854136a-00d4-41a4-855e-6f2445481dc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022621644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2022621644
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2508999858
Short name T182
Test name
Test status
Simulation time 488360104429 ps
CPU time 387.16 seconds
Started Feb 04 01:09:04 PM PST 24
Finished Feb 04 01:15:32 PM PST 24
Peak memory 201516 kb
Host smart-559f9ccf-c762-40bb-b52f-29818b350e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508999858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2508999858
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1178558014
Short name T136
Test name
Test status
Simulation time 157828915289 ps
CPU time 278.3 seconds
Started Feb 04 01:09:14 PM PST 24
Finished Feb 04 01:13:53 PM PST 24
Peak memory 201552 kb
Host smart-dfc772c6-9f52-4900-a471-c32d91996463
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178558014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1178558014
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4291317146
Short name T339
Test name
Test status
Simulation time 327346194815 ps
CPU time 266.36 seconds
Started Feb 04 01:09:09 PM PST 24
Finished Feb 04 01:13:36 PM PST 24
Peak memory 201604 kb
Host smart-4e60b3f6-8cc2-4202-8813-6733fd490a2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291317146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.4291317146
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2864356650
Short name T497
Test name
Test status
Simulation time 485615995510 ps
CPU time 590.79 seconds
Started Feb 04 01:09:10 PM PST 24
Finished Feb 04 01:19:01 PM PST 24
Peak memory 201656 kb
Host smart-fad5145d-6cef-434f-9f88-02655038dea3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864356650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2864356650
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3588392277
Short name T703
Test name
Test status
Simulation time 113355048919 ps
CPU time 642.76 seconds
Started Feb 04 01:09:15 PM PST 24
Finished Feb 04 01:19:59 PM PST 24
Peak memory 201888 kb
Host smart-c77e581a-4764-464f-9333-288a2050b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588392277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3588392277
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2287912176
Short name T528
Test name
Test status
Simulation time 23504987685 ps
CPU time 53.68 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:09:59 PM PST 24
Peak memory 201376 kb
Host smart-181e12e2-8957-42d9-bb61-668443f882cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287912176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2287912176
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1104442436
Short name T635
Test name
Test status
Simulation time 5027548648 ps
CPU time 4.65 seconds
Started Feb 04 01:09:08 PM PST 24
Finished Feb 04 01:09:14 PM PST 24
Peak memory 201340 kb
Host smart-aa1be7f4-59a7-4725-ab0c-7bbfb8bfe827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104442436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1104442436
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.552579148
Short name T94
Test name
Test status
Simulation time 5778262886 ps
CPU time 4.59 seconds
Started Feb 04 01:09:06 PM PST 24
Finished Feb 04 01:09:12 PM PST 24
Peak memory 201336 kb
Host smart-4e21e565-40f3-49b2-84b0-f2ee174fde7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552579148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.552579148
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.56347143
Short name T626
Test name
Test status
Simulation time 317309705033 ps
CPU time 407.26 seconds
Started Feb 04 01:09:03 PM PST 24
Finished Feb 04 01:15:51 PM PST 24
Peak memory 218204 kb
Host smart-8849d0b4-17b8-4156-80f3-a15d5fb59074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56347143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.56347143
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1638602981
Short name T235
Test name
Test status
Simulation time 73372871094 ps
CPU time 132.53 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:11:19 PM PST 24
Peak memory 210064 kb
Host smart-cb98fb64-f5d7-4f5e-8b01-b4adeaa08f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638602981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1638602981
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1376555011
Short name T838
Test name
Test status
Simulation time 522573846 ps
CPU time 1.33 seconds
Started Feb 04 01:09:02 PM PST 24
Finished Feb 04 01:09:04 PM PST 24
Peak memory 201264 kb
Host smart-acefdbe8-4f00-41d4-aabc-33fecf230971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376555011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1376555011
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.38450290
Short name T562
Test name
Test status
Simulation time 493319041727 ps
CPU time 259.8 seconds
Started Feb 04 01:09:12 PM PST 24
Finished Feb 04 01:13:33 PM PST 24
Peak memory 201508 kb
Host smart-fe3e4f78-7761-4f83-bc31-8fdbb9b6dbb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38450290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gatin
g.38450290
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.358327235
Short name T612
Test name
Test status
Simulation time 327131057496 ps
CPU time 407.46 seconds
Started Feb 04 01:09:03 PM PST 24
Finished Feb 04 01:15:51 PM PST 24
Peak memory 201688 kb
Host smart-b45a7450-4b09-4793-a5ad-29aab9ade823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358327235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.358327235
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.732649473
Short name T816
Test name
Test status
Simulation time 169250698384 ps
CPU time 106.89 seconds
Started Feb 04 01:09:04 PM PST 24
Finished Feb 04 01:10:52 PM PST 24
Peak memory 201524 kb
Host smart-cd424efd-8861-41b7-9e95-f3b7f042808d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=732649473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.732649473
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.185414415
Short name T232
Test name
Test status
Simulation time 168189094260 ps
CPU time 387.87 seconds
Started Feb 04 01:09:16 PM PST 24
Finished Feb 04 01:15:45 PM PST 24
Peak memory 201644 kb
Host smart-32495d6c-71e9-449b-b3f2-cd707a79ca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185414415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.185414415
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.41284794
Short name T474
Test name
Test status
Simulation time 329200082081 ps
CPU time 52.28 seconds
Started Feb 04 01:09:08 PM PST 24
Finished Feb 04 01:10:02 PM PST 24
Peak memory 201556 kb
Host smart-fa81b3f2-b78d-4083-83a2-4cd1e5b3aeec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=41284794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed
.41284794
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.573019491
Short name T183
Test name
Test status
Simulation time 501849798014 ps
CPU time 578.41 seconds
Started Feb 04 01:09:03 PM PST 24
Finished Feb 04 01:18:43 PM PST 24
Peak memory 201556 kb
Host smart-ac7d73fd-b817-4893-a96a-6758091b2f4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573019491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.573019491
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1179100671
Short name T822
Test name
Test status
Simulation time 332192448434 ps
CPU time 53.21 seconds
Started Feb 04 01:09:10 PM PST 24
Finished Feb 04 01:10:04 PM PST 24
Peak memory 201652 kb
Host smart-735e1bf0-4afe-4480-9f15-56abadbadd14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179100671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1179100671
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1524454440
Short name T210
Test name
Test status
Simulation time 85919293697 ps
CPU time 343.62 seconds
Started Feb 04 01:09:12 PM PST 24
Finished Feb 04 01:14:57 PM PST 24
Peak memory 201936 kb
Host smart-feb110d7-5d55-47db-b336-f174cf552c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524454440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1524454440
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.587984905
Short name T592
Test name
Test status
Simulation time 28179589961 ps
CPU time 16.72 seconds
Started Feb 04 01:09:04 PM PST 24
Finished Feb 04 01:09:22 PM PST 24
Peak memory 201428 kb
Host smart-c9a02ff9-e628-49fe-bc4b-a9a1f40018b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587984905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.587984905
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2174195303
Short name T638
Test name
Test status
Simulation time 3958764880 ps
CPU time 10.54 seconds
Started Feb 04 01:09:04 PM PST 24
Finished Feb 04 01:09:16 PM PST 24
Peak memory 201420 kb
Host smart-52bf3f5d-c7c6-4f71-a680-f0cc5e7dbebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174195303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2174195303
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3572084681
Short name T510
Test name
Test status
Simulation time 5625059888 ps
CPU time 12.76 seconds
Started Feb 04 01:09:09 PM PST 24
Finished Feb 04 01:09:23 PM PST 24
Peak memory 201336 kb
Host smart-8b52f072-fb10-42da-b54e-7c775163c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572084681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3572084681
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4090891348
Short name T365
Test name
Test status
Simulation time 145330742018 ps
CPU time 512.66 seconds
Started Feb 04 01:09:06 PM PST 24
Finished Feb 04 01:17:40 PM PST 24
Peak memory 202008 kb
Host smart-1230d706-7d2b-4d80-8068-db9e66e94109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090891348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4090891348
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3559129511
Short name T745
Test name
Test status
Simulation time 298405475 ps
CPU time 0.84 seconds
Started Feb 04 01:09:08 PM PST 24
Finished Feb 04 01:09:10 PM PST 24
Peak memory 201264 kb
Host smart-5d4e35f2-cbcc-4652-accc-b89f1e3fa903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559129511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3559129511
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2086850295
Short name T713
Test name
Test status
Simulation time 326835299097 ps
CPU time 767.96 seconds
Started Feb 04 01:09:02 PM PST 24
Finished Feb 04 01:21:51 PM PST 24
Peak memory 201620 kb
Host smart-3e15baef-ed47-4456-be0a-92fa7bfb2034
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086850295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2086850295
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3367631576
Short name T101
Test name
Test status
Simulation time 328448098114 ps
CPU time 751.75 seconds
Started Feb 04 01:09:06 PM PST 24
Finished Feb 04 01:21:39 PM PST 24
Peak memory 201600 kb
Host smart-246c4536-5d30-463f-8713-1f5b3f7f386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367631576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3367631576
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1443671949
Short name T702
Test name
Test status
Simulation time 161550890336 ps
CPU time 340.98 seconds
Started Feb 04 01:09:04 PM PST 24
Finished Feb 04 01:14:45 PM PST 24
Peak memory 201572 kb
Host smart-2ef0803d-ebe0-4ecd-966b-7579832030e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443671949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1443671949
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2339042798
Short name T483
Test name
Test status
Simulation time 497247515271 ps
CPU time 1136.41 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:28:03 PM PST 24
Peak memory 201632 kb
Host smart-672ce5d2-1391-4936-8477-469cd63d13e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339042798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2339042798
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3539003084
Short name T239
Test name
Test status
Simulation time 493890745717 ps
CPU time 1060.03 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:26:47 PM PST 24
Peak memory 201668 kb
Host smart-2e6edaa6-8703-4408-9031-fc1fa26dbd2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539003084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3539003084
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2199070107
Short name T732
Test name
Test status
Simulation time 165491700051 ps
CPU time 203.58 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:12:30 PM PST 24
Peak memory 201684 kb
Host smart-259181e1-8676-4281-a79d-7f74db0bddd9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199070107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2199070107
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1325983562
Short name T778
Test name
Test status
Simulation time 108696354167 ps
CPU time 359.53 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:15:05 PM PST 24
Peak memory 201952 kb
Host smart-ac00aad7-d0f7-42b5-961a-4d82ddd65839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325983562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1325983562
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1381084146
Short name T431
Test name
Test status
Simulation time 24058902443 ps
CPU time 54.48 seconds
Started Feb 04 01:09:02 PM PST 24
Finished Feb 04 01:09:58 PM PST 24
Peak memory 201380 kb
Host smart-644b38d6-36d2-4c5b-add7-059bffe357cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381084146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1381084146
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2182370434
Short name T531
Test name
Test status
Simulation time 2868538727 ps
CPU time 2.59 seconds
Started Feb 04 01:09:15 PM PST 24
Finished Feb 04 01:09:19 PM PST 24
Peak memory 201416 kb
Host smart-288b01bd-182c-4f48-b18b-e22e4cf67a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182370434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2182370434
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1075778472
Short name T476
Test name
Test status
Simulation time 5893525560 ps
CPU time 14.5 seconds
Started Feb 04 01:09:12 PM PST 24
Finished Feb 04 01:09:28 PM PST 24
Peak memory 201340 kb
Host smart-92e2a0fc-35b7-429e-8207-aacd3e6eacb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075778472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1075778472
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2019932080
Short name T217
Test name
Test status
Simulation time 228204156492 ps
CPU time 150.16 seconds
Started Feb 04 01:09:06 PM PST 24
Finished Feb 04 01:11:37 PM PST 24
Peak memory 201484 kb
Host smart-67357d96-1292-4169-bbb7-3d1fa1b7bd22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019932080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2019932080
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2172844941
Short name T96
Test name
Test status
Simulation time 51981282543 ps
CPU time 125.02 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:11:11 PM PST 24
Peak memory 202052 kb
Host smart-51ed7cd2-3cdf-4174-be95-c24d8387b0ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172844941 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2172844941
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3032797342
Short name T723
Test name
Test status
Simulation time 551188504 ps
CPU time 0.81 seconds
Started Feb 04 01:09:23 PM PST 24
Finished Feb 04 01:09:28 PM PST 24
Peak memory 201268 kb
Host smart-ad869cea-dca7-42bc-96b2-f62dcad4679e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032797342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3032797342
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2517717533
Short name T323
Test name
Test status
Simulation time 499155952159 ps
CPU time 79.94 seconds
Started Feb 04 01:09:22 PM PST 24
Finished Feb 04 01:10:47 PM PST 24
Peak memory 201588 kb
Host smart-db191e18-3c0c-4d86-a14f-c2ef1105df51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517717533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2517717533
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4173310395
Short name T311
Test name
Test status
Simulation time 327259016404 ps
CPU time 795.81 seconds
Started Feb 04 01:09:24 PM PST 24
Finished Feb 04 01:22:43 PM PST 24
Peak memory 201560 kb
Host smart-bef3e6af-65d2-4936-8925-542aa68f4e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173310395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4173310395
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1103529330
Short name T830
Test name
Test status
Simulation time 164371288379 ps
CPU time 89.73 seconds
Started Feb 04 01:09:15 PM PST 24
Finished Feb 04 01:10:46 PM PST 24
Peak memory 201568 kb
Host smart-33db830a-5962-401e-bf56-f64e03c30be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103529330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1103529330
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3194704358
Short name T49
Test name
Test status
Simulation time 493946126468 ps
CPU time 1152.36 seconds
Started Feb 04 01:09:18 PM PST 24
Finished Feb 04 01:28:33 PM PST 24
Peak memory 201572 kb
Host smart-5d46e5d5-72b8-4c64-9df3-f5661f1c8e4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194704358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3194704358
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1778869963
Short name T134
Test name
Test status
Simulation time 326736003613 ps
CPU time 61.42 seconds
Started Feb 04 01:09:14 PM PST 24
Finished Feb 04 01:10:16 PM PST 24
Peak memory 201640 kb
Host smart-6d519c2c-fd15-4c43-8404-9f74c487e111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778869963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1778869963
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.291098347
Short name T12
Test name
Test status
Simulation time 331330349794 ps
CPU time 206.81 seconds
Started Feb 04 01:09:05 PM PST 24
Finished Feb 04 01:12:33 PM PST 24
Peak memory 201544 kb
Host smart-14c2f786-1f57-4689-aec3-2392a75986ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=291098347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.291098347
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.985737399
Short name T259
Test name
Test status
Simulation time 165421733910 ps
CPU time 94.66 seconds
Started Feb 04 01:09:15 PM PST 24
Finished Feb 04 01:10:51 PM PST 24
Peak memory 201552 kb
Host smart-835e46fd-bd69-4834-93ff-8f9495ccd27c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985737399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.985737399
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2023644152
Short name T590
Test name
Test status
Simulation time 328798474084 ps
CPU time 794.9 seconds
Started Feb 04 01:09:13 PM PST 24
Finished Feb 04 01:22:29 PM PST 24
Peak memory 201464 kb
Host smart-5107aac1-2e26-423c-88a5-205430eff87a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023644152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2023644152
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1848524432
Short name T647
Test name
Test status
Simulation time 103871214682 ps
CPU time 392.82 seconds
Started Feb 04 01:09:24 PM PST 24
Finished Feb 04 01:16:00 PM PST 24
Peak memory 201800 kb
Host smart-1e5bfaac-9e26-445a-8a03-c3ab26bb9d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848524432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1848524432
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.908775481
Short name T572
Test name
Test status
Simulation time 38458634571 ps
CPU time 93 seconds
Started Feb 04 01:09:13 PM PST 24
Finished Feb 04 01:10:48 PM PST 24
Peak memory 201332 kb
Host smart-b31b80ae-b993-48c9-b335-838417bbb7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908775481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.908775481
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3854773962
Short name T518
Test name
Test status
Simulation time 4618600072 ps
CPU time 12.31 seconds
Started Feb 04 01:09:26 PM PST 24
Finished Feb 04 01:09:40 PM PST 24
Peak memory 201340 kb
Host smart-70254653-dd46-4550-9e34-fbe6904f34da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854773962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3854773962
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1123660146
Short name T849
Test name
Test status
Simulation time 6049959210 ps
CPU time 13.98 seconds
Started Feb 04 01:09:01 PM PST 24
Finished Feb 04 01:09:16 PM PST 24
Peak memory 201300 kb
Host smart-bdff976e-cd2e-4c4e-adae-dd72444dc7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123660146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1123660146
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1171670490
Short name T535
Test name
Test status
Simulation time 381244174 ps
CPU time 1.52 seconds
Started Feb 04 01:04:02 PM PST 24
Finished Feb 04 01:04:05 PM PST 24
Peak memory 201304 kb
Host smart-dd2a7551-237c-48f8-bf4b-f70b497c1f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171670490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1171670490
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3583402310
Short name T255
Test name
Test status
Simulation time 328289570452 ps
CPU time 183.17 seconds
Started Feb 04 01:03:34 PM PST 24
Finished Feb 04 01:06:41 PM PST 24
Peak memory 201732 kb
Host smart-a9f13675-0760-4aa2-a1e4-bf421af6969c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583402310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3583402310
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1211050704
Short name T748
Test name
Test status
Simulation time 320216153438 ps
CPU time 188.02 seconds
Started Feb 04 01:03:37 PM PST 24
Finished Feb 04 01:06:53 PM PST 24
Peak memory 201708 kb
Host smart-ae7918f4-2879-451e-be4c-a08efb81204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211050704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1211050704
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3398287528
Short name T791
Test name
Test status
Simulation time 489720337142 ps
CPU time 630.7 seconds
Started Feb 04 01:03:35 PM PST 24
Finished Feb 04 01:14:09 PM PST 24
Peak memory 201552 kb
Host smart-4cefebbb-93f1-4cd7-bcf6-f0e059513dd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398287528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3398287528
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2381414612
Short name T127
Test name
Test status
Simulation time 328997998131 ps
CPU time 379.22 seconds
Started Feb 04 01:03:40 PM PST 24
Finished Feb 04 01:10:05 PM PST 24
Peak memory 201640 kb
Host smart-93ec03a3-99ff-4dd9-935f-5c1c5cef3a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381414612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2381414612
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3447957310
Short name T650
Test name
Test status
Simulation time 329698693518 ps
CPU time 213.5 seconds
Started Feb 04 01:03:51 PM PST 24
Finished Feb 04 01:07:25 PM PST 24
Peak memory 201648 kb
Host smart-39c362da-83f2-4cae-92f2-bc34592cd4e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447957310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3447957310
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2453197016
Short name T463
Test name
Test status
Simulation time 328024444106 ps
CPU time 760.52 seconds
Started Feb 04 01:03:57 PM PST 24
Finished Feb 04 01:16:38 PM PST 24
Peak memory 201636 kb
Host smart-5f3e42c7-b31d-42ff-9e2f-fc62befb28f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453197016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2453197016
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.323483337
Short name T704
Test name
Test status
Simulation time 103546889742 ps
CPU time 438.8 seconds
Started Feb 04 01:04:02 PM PST 24
Finished Feb 04 01:11:22 PM PST 24
Peak memory 201924 kb
Host smart-e7f74867-dd29-4fc6-8aa5-256636dec8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323483337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.323483337
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.952814913
Short name T525
Test name
Test status
Simulation time 39167206342 ps
CPU time 96.74 seconds
Started Feb 04 01:04:05 PM PST 24
Finished Feb 04 01:05:48 PM PST 24
Peak memory 201372 kb
Host smart-8c0d8291-ca47-4d7b-b0fd-4924652f8c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952814913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.952814913
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2479112187
Short name T842
Test name
Test status
Simulation time 3153383385 ps
CPU time 2.48 seconds
Started Feb 04 01:03:52 PM PST 24
Finished Feb 04 01:03:55 PM PST 24
Peak memory 201404 kb
Host smart-9d6b9603-ff20-4112-94f1-0919430c5b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479112187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2479112187
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1928199893
Short name T165
Test name
Test status
Simulation time 5639985647 ps
CPU time 3.8 seconds
Started Feb 04 01:03:45 PM PST 24
Finished Feb 04 01:03:54 PM PST 24
Peak memory 201304 kb
Host smart-5f10bc20-bb94-4b63-90f7-04d31d4d19f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928199893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1928199893
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.209503831
Short name T728
Test name
Test status
Simulation time 396496196195 ps
CPU time 441.25 seconds
Started Feb 04 01:04:03 PM PST 24
Finished Feb 04 01:11:26 PM PST 24
Peak memory 210288 kb
Host smart-6fa3de67-9a6b-4261-902b-91fadfa7c53f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209503831 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.209503831
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.594880158
Short name T828
Test name
Test status
Simulation time 345110276 ps
CPU time 0.76 seconds
Started Feb 04 01:04:01 PM PST 24
Finished Feb 04 01:04:03 PM PST 24
Peak memory 201264 kb
Host smart-cbd41dbc-3ebb-4530-9a8f-02ff42b86507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594880158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.594880158
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3831757009
Short name T781
Test name
Test status
Simulation time 324529921916 ps
CPU time 349.27 seconds
Started Feb 04 01:04:01 PM PST 24
Finished Feb 04 01:09:51 PM PST 24
Peak memory 201680 kb
Host smart-a8df2826-e3b5-47cb-ba40-1b00ada28f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831757009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3831757009
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.814196592
Short name T229
Test name
Test status
Simulation time 329790127732 ps
CPU time 259.97 seconds
Started Feb 04 01:04:01 PM PST 24
Finished Feb 04 01:08:22 PM PST 24
Peak memory 201620 kb
Host smart-f1e504a1-ac3e-4bab-94d8-4e2e16332a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814196592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.814196592
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2851420172
Short name T694
Test name
Test status
Simulation time 321889991312 ps
CPU time 167.82 seconds
Started Feb 04 01:04:05 PM PST 24
Finished Feb 04 01:06:59 PM PST 24
Peak memory 201560 kb
Host smart-5fa540cd-3610-4289-b32f-b9c5c3966db8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851420172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2851420172
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2155396027
Short name T290
Test name
Test status
Simulation time 166831856707 ps
CPU time 412.02 seconds
Started Feb 04 01:04:04 PM PST 24
Finished Feb 04 01:10:58 PM PST 24
Peak memory 201560 kb
Host smart-d2389da5-d1d2-43e1-aac4-7539664c5fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155396027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2155396027
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.4007189476
Short name T441
Test name
Test status
Simulation time 335509962224 ps
CPU time 51.4 seconds
Started Feb 04 01:04:02 PM PST 24
Finished Feb 04 01:04:55 PM PST 24
Peak memory 201604 kb
Host smart-5f81494d-5a3f-4fbb-927a-2bd614ffef01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007189476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.4007189476
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3324831196
Short name T280
Test name
Test status
Simulation time 490862075367 ps
CPU time 304.37 seconds
Started Feb 04 01:04:01 PM PST 24
Finished Feb 04 01:09:07 PM PST 24
Peak memory 201632 kb
Host smart-f16db292-e7b9-4670-8afa-3e32928c96ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324831196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3324831196
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.426569968
Short name T440
Test name
Test status
Simulation time 328625357676 ps
CPU time 718.86 seconds
Started Feb 04 01:04:03 PM PST 24
Finished Feb 04 01:16:04 PM PST 24
Peak memory 201588 kb
Host smart-a35b792b-9773-4525-8214-af55b8d76c16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426569968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.426569968
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3961439097
Short name T369
Test name
Test status
Simulation time 96243211855 ps
CPU time 351.85 seconds
Started Feb 04 01:04:04 PM PST 24
Finished Feb 04 01:09:58 PM PST 24
Peak memory 201884 kb
Host smart-7fde4f2e-6634-4603-b212-24f635883837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961439097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3961439097
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.544722874
Short name T681
Test name
Test status
Simulation time 43211883566 ps
CPU time 26.43 seconds
Started Feb 04 01:04:05 PM PST 24
Finished Feb 04 01:04:37 PM PST 24
Peak memory 201372 kb
Host smart-38065bd2-a7e1-4382-a660-2f92ce497eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544722874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.544722874
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4163058859
Short name T533
Test name
Test status
Simulation time 4863675285 ps
CPU time 10.34 seconds
Started Feb 04 01:04:02 PM PST 24
Finished Feb 04 01:04:14 PM PST 24
Peak memory 201400 kb
Host smart-33bf46b3-e886-4f2b-ac4e-010f32cfe80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163058859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4163058859
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2827756396
Short name T485
Test name
Test status
Simulation time 5847633075 ps
CPU time 9.67 seconds
Started Feb 04 01:04:04 PM PST 24
Finished Feb 04 01:04:15 PM PST 24
Peak memory 201268 kb
Host smart-7ec91bfa-c333-45cf-b487-80a47e120320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827756396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2827756396
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2826517951
Short name T861
Test name
Test status
Simulation time 5841106260 ps
CPU time 7.42 seconds
Started Feb 04 01:04:03 PM PST 24
Finished Feb 04 01:04:12 PM PST 24
Peak memory 201360 kb
Host smart-04f9024f-b7d3-48a5-95be-03ee63d66623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826517951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2826517951
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1981993631
Short name T227
Test name
Test status
Simulation time 89169510079 ps
CPU time 72.19 seconds
Started Feb 04 01:04:07 PM PST 24
Finished Feb 04 01:05:27 PM PST 24
Peak memory 209932 kb
Host smart-a1f94783-06df-4834-8107-5196271ec55c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981993631 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1981993631
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4128085563
Short name T804
Test name
Test status
Simulation time 322392338 ps
CPU time 1.39 seconds
Started Feb 04 01:04:07 PM PST 24
Finished Feb 04 01:04:16 PM PST 24
Peak memory 201204 kb
Host smart-6dc4023a-c904-4580-981e-c6c87946a7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128085563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4128085563
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2213264052
Short name T757
Test name
Test status
Simulation time 491327091417 ps
CPU time 239.7 seconds
Started Feb 04 01:04:04 PM PST 24
Finished Feb 04 01:08:06 PM PST 24
Peak memory 201636 kb
Host smart-fa07997e-2f67-4138-b0f4-bebc8bccc5e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213264052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2213264052
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2847627242
Short name T765
Test name
Test status
Simulation time 158160449873 ps
CPU time 89.47 seconds
Started Feb 04 01:04:02 PM PST 24
Finished Feb 04 01:05:33 PM PST 24
Peak memory 201648 kb
Host smart-cf6ba2e5-baf8-4684-aa65-307dceb6ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847627242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2847627242
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.657512917
Short name T299
Test name
Test status
Simulation time 160702764447 ps
CPU time 142.15 seconds
Started Feb 04 01:04:00 PM PST 24
Finished Feb 04 01:06:23 PM PST 24
Peak memory 201664 kb
Host smart-000d7ad2-6a50-46dc-b43d-203735242868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657512917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.657512917
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1212584144
Short name T629
Test name
Test status
Simulation time 163388107173 ps
CPU time 101.94 seconds
Started Feb 04 01:04:12 PM PST 24
Finished Feb 04 01:05:57 PM PST 24
Peak memory 201552 kb
Host smart-23c4af75-0e88-4b8e-bf51-5626f4a5820c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212584144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1212584144
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2887024449
Short name T294
Test name
Test status
Simulation time 501267783879 ps
CPU time 223.06 seconds
Started Feb 04 01:04:01 PM PST 24
Finished Feb 04 01:07:45 PM PST 24
Peak memory 201564 kb
Host smart-eb2fe823-dff4-415d-902a-8d57381b864c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887024449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2887024449
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4174974841
Short name T496
Test name
Test status
Simulation time 329275523699 ps
CPU time 716.17 seconds
Started Feb 04 01:04:05 PM PST 24
Finished Feb 04 01:16:08 PM PST 24
Peak memory 201224 kb
Host smart-056e4be5-3faf-41e7-9c1f-fd6662179ba1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174974841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4174974841
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4147791924
Short name T13
Test name
Test status
Simulation time 165968428180 ps
CPU time 88.98 seconds
Started Feb 04 01:04:07 PM PST 24
Finished Feb 04 01:05:43 PM PST 24
Peak memory 201596 kb
Host smart-d7cb182f-9c07-47c9-8475-f94b34c57916
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147791924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4147791924
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.347272469
Short name T680
Test name
Test status
Simulation time 86988452229 ps
CPU time 337.47 seconds
Started Feb 04 01:04:02 PM PST 24
Finished Feb 04 01:09:41 PM PST 24
Peak memory 201896 kb
Host smart-e98d01d3-68f6-4d18-90ec-34aca171e92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347272469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.347272469
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.697266593
Short name T743
Test name
Test status
Simulation time 44058640948 ps
CPU time 27.33 seconds
Started Feb 04 01:04:04 PM PST 24
Finished Feb 04 01:04:34 PM PST 24
Peak memory 201396 kb
Host smart-d82db384-3481-4d3c-951b-b2c733cd750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697266593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.697266593
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3845369302
Short name T767
Test name
Test status
Simulation time 4963411155 ps
CPU time 3.48 seconds
Started Feb 04 01:04:04 PM PST 24
Finished Feb 04 01:04:09 PM PST 24
Peak memory 201396 kb
Host smart-c5b2f5ed-55ad-45a9-a9d5-fc1b58ba7441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845369302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3845369302
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2908436630
Short name T793
Test name
Test status
Simulation time 5925908474 ps
CPU time 4.22 seconds
Started Feb 04 01:04:05 PM PST 24
Finished Feb 04 01:04:15 PM PST 24
Peak memory 201428 kb
Host smart-b7c38cfe-88fe-4e1d-8d66-e692d7798921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908436630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2908436630
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.220758236
Short name T786
Test name
Test status
Simulation time 369674125528 ps
CPU time 236 seconds
Started Feb 04 01:04:05 PM PST 24
Finished Feb 04 01:08:08 PM PST 24
Peak memory 201232 kb
Host smart-b702dab9-8619-4975-9f1f-f4620b2c781f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220758236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.220758236
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3953273605
Short name T338
Test name
Test status
Simulation time 85031338133 ps
CPU time 118.19 seconds
Started Feb 04 01:04:04 PM PST 24
Finished Feb 04 01:06:04 PM PST 24
Peak memory 210276 kb
Host smart-97209ef8-cd44-4cc6-ab15-91257ef7dda5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953273605 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3953273605
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3083721523
Short name T637
Test name
Test status
Simulation time 287762147 ps
CPU time 0.96 seconds
Started Feb 04 01:04:16 PM PST 24
Finished Feb 04 01:04:19 PM PST 24
Peak memory 201288 kb
Host smart-9f02993e-3174-486d-ae10-d3135080162e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083721523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3083721523
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1320074906
Short name T241
Test name
Test status
Simulation time 343426678154 ps
CPU time 101.16 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:06:03 PM PST 24
Peak memory 201088 kb
Host smart-8dd7ca65-87da-4b3d-8b72-716721f984c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320074906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1320074906
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2649437985
Short name T307
Test name
Test status
Simulation time 329341059223 ps
CPU time 736.05 seconds
Started Feb 04 01:04:16 PM PST 24
Finished Feb 04 01:16:34 PM PST 24
Peak memory 201668 kb
Host smart-db150440-b830-422d-bd58-33b9ba91925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649437985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2649437985
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2224287017
Short name T739
Test name
Test status
Simulation time 163028875944 ps
CPU time 119.63 seconds
Started Feb 04 01:04:10 PM PST 24
Finished Feb 04 01:06:14 PM PST 24
Peak memory 201540 kb
Host smart-1c1c4ac3-0c9a-45a2-96ce-6a132717809b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224287017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2224287017
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.4252626307
Short name T21
Test name
Test status
Simulation time 489927456758 ps
CPU time 1205.2 seconds
Started Feb 04 01:04:03 PM PST 24
Finished Feb 04 01:24:10 PM PST 24
Peak memory 201604 kb
Host smart-6e141998-a309-4f9d-a09f-81121b6f19d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252626307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.4252626307
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2186326559
Short name T547
Test name
Test status
Simulation time 502784362865 ps
CPU time 574.88 seconds
Started Feb 04 01:04:13 PM PST 24
Finished Feb 04 01:13:51 PM PST 24
Peak memory 201684 kb
Host smart-07f6958f-f19d-47c3-b8cc-89be57580789
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186326559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2186326559
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1858265054
Short name T188
Test name
Test status
Simulation time 168773647963 ps
CPU time 93.75 seconds
Started Feb 04 01:04:12 PM PST 24
Finished Feb 04 01:05:49 PM PST 24
Peak memory 201664 kb
Host smart-4d5607f4-0cb4-4ba5-9851-25f5a48bf961
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858265054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1858265054
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.819222361
Short name T710
Test name
Test status
Simulation time 486599449521 ps
CPU time 1093.64 seconds
Started Feb 04 01:04:12 PM PST 24
Finished Feb 04 01:22:29 PM PST 24
Peak memory 201596 kb
Host smart-74612656-6e18-4120-9cd0-ef89c2f40eeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819222361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.819222361
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1984629190
Short name T202
Test name
Test status
Simulation time 121087168963 ps
CPU time 566.09 seconds
Started Feb 04 01:04:18 PM PST 24
Finished Feb 04 01:13:46 PM PST 24
Peak memory 201940 kb
Host smart-f825558a-c277-43e9-b2a8-835185b9fdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984629190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1984629190
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3302318744
Short name T571
Test name
Test status
Simulation time 24607633668 ps
CPU time 29.59 seconds
Started Feb 04 01:04:11 PM PST 24
Finished Feb 04 01:04:44 PM PST 24
Peak memory 201396 kb
Host smart-8bb25edc-3cd8-4294-97fc-05a272ffe70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302318744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3302318744
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2502894340
Short name T498
Test name
Test status
Simulation time 5273641983 ps
CPU time 3.84 seconds
Started Feb 04 01:04:10 PM PST 24
Finished Feb 04 01:04:19 PM PST 24
Peak memory 201428 kb
Host smart-2a2118a7-68c7-4884-acb9-a94841d20994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502894340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2502894340
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2103935784
Short name T600
Test name
Test status
Simulation time 6078071362 ps
CPU time 4.18 seconds
Started Feb 04 01:04:02 PM PST 24
Finished Feb 04 01:04:07 PM PST 24
Peak memory 201436 kb
Host smart-c9aaed32-32c3-4586-a3e6-8d2c3cf56ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103935784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2103935784
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1276902413
Short name T819
Test name
Test status
Simulation time 11653850123 ps
CPU time 27.95 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:04:49 PM PST 24
Peak memory 201508 kb
Host smart-eca1636d-811f-4233-871b-9a89e623c875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276902413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1276902413
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3771825381
Short name T539
Test name
Test status
Simulation time 100644122821 ps
CPU time 122.36 seconds
Started Feb 04 01:04:11 PM PST 24
Finished Feb 04 01:06:17 PM PST 24
Peak memory 210280 kb
Host smart-3ac74428-9b42-48d9-91f2-2ad8394207a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771825381 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3771825381
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2592542068
Short name T768
Test name
Test status
Simulation time 337244251 ps
CPU time 1.06 seconds
Started Feb 04 01:04:16 PM PST 24
Finished Feb 04 01:04:18 PM PST 24
Peak memory 201276 kb
Host smart-6ee5ce65-1d70-4b43-9c57-9c64a40a384b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592542068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2592542068
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1426363381
Short name T275
Test name
Test status
Simulation time 159228577171 ps
CPU time 360.81 seconds
Started Feb 04 01:04:17 PM PST 24
Finished Feb 04 01:10:19 PM PST 24
Peak memory 201568 kb
Host smart-52696bf2-0763-4001-a35b-dadb1900e480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426363381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1426363381
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2157000493
Short name T363
Test name
Test status
Simulation time 166912878705 ps
CPU time 397.46 seconds
Started Feb 04 01:04:16 PM PST 24
Finished Feb 04 01:10:55 PM PST 24
Peak memory 201572 kb
Host smart-8d6944ea-618d-4c10-a64c-6bebeda13c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157000493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2157000493
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3044416310
Short name T532
Test name
Test status
Simulation time 494237957033 ps
CPU time 1140.67 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:23:22 PM PST 24
Peak memory 200968 kb
Host smart-6e37f1d6-3036-4175-887a-7370f13381ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044416310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3044416310
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.345764024
Short name T359
Test name
Test status
Simulation time 504097118230 ps
CPU time 308.89 seconds
Started Feb 04 01:04:11 PM PST 24
Finished Feb 04 01:09:24 PM PST 24
Peak memory 201520 kb
Host smart-837a1ecb-8a2e-4c8a-8a43-9bbf3601715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345764024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.345764024
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3578314755
Short name T660
Test name
Test status
Simulation time 163676750264 ps
CPU time 362.67 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:10:24 PM PST 24
Peak memory 201576 kb
Host smart-03dda77d-5850-46c4-b1c9-3817e3b88676
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578314755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3578314755
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1550160591
Short name T149
Test name
Test status
Simulation time 501902049445 ps
CPU time 185.81 seconds
Started Feb 04 01:04:13 PM PST 24
Finished Feb 04 01:07:22 PM PST 24
Peak memory 201660 kb
Host smart-2a25e631-ee20-4e26-94f6-f03d554d2496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550160591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1550160591
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.474285788
Short name T569
Test name
Test status
Simulation time 170100519651 ps
CPU time 406.99 seconds
Started Feb 04 01:04:16 PM PST 24
Finished Feb 04 01:11:04 PM PST 24
Peak memory 201620 kb
Host smart-c7935b05-3b43-4edf-b8a7-ebb639311722
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474285788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.474285788
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2182469099
Short name T753
Test name
Test status
Simulation time 80057169116 ps
CPU time 478.62 seconds
Started Feb 04 01:04:17 PM PST 24
Finished Feb 04 01:12:17 PM PST 24
Peak memory 201904 kb
Host smart-1d7f14b5-ecfa-4bdd-ba54-7427b50c3eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182469099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2182469099
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.357522057
Short name T538
Test name
Test status
Simulation time 30893462188 ps
CPU time 39.65 seconds
Started Feb 04 01:04:16 PM PST 24
Finished Feb 04 01:04:57 PM PST 24
Peak memory 201352 kb
Host smart-d74025aa-c3d2-4014-8126-73f9159d80d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357522057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.357522057
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1543795712
Short name T16
Test name
Test status
Simulation time 5215995111 ps
CPU time 5.4 seconds
Started Feb 04 01:04:20 PM PST 24
Finished Feb 04 01:04:27 PM PST 24
Peak memory 201400 kb
Host smart-500c1eb3-7e34-41c6-8f38-7dd04385b7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543795712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1543795712
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.303203884
Short name T665
Test name
Test status
Simulation time 6075268637 ps
CPU time 15.86 seconds
Started Feb 04 01:04:11 PM PST 24
Finished Feb 04 01:04:31 PM PST 24
Peak memory 201416 kb
Host smart-21d33f89-a179-45bc-af33-23681dea7cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303203884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.303203884
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2494100734
Short name T140
Test name
Test status
Simulation time 54026977188 ps
CPU time 117.16 seconds
Started Feb 04 01:04:17 PM PST 24
Finished Feb 04 01:06:15 PM PST 24
Peak memory 210004 kb
Host smart-9138720a-d99a-4d23-88d7-62747d38479b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494100734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2494100734
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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