Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7140	1			T11	58		T16	43		T18	6
testmodes[AdcCtrlTestmodeNormal]	5417	1			T11	44		T12	2		T14	3
testmodes[AdcCtrlTestmodeLowpower]	5586	1			T10	2		T11	46		T12	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3992	1			T11	25		T16	33		T18	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1718	1			T11	15		T16	6		T18	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1304	1			T11	17		T16	4		T30	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1717	1			T11	20		T16	7		T18	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2029	1			T11	10		T14	2		T16	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1338	1			T11	14		T12	2		T16	6
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1313	1			T11	12		T16	3		T30	5
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1333	1			T11	19		T12	1		T16	6
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2704	1			T10	1		T11	15		T12	2