Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22096

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3534

1

T10

16

T13

11

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19746

1

T22

1

T24

1

T25

1

auto[1]

5884

1

T11

2

T12

9

T13

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	452	1			T11	2		T16	6		T30	4
values[0]	7	1			T187	1		T188	6		-	-
values[1]	704	1			T55	13		T148	10		T94	7
values[2]	2621	1			T14	3		T17	2		T19	10
values[3]	691	1			T111	26		T189	13		T121	21
values[4]	821	1			T13	11		T190	1		T81	23
values[5]	581	1			T10	8		T16	5		T84	22
values[6]	620	1			T12	9		T113	17		T30	24
values[7]	808	1			T10	8		T189	14		T191	15
values[8]	706	1			T17	9		T21	5		T55	9
values[9]	810	1			T15	2		T20	1		T55	10
minimum	16809	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	928	1			T55	13		T100	7		T148	10
values[1]	2579	1			T14	3		T17	2		T19	10
values[2]	623	1			T93	15		T85	1		T189	13
values[3]	761	1			T13	11		T190	1		T113	12
values[4]	734	1			T10	8		T12	9		T16	5
values[5]	686	1			T10	8		T113	17		T30	24
values[6]	808	1			T97	16		T123	3		T88	2
values[7]	609	1			T17	9		T21	5		T55	9
values[8]	615	1			T15	2		T20	1		T55	10
values[9]	39	1			T126	3		T151	1		T192	14
minimum	17248	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[9] , minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T100	7		T148	8		T94	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T55	11		T193	11		T99	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T14	3		T17	1		T19	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	2		T84	9		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T93	1		T85	1		T87	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T189	1		T121	10		T99	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T85	13		T194	12		T86	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	11		T190	1		T113	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	7		T16	3		T111	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	6		T16	1		T84	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T113	9		T189	1		T195	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	1		T30	13		T194	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T97	8		T88	1		T196	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T123	3		T90	1		T131	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	1		T113	11		T112	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	9		T55	3		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	1		T20	1		T55	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T96	1		T195	8		T154	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T151	1		T192	14		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T126	3		T197	1		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T11	148		T12	1		T16	80
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T148	2		T94	1		T95	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T55	2		T193	10		T99	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T17	1		T116	6		T92	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T96	18		T199	2		T200	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T93	14		T87	4		T50	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T189	12		T121	11		T99	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T85	14		T194	11		T86	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T113	8		T139	2		T191	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	2		T16	1		T111	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	2		T84	10		T81	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T113	8		T189	13		T195	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	7		T30	11		T194	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T97	8		T88	1		T196	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T90	7		T131	12		T107	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T21	4		T113	14		T112	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T55	6		T148	5		T199	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T15	1		T201	2		T89	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T96	7		T195	8		T154	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T202	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T22	1		T24	1		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T11	2		T16	6		T30	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T203	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T187	1		T188	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T148	8		T94	6		T95	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T55	11		T193	11		T118	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T14	3		T17	1		T19	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T20	2		T84	9		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T111	12		T123	2		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T189	1		T121	10		T99	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T85	14		T86	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	11		T190	1		T81	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	3		T111	14		T33	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	6		T16	1		T84	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	7		T113	9		T78	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	13		T117	3		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T189	1		T191	1		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	1		T131	10		T205	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	1		T112	11		T97	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	9		T55	3		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	1		T20	1		T55	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T96	1		T195	8		T154	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16683	1			T11	146		T12	1		T16	74
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T203	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T188	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T148	2		T94	1		T95	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T55	2		T193	10		T118	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T17	1		T116	6		T92	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T96	18		T99	14		T199	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T111	14		T46	6		T50	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T189	12		T121	11		T99	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T85	14		T86	3		T87	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T81	12		T113	8		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T16	1		T111	12		T33	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	2		T84	10		T85	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T12	2		T113	8		T78	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	11		T117	1		T50	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T189	13		T191	14		T196	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	7		T131	12		T207	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T21	4		T112	9		T97	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T55	6		T148	5		T199	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	1		T113	14		T195	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T96	7		T195	8		T154	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T100	1		T148	3		T94	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T55	3		T193	11		T99	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T14	3		T17	2		T19	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T20	2		T84	1		T96	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T93	15		T85	1		T87	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T189	13		T121	12		T99	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T85	15		T194	12		T86	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	1		T190	1		T113	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	7		T16	3		T111	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	3		T16	1		T84	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T113	9		T189	14		T195	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	8		T30	17		T194	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T97	9		T88	2		T196	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T123	1		T90	8		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T21	5		T113	15		T112	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	1		T55	7		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	2		T20	1		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T96	8		T195	9		T154	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T151	1		T192	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T126	1		T197	1		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17248	1			T22	1		T24	1		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T100	6		T148	7		T94	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T55	10		T193	10		T99	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T19	9		T53	22		T54	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T84	8		T104	12		T199	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T208	19		T209	13		T210	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T121	9		T99	12		T114	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T85	12		T194	11		T211	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	10		T113	3		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	2		T16	1		T111	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	5		T84	11		T81	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T113	8		T195	13		T104	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	7		T194	5		T117	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T97	7		T196	5		T105	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T123	2		T131	9		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T113	10		T112	10		T195	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T17	8		T55	2		T104	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T55	9		T201	6		T200	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T195	7		T154	2		T106	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T192	13		T202	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T126	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T11	2		T16	6		T30	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T203	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T187	1		T188	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T148	3		T94	5		T95	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T55	3		T193	11		T118	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T14	3		T17	2		T19	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	2		T84	1		T96	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T111	15		T123	1		T46	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T189	13		T121	12		T99	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T85	16		T86	4		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	1		T190	1		T81	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	3		T111	13		T33	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	3		T16	1		T84	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	7		T113	9		T78	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T30	17		T117	3		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T189	14		T191	15		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	8		T131	13		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	5		T112	10		T97	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	1		T55	7		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	2		T20	1		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T96	8		T195	9		T154	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16809	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T203	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T188	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T148	7		T94	2		T95	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T55	10		T193	10		T118	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	878	1			T19	9		T53	22		T54	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T84	8		T99	12		T199	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T111	11		T123	1		T212	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T121	9		T99	12		T104	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T85	12		T208	19		T209	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	10		T81	10		T113	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	1		T111	13		T33	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	5		T84	11		T194	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T12	2		T113	8		T86	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	7		T117	1		T213	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	14		T105	9		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T131	9		T205	2		T105	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T112	10		T97	7		T201	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	8		T55	2		T104	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T55	9		T113	10		T195	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T195	7		T154	2		T106	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21908

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3722

1

T10

16

T12

9

T16

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19977

1

T22

1

T24

1

T25

1

auto[1]

5653

1

T10

8

T12

9

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	247	1			T16	1		T17	2		T84	9
values[1]	792	1			T84	26		T55	13		T100	7
values[2]	707	1			T15	2		T20	1		T111	26
values[3]	478	1			T55	10		T113	17		T85	27
values[4]	730	1			T190	1		T85	3		T118	31
values[5]	641	1			T111	26		T95	11		T194	7
values[6]	593	1			T16	4		T20	1		T55	9
values[7]	618	1			T12	9		T13	11		T17	9
values[8]	699	1			T10	8		T84	22		T113	12
values[9]	2888	1			T10	8		T14	3		T19	10
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	650	1			T84	26		T55	13		T100	7
values[1]	719	1			T15	2		T20	1		T111	26
values[2]	684	1			T55	10		T113	17		T85	27
values[3]	656	1			T190	1		T85	3		T104	11
values[4]	620	1			T16	4		T111	26		T95	11
values[5]	536	1			T12	9		T13	11		T20	1
values[6]	2536	1			T14	3		T17	9		T19	10
values[7]	686	1			T10	8		T84	22		T148	10
values[8]	978	1			T10	8		T16	1		T17	2
values[9]	110	1			T20	1		T96	8		T121	21
minimum	17455	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T84	13		T104	13		T215	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T55	11		T100	7		T113	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T15	1		T112	11		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	1		T111	14		T86	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T55	10		T118	25		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T113	9		T85	13		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T85	1		T114	4		T196	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T190	1		T85	1		T104	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T111	12		T95	9		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	3		T194	6		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	11		T55	3		T211	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	7		T20	1		T103	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T14	3		T19	10		T21	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T17	9		T117	3		T99	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T97	8		T195	14		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	6		T84	12		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T16	1		T84	9		T81	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T10	1		T17	1		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T20	1		T96	1		T154	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T121	10		T88	6		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17168	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T199	11		T216	14		T187	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T84	13		T215	13		T109	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T55	2		T113	14		T148	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	1		T112	9		T50	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T111	12		T86	9		T99	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T118	26		T217	8		T119	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T113	8		T85	14		T218	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T114	2		T131	12		T200	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T85	1		T141	16		T200	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T111	14		T95	2		T191	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	1		T194	1		T86	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T55	6		T211	4		T195	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	2		T30	11		T78	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T21	4		T116	6		T92	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T117	1		T99	11		T200	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T97	8		T195	13		T191	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	2		T84	10		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T81	12		T30	1		T194	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T10	7		T17	1		T93	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T96	7		T154	4		T107	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T121	11		T88	2		T199	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T199	2		T216	14		T187	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T16	1		T84	9		T96	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T17	1		T189	1		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T84	13		T104	13		T208	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T55	11		T100	7		T113	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	1		T112	11		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T20	1		T111	14		T86	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T55	10		T118	10		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T113	9		T85	13		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T85	1		T118	15		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T190	1		T85	1		T104	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T111	12		T95	9		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T194	6		T96	1		T195	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T55	3		T195	8		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	3		T20	1		T30	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	11		T21	1		T94	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	7		T17	9		T103	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T113	4		T193	11		T105	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	6		T84	12		T33	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T14	3		T19	10		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T10	1		T93	1		T148	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T96	7		T141	9		T219	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T17	1		T189	12		T121	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T84	13		T215	13		T109	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T55	2		T113	14		T148	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	1		T112	9		T50	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T111	12		T86	9		T99	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T118	10		T217	8		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T113	8		T85	14		T218	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T118	16		T114	2		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T85	1		T141	16		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T111	14		T95	2		T191	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T194	1		T96	18		T195	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T55	6		T195	8		T221	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	1		T30	11		T78	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T21	4		T94	1		T211	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	2		T117	1		T99	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T113	8		T193	10		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	2		T84	10		T33	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T116	6		T92	27		T81	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T10	7		T93	14		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1