Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22329

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3301

1

T10

16

T16

1

T17

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20220

1

T22

1

T24

1

T25

1

auto[1]

5410

1

T12

9

T13

11

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	153	1			T55	10		T114	6		T125	1
values[0]	16	1			T151	1		T255	3		T239	9
values[1]	605	1			T12	9		T20	1		T96	19
values[2]	2416	1			T14	3		T19	10		T53	25
values[3]	839	1			T13	11		T16	1		T21	5
values[4]	627	1			T84	22		T55	9		T148	10
values[5]	731	1			T10	8		T17	9		T190	1
values[6]	632	1			T100	7		T194	23		T96	8
values[7]	720	1			T20	1		T103	1		T113	25
values[8]	633	1			T20	1		T103	1		T113	12
values[9]	1021	1			T10	8		T15	2		T16	4
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	685	1			T12	9		T96	19		T189	14
values[1]	2461	1			T14	3		T16	1		T19	10
values[2]	840	1			T13	11		T21	5		T84	35
values[3]	596	1			T10	8		T84	22		T30	26
values[4]	704	1			T17	9		T190	1		T148	16
values[5]	610	1			T20	1		T100	7		T111	26
values[6]	733	1			T103	1		T113	25		T85	27
values[7]	726	1			T20	1		T103	1		T113	12
values[8]	758	1			T10	8		T15	2		T16	4
values[9]	174	1			T232	12		T218	9		T126	15
minimum	17343	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	7		T96	1		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T189	1		T118	10		T104	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T14	3		T19	10		T53	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	1		T55	11		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	11		T21	1		T84	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T84	9		T113	9		T123	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T30	14		T111	14		T33	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	6		T84	12		T78	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T17	9		T148	8		T123	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T190	1		T148	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T100	7		T194	12		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T20	1		T111	12		T95	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T103	1		T85	13		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T113	11		T199	11		T141	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T117	3		T191	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T20	1		T103	1		T113	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	1		T16	3		T55	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	1		T17	1		T112	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T232	1		T218	5		T126	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T256	1		T295	1		T258	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17152	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T241	3		T130	1		T289	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	2		T96	18		T222	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T189	13		T118	10		T88	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T116	6		T92	27		T81	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T55	2		T46	6		T200	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T21	4		T84	13		T55	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T113	8		T106	3		T219	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T30	12		T111	12		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	2		T84	10		T78	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T148	2		T205	1		T217	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T148	5		T96	7		T97	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T194	11		T195	13		T87	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T111	14		T95	2		T195	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T85	14		T193	10		T189	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T113	14		T199	2		T141	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T117	1		T191	2		T217	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T113	8		T85	1		T86	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	1		T16	1		T93	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	7		T17	1		T112	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T232	11		T218	4		T262	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T256	15		T295	9		T258	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T241	7		T289	2		T296	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T55	10		T125	1		T108	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T114	4		T297	1		T295	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T151	1		T255	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T239	9		T238	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	7		T20	1		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T189	1		T118	10		T104	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T14	3		T19	10		T53	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T55	11		T123	3		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T13	11		T21	1		T84	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	1		T84	9		T113	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	3		T148	8		T30	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T84	12		T78	4		T123	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	9		T86	11		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	6		T190	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T100	7		T194	12		T195	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T96	1		T195	7		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T103	1		T85	13		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	1		T113	11		T111	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T117	3		T191	1		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T20	1		T103	1		T113	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	1		T16	3		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T10	1		T17	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T289	13		T254	4		T298	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T114	2		T297	17		T295	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	2		T96	18		T222	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T189	13		T118	10		T241	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T116	6		T92	27		T101	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T55	2		T88	1		T46	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T21	4		T84	13		T81	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T113	8		T159	2		T252	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T55	6		T148	2		T30	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T84	10		T78	2		T50	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T86	9		T205	1		T217	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	2		T148	5		T194	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T194	11		T195	13		T218	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T96	7		T195	7		T221	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T85	14		T193	10		T189	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T113	14		T111	14		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T117	1		T191	2		T196	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T113	8		T85	1		T86	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	1		T16	1		T93	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T10	7		T17	1		T112	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	7		T96	19		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T189	14		T118	11		T104	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T14	3		T19	1		T53	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T55	3		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	1		T21	5		T84	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T84	1		T113	9		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T30	19		T111	13		T33	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	3		T84	11		T78	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	1		T148	3		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T190	1		T148	6		T96	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T100	1		T194	12		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T20	1		T111	15		T95	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T103	1		T85	15		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T113	15		T199	5		T141	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T117	3		T191	3		T217	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	1		T103	1		T113	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	2		T16	3		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	8		T17	2		T112	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T232	12		T218	5		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T256	16		T295	10		T258	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17259	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T241	8		T130	1		T289	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	2		T222	11		T227	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T118	9		T104	10		T105	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	846	1			T19	9		T53	22		T54	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T55	10		T123	2		T200	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	10		T84	12		T55	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T84	8		T113	8		T123	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T30	7		T111	13		T33	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T10	5		T84	11		T194	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T17	8		T148	7		T123	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T97	7		T131	14		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T100	6		T194	11		T195	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T111	11		T95	5		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T85	12		T193	10		T211	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T113	10		T199	8		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T117	1		T119	18		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T113	3		T154	2		T122	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	1		T55	9		T139	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T112	10		T195	7		T104	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T218	4		T126	14		T262	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T258	13		T259	13		T299	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T213	9		T205	2		T207	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T241	2		T278	9		T298	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T55	1		T125	1		T108	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T114	5		T297	18		T295	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T151	1		T255	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T239	1		T238	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	7		T20	1		T96	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T189	14		T118	11		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T14	3		T19	1		T53	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T55	3		T123	1		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	1		T21	5		T84	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	1		T84	1		T113	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T55	7		T148	3		T30	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T84	11		T78	6		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T17	1		T86	10		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	3		T190	1		T148	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T100	1		T194	12		T195	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T96	8		T195	8		T221	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T103	1		T85	15		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	1		T113	15		T111	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T117	3		T191	3		T196	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	1		T103	1		T113	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T15	2		T16	3		T93	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T10	8		T17	2		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T55	9		T251	11		T254	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T114	1		T300	10		T259	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T239	8		T238	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	2		T213	9		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T118	9		T104	10		T105	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	821	1			T19	9		T53	22		T54	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T55	10		T123	2		T200	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	10		T84	12		T81	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T84	8		T113	8		T196	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T55	2		T148	7		T30	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T84	11		T123	13		T208	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T17	8		T86	10		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	5		T194	5		T97	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T100	6		T194	11		T195	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T195	6		T106	1		T126	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T85	12		T193	10		T211	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T113	10		T111	11		T95	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T117	1		T200	13		T105	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T113	3		T154	2		T199	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	1		T139	1		T119	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T112	10		T195	7		T104	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10