Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22514

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3116

1

T10

8

T13

11

T16

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20061

1

T22

1

T24

1

T25

1

auto[1]

5569

1

T12

9

T14

3

T16

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	276	1			T84	22		T55	22		T208	20
values[0]	21	1			T105	10		T308	11		-	-
values[1]	663	1			T12	9		T20	1		T30	26
values[2]	690	1			T10	8		T20	1		T21	5
values[3]	748	1			T17	9		T84	26		T103	1
values[4]	664	1			T113	12		T148	10		T111	26
values[5]	2473	1			T13	11		T14	3		T17	2
values[6]	600	1			T10	8		T15	2		T16	5
values[7]	649	1			T113	25		T111	26		T95	1
values[8]	723	1			T84	9		T100	7		T78	6
values[9]	886	1			T81	23		T194	23		T97	1
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	683	1			T12	9		T20	2		T30	24
values[1]	669	1			T10	8		T21	5		T93	15
values[2]	827	1			T17	9		T84	26		T103	1
values[3]	2406	1			T14	3		T19	10		T53	25
values[4]	693	1			T13	11		T15	2		T16	1
values[5]	491	1			T10	8		T16	4		T190	1
values[6]	735	1			T113	25		T111	26		T95	1
values[7]	710	1			T84	9		T100	7		T78	6
values[8]	889	1			T84	22		T55	13		T81	23
values[9]	115	1			T55	9		T191	12		T119	8
minimum	17412	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	7		T20	1		T30	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T20	1		T86	11		T193	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	6		T21	1		T195	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T93	1		T113	9		T94	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T17	9		T113	4		T85	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T84	13		T103	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T14	3		T19	10		T53	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T111	14		T85	1		T97	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	1		T17	1		T20	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	11		T16	1		T55	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T190	1		T33	5		T95	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	1		T16	3		T195	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T95	1		T112	11		T213	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T113	11		T111	12		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T84	9		T100	7		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T78	4		T200	16		T221	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T55	11		T194	12		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T84	12		T81	11		T104	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T191	1		T119	8		T262	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T55	3		T246	1		T110	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17143	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T204	2		T114	4		T105	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	2		T30	11		T211	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T86	9		T193	10		T191	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	2		T21	4		T195	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T93	14		T113	8		T94	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T113	8		T85	14		T189	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T84	13		T96	7		T118	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T116	6		T92	27		T101	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T111	12		T85	1		T97	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	1		T17	1		T194	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T99	14		T191	2		T131	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T33	3		T95	2		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T10	7		T16	1		T195	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T112	9		T200	11		T106	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T113	14		T111	14		T86	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T119	2		T215	13		T107	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T78	2		T200	2		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T55	2		T194	11		T218	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T84	10		T81	12		T199	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T191	11		T262	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T55	6		T210	11		T146	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T114	2		T106	10		T264	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T55	11		T119	8		T220	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T84	12		T55	3		T208	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T308	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T105	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	7		T30	14		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	1		T86	11		T193	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	6		T20	1		T21	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T93	1		T94	6		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	9		T189	1		T154	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T84	13		T103	1		T113	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T113	4		T148	8		T85	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T111	14		T85	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T14	3		T17	1		T19	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	11		T55	10		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	1		T20	1		T190	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	1		T16	4		T99	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T95	1		T112	11		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T113	11		T111	12		T104	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T84	9		T100	7		T200	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T78	4		T86	1		T117	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T194	12		T97	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T81	11		T104	13		T123	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T55	2		T220	10		T257	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T84	10		T55	6		T109	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T308	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	2		T30	12		T121	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T86	9		T193	10		T114	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	2		T21	4		T195	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T93	14		T94	1		T96	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T189	12		T154	4		T196	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T84	13		T113	8		T96	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T113	8		T148	2		T85	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T111	12		T85	1		T46	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T17	1		T116	6		T92	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T97	8		T191	2		T131	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	1		T33	3		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T10	7		T16	1		T99	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T112	9		T106	3		T207	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T113	14		T111	14		T205	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T200	11		T119	2		T215	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T78	2		T86	3		T117	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T194	11		T191	11		T218	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T81	12		T199	1		T90	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	7		T20	1		T30	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	1		T86	10		T193	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T10	3		T21	5		T195	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T93	15		T113	9		T94	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T17	1		T113	9		T85	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T84	14		T103	1		T96	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T14	3		T19	1		T53	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T111	13		T85	2		T97	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	2		T17	2		T20	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	1		T16	1		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T190	1		T33	4		T95	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	8		T16	3		T195	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T95	1		T112	10		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T113	15		T111	15		T86	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T84	1		T100	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T78	6		T200	3		T221	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T55	3		T194	12		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T84	11		T81	13		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T191	12		T119	1		T262	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T55	7		T246	1		T110	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17300	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T204	2		T114	5		T105	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	2		T30	7		T211	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T86	10		T193	10		T104	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	5		T195	20		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T113	8		T94	2		T240	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	8		T113	3		T85	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T84	12		T118	9		T122	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	815	1			T19	9		T53	22		T54	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T111	13		T97	7		T227	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T194	5		T99	12		T118	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	10		T55	9		T99	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T33	4		T95	5		T139	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T16	1		T195	6		T123	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T112	10		T213	9		T200	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T113	10		T111	11		T117	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T84	8		T100	6		T119	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T200	15		T221	9		T107	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	10		T194	11		T218	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T84	11		T81	10		T104	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T119	7		T262	6		T309	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T55	2		T210	6		T251	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T121	9		T252	13		T310	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T114	1		T105	9		T106	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T55	3		T119	1		T220	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T84	11		T55	7		T208	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T308	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T105	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	7		T30	19		T121	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	1		T86	10		T193	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T10	3		T20	1		T21	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T93	15		T94	5		T96	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	1		T189	13		T154	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T84	14		T103	1		T113	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T113	9		T148	3		T85	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T111	13		T85	2		T46	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T14	3		T17	2		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	1		T55	1		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	2		T20	1		T190	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	8		T16	4		T99	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T95	1		T112	10		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T113	15		T111	15		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T84	1		T100	1		T200	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T78	6		T86	4		T117	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T194	12		T97	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T81	13		T104	1		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T55	10		T119	7		T257	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T84	11		T55	2		T208	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T105	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	2		T30	7		T121	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T86	10		T193	10		T104	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	5		T195	20		T131	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T94	2		T240	11		T168	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	8		T154	2		T196	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T84	12		T113	8		T118	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T113	3		T148	7		T85	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T111	13		T205	2		T222	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	875	1			T19	9		T53	22		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	10		T55	9		T97	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	4		T139	1		T99	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T16	1		T99	12		T195	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T112	10		T213	9		T106	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T113	10		T111	11		T104	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T84	8		T100	6		T200	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T117	1		T200	15		T107	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T194	11		T218	4		T107	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T81	10		T104	12		T123	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10