Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21806

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3824

1

T10

8

T15

2

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20086

1

T22

1

T24

1

T25

1

auto[1]

5544

1

T10

8

T13

11

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	248	1			T12	9		T20	1		T113	25
values[0]	46	1			T96	8		T199	2		T219	30
values[1]	537	1			T20	1		T84	22		T55	9
values[2]	627	1			T10	8		T15	2		T55	13
values[3]	610	1			T13	11		T17	9		T20	1
values[4]	708	1			T10	8		T84	26		T113	17
values[5]	722	1			T16	4		T21	5		T30	2
values[6]	789	1			T190	1		T148	10		T95	11
values[7]	548	1			T100	7		T113	12		T111	26
values[8]	2550	1			T14	3		T19	10		T53	25
values[9]	1008	1			T16	1		T17	2		T84	9
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	537	1			T15	2		T20	1		T84	22
values[1]	707	1			T10	8		T13	11		T55	13
values[2]	494	1			T17	9		T20	1		T103	1
values[3]	777	1			T10	8		T16	4		T21	5
values[4]	848	1			T193	21		T99	24		T204	1
values[5]	667	1			T190	1		T100	7		T148	10
values[6]	2371	1			T14	3		T19	10		T53	25
values[7]	720	1			T103	1		T194	7		T211	10
values[8]	930	1			T12	9		T16	1		T17	2
values[9]	171	1			T55	10		T195	16		T104	13
minimum	17408	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T84	12		T98	1		T195	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	1		T20	1		T55	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	6		T13	11		T51	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T55	11		T30	13		T112	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T17	9		T20	1		T113	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T103	1		T85	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T16	3		T97	8		T99	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	1		T21	1		T84	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	1		T124	1		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T193	11		T99	13		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T190	1		T100	7		T194	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T148	8		T95	9		T86	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T14	3		T19	10		T53	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T111	26		T85	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T103	1		T211	6		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T194	6		T195	14		T104	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	7		T84	9		T81	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T16	1		T17	1		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T55	10		T104	13		T200	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T195	8		T221	1		T306	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17129	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T191	1		T214	12		T219	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T84	10		T195	7		T200	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	1		T55	6		T93	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	2		T214	10		T120	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T55	2		T30	11		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T113	8		T33	3		T78	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T218	13		T219	6		T240	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	1		T97	8		T99	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	7		T21	4		T84	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	12		T131	12		T141	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T193	10		T99	11		T46	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T194	11		T191	2		T90	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T148	2		T95	2		T86	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T116	6		T92	27		T101	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T111	26		T85	1		T217	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T211	4		T196	2		T218	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T194	1		T195	13		T221	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	2		T81	12		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T17	1		T85	14		T96	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T200	2		T311	13		T294	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T195	8		T221	15		T306	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T191	11		T214	12		T219	21

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T12	7		T113	11		T154	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T20	1		T121	10		T195	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T96	1		T199	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T219	9		T153	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T84	12		T98	1		T200	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T20	1		T55	3		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	6		T195	7		T51	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	1		T55	11		T30	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	11		T17	9		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T103	1		T85	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T113	9		T97	8		T99	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	1		T84	13		T94	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T16	3		T104	13		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T21	1		T30	1		T193	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T190	1		T194	12		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T148	8		T95	9		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T100	7		T113	4		T201	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T111	12		T86	11		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1142	1			T14	3		T19	10		T53	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T111	14		T85	1		T194	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T84	9		T55	10		T81	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T16	1		T17	1		T85	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T12	2		T113	14		T154	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T121	11		T195	8		T191	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T96	7		T199	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T219	21		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T84	10		T200	11		T264	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T55	6		T93	14		T87	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T10	2		T195	7		T214	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T55	2		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T33	3		T78	2		T50	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T86	3		T119	18		T207	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T113	8		T97	8		T99	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	7		T84	13		T94	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	1		T50	12		T131	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	4		T30	1		T193	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T194	11		T191	2		T90	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T148	2		T95	2		T189	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T113	8		T201	2		T50	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T111	14		T86	9		T189	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T116	6		T92	27		T101	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T111	12		T85	1		T194	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T81	12		T148	5		T117	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T17	1		T85	14		T96	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T84	11		T98	1		T195	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T15	2		T20	1		T55	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	3		T13	1		T51	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T55	3		T30	17		T112	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T17	1		T20	1		T113	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T103	1		T85	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	3		T97	9		T99	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T10	8		T21	5		T84	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T50	13		T124	1		T131	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T193	11		T99	12		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T190	1		T100	1		T194	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T148	3		T95	6		T86	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T14	3		T19	1		T53	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T111	28		T85	2		T217	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T103	1		T211	5		T196	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T194	2		T195	14		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	7		T84	1		T81	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T16	1		T17	2		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T55	1		T104	1		T200	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T195	9		T221	16		T306	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17282	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T191	12		T214	13		T219	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T84	11		T195	6		T200	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T55	2		T199	8		T196	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	5		T13	10		T214	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T55	10		T30	7		T112	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T17	8		T113	8		T33	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T105	16		T218	12		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	1		T97	7		T99	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T84	12		T94	2		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T131	9		T141	2		T105	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T193	10		T99	12		T213	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T100	6		T194	11		T212	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	7		T95	5		T86	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	823	1			T19	9		T53	22		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T111	24		T200	13		T235	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T211	5		T218	4		T107	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T194	5		T195	13		T104	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	2		T84	8		T81	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T85	12		T121	9		T122	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T55	9		T104	12		T200	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T195	7		T306	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T300	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T214	11		T219	8		T301	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	7		T113	15		T154	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T20	1		T121	12		T195	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T96	8		T199	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T219	22		T153	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T84	11		T98	1		T200	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T20	1		T55	7		T93	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	3		T195	8		T51	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	2		T55	3		T30	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	1		T17	1		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T103	1		T85	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T113	9		T97	9		T99	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	8		T84	14		T94	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T16	3		T104	1		T50	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T21	5		T30	2		T193	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T190	1		T194	12		T191	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T148	3		T95	6		T189	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T100	1		T113	9		T201	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T111	15		T86	10		T189	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T14	3		T19	1		T53	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T111	13		T85	2		T194	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T84	1		T55	1		T81	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T16	1		T17	2		T85	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T12	2		T113	10		T154	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T121	9		T195	7		T306	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T219	8		T153	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T84	11		T200	4		T107	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T55	2		T199	8		T196	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	5		T195	6		T214	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T55	10		T30	7		T112	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	10		T17	8		T33	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T105	16		T119	18		T207	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T113	8		T97	7		T99	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T84	12		T94	2		T122	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T16	1		T104	12		T131	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T193	10		T222	10		T227	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T194	11		T106	9		T126	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T148	7		T95	5		T99	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T100	6		T113	3		T201	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T111	11		T86	10		T200	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	811	1			T19	9		T53	22		T54	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T111	13		T194	5		T195	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T84	8		T55	9		T81	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T85	12		T122	14		T227	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10