Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20326

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

5304

1

T10

8

T14

3

T16

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19996

1

T22

1

T24

1

T25

1

auto[1]

5634

1

T10

16

T14

3

T16

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	304	1			T17	9		T30	24		T194	7
values[0]	22	1			T126	3		T301	17		T302	2
values[1]	699	1			T16	1		T20	1		T21	5
values[2]	679	1			T81	23		T113	25		T111	26
values[3]	646	1			T84	22		T111	26		T33	8
values[4]	607	1			T12	9		T17	2		T103	1
values[5]	738	1			T13	11		T16	4		T20	1
values[6]	669	1			T20	1		T103	1		T118	20
values[7]	615	1			T84	9		T190	1		T93	15
values[8]	579	1			T10	8		T85	2		T112	20
values[9]	2835	1			T10	8		T14	3		T15	2
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	766	1			T20	1		T21	5		T55	19
values[1]	2440	1			T14	3		T19	10		T53	25
values[2]	589	1			T84	22		T85	27		T78	6
values[3]	630	1			T12	9		T13	11		T17	2
values[4]	915	1			T16	4		T20	1		T84	26
values[5]	541	1			T20	1		T103	1		T85	1
values[6]	579	1			T84	9		T190	1		T93	15
values[7]	706	1			T10	16		T85	2		T112	20
values[8]	986	1			T15	2		T17	9		T55	13
values[9]	75	1			T104	13		T125	1		T218	9
minimum	17403	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T20	1		T55	3		T113	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T21	1		T55	10		T94	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T33	5		T195	8		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1191	1			T14	3		T19	10		T53	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T78	4		T284	1		T221	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T84	12		T85	13		T95	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	7		T13	11		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T103	1		T113	4		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T20	1		T84	13		T86	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	3		T211	6		T195	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T20	1		T103	1		T118	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T85	1		T96	1		T139	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T190	1		T204	1		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T84	9		T93	1		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	6		T85	1		T112	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	1		T114	4		T201	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T15	1		T55	11		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T17	9		T100	7		T30	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T265	3		T175	1		T206	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T104	13		T125	1		T218	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17164	1			T11	148		T12	1		T16	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T205	1		T214	13		T305	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T55	6		T113	8		T111	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T21	4		T94	1		T96	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T33	3		T195	8		T221	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1033	1			T116	6		T92	27		T81	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T78	2		T221	10		T241	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T84	10		T85	14		T95	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	2		T17	1		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T113	8		T30	1		T106	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T84	13		T86	3		T117	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T16	1		T211	4		T195	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T118	10		T131	12		T264	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T96	18		T139	2		T189	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T191	14		T199	1		T221	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T93	14		T118	16		T88	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	2		T85	1		T112	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	7		T114	2		T201	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	1		T55	2		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T30	11		T194	1		T121	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T265	12		T206	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T218	4		T267	2		T312	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T205	1		T214	10		T305	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T200	16		T212	20		T109	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T17	9		T30	13		T194	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T301	17		T302	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T126	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	1		T20	1		T55	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T21	1		T55	10		T94	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T111	14		T97	8		T195	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T81	11		T113	11		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T33	5		T78	4		T221	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T84	12		T111	12		T85	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	7		T17	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T103	1		T113	4		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	11		T20	1		T84	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	3		T211	6		T195	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T20	1		T103	1		T118	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T207	1		T108	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T190	1		T204	1		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T84	9		T93	1		T85	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	6		T85	1		T112	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T114	4		T213	10		T122	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	1		T55	11		T148	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1356	1			T10	1		T14	3		T19	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T200	2		T212	19		T109	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T30	11		T194	1		T121	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T302	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T55	6		T113	8		T235	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	4		T94	1		T193	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T111	12		T97	8		T195	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T81	12		T113	14		T96	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T33	3		T78	2		T221	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T84	10		T111	14		T85	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	2		T17	1		T148	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T113	8		T30	1		T106	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T84	13		T86	3		T117	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	1		T211	4		T195	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T118	10		T141	9		T264	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T220	10		T257	11		T303	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T191	14		T131	12		T221	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T93	14		T96	18		T139	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	2		T85	1		T112	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T114	2		T304	17		T257	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	1		T55	2		T148	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1097	1			T10	7		T116	6		T92	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	1		T55	7		T113	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T21	5		T55	1		T94	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	4		T195	9		T221	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1352	1			T14	3		T19	1		T53	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T78	6		T284	1		T221	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T84	11		T85	15		T95	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	7		T13	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T103	1		T113	9		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T20	1		T84	14		T86	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T16	3		T211	5		T195	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T20	1		T103	1		T118	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T85	1		T96	19		T139	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T190	1		T204	1		T191	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T84	1		T93	15		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T10	3		T85	2		T112	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	8		T114	5		T201	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	2		T55	3		T148	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T17	1		T100	1		T30	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T265	13		T175	1		T206	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T104	1		T125	1		T218	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17275	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T205	2		T214	11		T305	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T55	2		T113	8		T111	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T55	9		T94	2		T193	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T33	4		T195	7		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	872	1			T19	9		T53	22		T54	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T221	9		T241	2		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T84	11		T85	12		T95	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	2		T13	10		T99	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T113	3		T208	19		T106	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T84	12		T117	1		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	1		T211	5		T195	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T118	9		T104	10		T123	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T139	1		T305	9		T292	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T105	9		T235	15		T150	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T84	8		T118	14		T88	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	5		T112	10		T194	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T114	1		T201	6		T199	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T55	10		T148	7		T122	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T17	8		T100	6		T30	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T265	2		T206	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T104	12		T218	4		T312	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T242	11		T286	10		T145	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T214	12		T305	10		T313	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T200	3		T212	20		T109	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T17	1		T30	17		T194	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T301	1		T302	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T126	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	1		T20	1		T55	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T21	5		T55	1		T94	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T111	13		T97	9		T195	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T81	13		T113	15		T96	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T33	4		T78	6		T221	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T84	11		T111	15		T85	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	7		T17	2		T148	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T103	1		T113	9		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	1		T20	1		T84	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T16	3		T211	5		T195	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T20	1		T103	1		T118	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T207	1		T108	1		T220	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T190	1		T204	1		T191	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T84	1		T93	15		T85	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	3		T85	2		T112	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T114	5		T213	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	2		T55	3		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1440	1			T10	8		T14	3		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T200	15		T212	19		T109	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T17	8		T30	7		T194	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T301	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T126	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T55	2		T113	8		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T55	9		T94	2		T193	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T111	13		T97	7		T195	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T81	10		T113	10		T131	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T33	4		T221	9		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T84	11		T111	11		T85	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T12	2		T99	12		T123	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T113	3		T208	19		T106	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	10		T84	12		T117	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T16	1		T211	5		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T118	9		T104	10		T123	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T257	10		T303	13		T305	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T131	9		T105	9		T235	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T84	8		T139	1		T118	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	5		T112	10		T194	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T114	1		T213	9		T122	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T55	10		T148	7		T99	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1013	1			T19	9		T53	22		T54	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10