Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22254

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3376

1

T10

8

T12

9

T13

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20179

1

T22

1

T24

1

T25

1

auto[1]

5451

1

T10

8

T14

3

T17

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	264	1			T84	26		T113	17		T94	7
values[0]	71	1			T205	3		T283	3		T314	13
values[1]	751	1			T12	9		T20	1		T21	5
values[2]	657	1			T84	22		T30	2		T98	1
values[3]	654	1			T17	9		T148	10		T85	1
values[4]	612	1			T10	8		T93	15		T112	20
values[5]	2618	1			T10	8		T14	3		T19	10
values[6]	596	1			T13	11		T15	2		T16	4
values[7]	551	1			T17	2		T20	1		T113	12
values[8]	744	1			T84	9		T81	23		T118	31
values[9]	875	1			T16	1		T190	1		T100	7
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	701	1			T12	9		T20	1		T21	5
values[1]	583	1			T17	9		T30	2		T189	14
values[2]	767	1			T93	15		T148	10		T85	1
values[3]	2517	1			T10	8		T14	3		T19	10
values[4]	592	1			T10	8		T16	4		T20	1
values[5]	564	1			T13	11		T15	2		T17	2
values[6]	702	1			T20	1		T81	23		T113	12
values[7]	675	1			T84	9		T86	20		T97	16
values[8]	838	1			T16	1		T84	26		T190	1
values[9]	160	1			T113	17		T94	7		T95	11
minimum	17531	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	1		T55	10		T113	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	7		T20	1		T84	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	9		T30	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T189	1		T211	6		T196	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T112	11		T139	7		T104	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T93	1		T148	8		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T10	1		T14	3		T19	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T104	24		T191	1		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T55	11		T117	3		T123	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	6		T16	3		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T85	13		T96	1		T195	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	11		T15	1		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T20	1		T81	11		T33	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T113	4		T193	11		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T84	9		T97	8		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T86	11		T118	15		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T16	1		T84	13		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T190	1		T100	7		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T113	9		T94	6		T95	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T96	1		T286	6		T290	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T99	13		T205	3		T159	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T21	4		T113	14		T86	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	2		T84	10		T141	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T30	1		T201	2		T264	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T189	13		T211	4		T196	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T112	9		T139	2		T191	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T93	14		T148	2		T195	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T10	7		T116	6		T92	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T191	11		T131	14		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T55	2		T117	1		T205	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	2		T16	1		T55	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T85	14		T96	18		T195	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T15	1		T17	1		T78	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T81	12		T33	3		T200	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T113	8		T193	10		T212	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T97	8		T88	1		T131	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T86	9		T118	16		T199	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T84	13		T111	12		T121	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T148	5		T114	2		T199	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T113	8		T94	1		T95	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T96	7		T290	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T99	11		T159	15		T267	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T84	13		T113	9		T94	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T124	1		T207	18		T286	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T145	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T205	3		T283	3		T314	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T21	1		T55	10		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	7		T20	1		T99	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	1		T98	1		T201	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T84	12		T211	6		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T17	9		T139	7		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T148	8		T85	1		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	1		T112	11		T194	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T93	1		T195	8		T104	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T14	3		T19	10		T53	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	6		T20	1		T55	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T85	13		T96	1		T117	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	11		T15	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T20	1		T33	5		T123	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	1		T113	4		T193	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T84	9		T81	11		T122	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T118	15		T199	11		T208	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T16	1		T103	1		T111	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T190	1		T100	7		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T84	13		T113	8		T94	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T207	18		T315	1		T202	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T145	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T314	3		T273	10		T299	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T21	4		T113	14		T86	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	2		T99	11		T141	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T30	1		T201	2		T264	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T84	10		T211	4		T196	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T139	2		T191	2		T218	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T148	2		T189	13		T195	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	7		T112	9		T194	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T93	14		T195	8		T88	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	898	1			T116	6		T92	27		T55	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	2		T55	6		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T85	14		T96	18		T117	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	1		T16	1		T78	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T33	3		T200	2		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T17	1		T113	8		T193	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T81	12		T131	10		T217	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T118	16		T199	2		T221	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T111	12		T95	2		T97	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T148	5		T86	9		T96	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T21	5		T55	1		T113	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	7		T20	1		T84	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T17	1		T30	2		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T189	14		T211	5		T196	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T112	10		T139	8		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T93	15		T148	3		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T10	8		T14	3		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T104	2		T191	12		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T55	3		T117	3		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	3		T16	3		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T85	15		T96	19		T195	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	1		T15	2		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T20	1		T81	13		T33	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T113	9		T193	11		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T84	1		T97	9		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T86	10		T118	17		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T16	1		T84	14		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T190	1		T100	1		T148	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T113	9		T94	5		T95	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T96	8		T286	1		T290	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17301	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T99	12		T205	1		T159	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T55	9		T113	10		T244	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	2		T84	11		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T17	8		T201	6		T159	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T211	5		T240	5		T109	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T112	10		T139	1		T104	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	7		T195	20		T123	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T19	9		T53	22		T54	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T104	22		T131	14		T200	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T55	10		T117	1		T123	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	5		T16	1		T55	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T85	12		T195	6		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	10		T213	9		T131	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T81	10		T33	4		T123	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T113	3		T193	10		T212	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T84	8		T97	7		T122	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T86	10		T118	14		T199	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T84	12		T111	13		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T100	6		T114	1		T207	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T113	8		T94	2		T95	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T286	5		T290	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T219	5		T243	9		T316	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T99	12		T205	2		T159	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T84	14		T113	9		T94	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T124	1		T207	20		T286	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T145	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T205	1		T283	1		T314	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T21	5		T55	1		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	7		T20	1		T99	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T30	2		T98	1		T201	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T84	11		T211	5		T196	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T17	1		T139	8		T191	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T148	3		T85	1		T189	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	8		T112	10		T194	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T93	15		T195	9		T104	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T14	3		T19	1		T53	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T10	3		T20	1		T55	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T85	15		T96	19		T117	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	1		T15	2		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T20	1		T33	4		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	2		T113	9		T193	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T84	1		T81	13		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T118	17		T199	5		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T16	1		T103	1		T111	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T190	1		T100	1		T148	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T84	12		T113	8		T94	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T207	16		T286	5		T315	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T145	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T205	2		T283	2		T314	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T55	9		T113	10		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	2		T99	12		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T201	6		T265	2		T262	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T84	11		T211	5		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T17	8		T139	1		T218	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	7		T195	13		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T112	10		T194	16		T104	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T195	7		T104	22		T123	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T19	9		T53	22		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	5		T55	2		T30	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T85	12		T117	1		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	10		T16	1		T213	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T33	4		T123	2		T200	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T113	3		T193	10		T219	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T84	8		T81	10		T122	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T118	14		T199	8		T208	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T111	13		T95	5		T97	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T100	6		T86	10		T114	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10