Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1		T84	14	T104	1	T215	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1		T55	3	T100	1	T113	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1		T15	2	T112	10	T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1		T20	1	T111	13	T86	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1		T55	1	T118	28	T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1		T113	9	T85	15	T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1		T85	1	T114	5	T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1		T190	1	T85	2	T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1		T111	15	T95	6	T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1		T16	3	T194	2	T86	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1		T13	1	T55	7	T211	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1		T12	7	T20	1	T103	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1		T14	3	T19	1	T21	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1		T17	1	T117	3	T99	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1		T97	9	T195	14	T191	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1		T10	3	T84	11	T148	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1		T16	1	T84	1	T81	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1		T10	8	T17	2	T93	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1		T20	1	T96	8	T154	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1		T121	12	T88	7	T199	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17267	1		T22	1	T24	1	T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1		T199	5	T216	15	T187	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1		T84	12	T104	12	T215	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1		T55	10	T100	6	T113	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1		T112	10	T106	9	T152	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1		T111	13	T86	10	T99	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1		T55	9	T118	23	T119	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1		T113	8	T85	12	T213	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1		T114	1	T196	5	T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1		T104	10	T122	14	T141	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1		T111	11	T95	5	T210	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1		T16	1	T194	5	T195	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1		T13	10	T55	2	T211	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1		T12	2	T30	7	T207	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	828	1		T19	9	T53	22	T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1		T17	8	T117	1	T99	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1		T97	7	T195	13	T201	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1		T10	5	T84	11	T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1		T84	8	T81	10	T194	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1		T123	13	T105	16	T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1		T154	2	T107	4	T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1		T121	9	T88	1	T224	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1		T208	19	T205	2	T210	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1		T199	8	T216	13	T187	10

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1		T16	1	T84	1	T96	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1		T17	2	T189	13	T121	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1		T84	14	T104	1	T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1		T55	3	T100	1	T113	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1		T15	2	T112	10	T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1		T20	1	T111	13	T86	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1		T55	1	T118	11	T217	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1		T113	9	T85	15	T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1		T85	1	T118	17	T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1		T190	1	T85	2	T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1		T111	15	T95	6	T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1		T194	2	T96	19	T195	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1		T55	7	T195	9	T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1		T16	3	T20	1	T30	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1		T13	1	T21	5	T94	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1		T12	7	T17	1	T103	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1		T113	9	T193	11	T105	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1		T10	3	T84	11	T33	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1		T14	3	T19	1	T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1		T10	8	T93	15	T148	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1		T22	1	T24	1	T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1		T84	8	T219	8	T225	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1		T121	9	T226	10	T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1		T84	12	T104	12	T208	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1		T55	10	T100	6	T113	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1		T112	10	T106	9	T175	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1		T111	13	T86	10	T99	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1		T55	9	T118	9	T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1		T113	8	T85	12	T213	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1		T118	14	T114	1	T209	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1		T104	10	T141	2	T200	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1		T111	11	T95	5	T196	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1		T194	5	T195	6	T122	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1		T55	2	T195	7	T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1		T16	1	T30	7	T119	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1		T13	10	T94	2	T211	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1		T12	2	T17	8	T117	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1		T113	3	T193	10	T105	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1		T10	5	T84	11	T33	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	934	1		T19	9	T53	22	T54	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1		T148	7	T123	13	T88	1

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

T22

T24

T25

auto[1]

auto[0]

3530

T10

T12

T13