Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22086

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3544

1

T10

16

T13

11

T15

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19841

1

T22

1

T24

1

T25

1

auto[1]

5789

1

T11

2

T12

9

T13

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	586	1			T11	2		T15	2		T16	6
values[0]	6	1			T188	6		-	-		-	-
values[1]	737	1			T55	13		T148	10		T94	7
values[2]	2575	1			T14	3		T17	2		T19	10
values[3]	745	1			T84	26		T93	15		T189	13
values[4]	658	1			T13	11		T190	1		T113	12
values[5]	685	1			T10	8		T16	5		T84	22
values[6]	644	1			T12	9		T113	17		T30	24
values[7]	819	1			T10	8		T97	16		T189	14
values[8]	738	1			T17	9		T21	5		T55	9
values[9]	628	1			T55	10		T103	1		T113	25
minimum	16809	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	780	1			T55	13		T100	7		T148	10
values[1]	2597	1			T14	3		T17	2		T19	10
values[2]	566	1			T93	15		T113	12		T85	1
values[3]	724	1			T13	11		T190	1		T85	27
values[4]	761	1			T10	8		T12	9		T16	5
values[5]	659	1			T10	8		T113	17		T30	24
values[6]	843	1			T97	16		T189	14		T123	3
values[7]	594	1			T17	9		T21	5		T55	19
values[8]	663	1			T20	1		T103	1		T95	1
values[9]	16	1			T15	2		T126	3		T127	1
minimum	17427	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T100	7		T148	8		T95	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T55	11		T193	11		T99	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T14	3		T17	1		T19	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	2		T84	22		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T85	1		T189	1		T123	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T93	1		T113	4		T121	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T85	13		T86	1		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	11		T190	1		T194	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	7		T16	4		T33	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	6		T84	12		T81	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T113	9		T194	6		T104	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	1		T30	13		T117	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T97	8		T189	1		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T123	3		T90	1		T131	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T21	1		T55	3		T113	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	9		T55	10		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T103	1		T115	1		T201	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T20	1		T95	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T127	1		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T15	1		T126	3		T228	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17156	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T118	15		T221	3		T156	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T148	2		T95	2		T141	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T55	2		T193	10		T99	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T17	1		T116	6		T92	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T84	13		T96	18		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T189	12		T50	12		T155	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T93	14		T113	8		T121	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T85	14		T86	3		T211	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T194	11		T139	2		T191	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	2		T16	1		T33	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	2		T84	10		T81	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T113	8		T194	1		T191	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	7		T30	11		T117	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T97	8		T189	13		T88	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T90	7		T131	12		T221	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T21	4		T55	6		T113	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T148	5		T199	1		T218	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T201	2		T89	9		T218	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T96	7		T195	8		T154	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T15	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T118	16		T221	15		T156	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	462	1			T11	2		T16	6		T30	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T15	1		T20	1		T195	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T188	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T148	8		T94	6		T95	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T55	11		T193	11		T118	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T14	3		T17	1		T19	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T20	2		T84	9		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T189	1		T99	13		T123	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T84	13		T93	1		T121	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T85	14		T86	1		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	11		T190	1		T113	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T16	4		T33	5		T194	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	6		T84	12		T81	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	7		T113	9		T78	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	13		T86	11		T117	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T97	8		T189	1		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	1		T122	9		T131	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T21	1		T55	3		T112	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	9		T103	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T103	1		T113	11		T195	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T55	10		T95	1		T96	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16683	1			T11	146		T12	1		T16	74
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T109	6		T229	2		T230	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T15	1		T195	8		T231	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T188	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T148	2		T94	1		T95	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T55	2		T193	10		T118	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T17	1		T116	6		T92	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T96	18		T99	14		T199	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T189	12		T99	11		T50	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T84	13		T93	14		T121	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T85	14		T86	3		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T113	8		T139	2		T114	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	1		T33	3		T194	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	2		T84	10		T81	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	2		T113	8		T78	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T30	11		T86	9		T117	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T97	8		T189	13		T196	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	7		T131	12		T221	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T21	4		T55	6		T112	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T148	5		T199	1		T90	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T113	14		T195	7		T89	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T96	7		T154	4		T200	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T100	1		T148	3		T95	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T55	3		T193	11		T99	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T14	3		T17	2		T19	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T20	2		T84	15		T96	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T85	1		T189	13		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T93	15		T113	9		T121	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T85	15		T86	4		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	1		T190	1		T194	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	7		T16	4		T33	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	3		T84	11		T81	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T113	9		T194	2		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	8		T30	17		T117	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T97	9		T189	14		T88	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T123	1		T90	8		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T21	5		T55	7		T113	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	1		T55	1		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T103	1		T115	1		T201	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	1		T95	1		T96	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T127	1		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T15	2		T126	1		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17278	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T118	17		T221	16		T156	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T100	6		T148	7		T95	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	10		T193	10		T99	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	879	1			T19	9		T53	22		T54	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T84	20		T104	12		T199	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T123	1		T208	19		T155	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T113	3		T121	9		T114	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T85	12		T211	5		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	10		T194	11		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	2		T16	1		T33	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	5		T84	11		T81	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T113	8		T194	5		T104	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	7		T117	1		T195	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T97	7		T196	5		T105	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T123	2		T131	9		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T55	2		T113	10		T112	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	8		T55	9		T104	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T201	6		T119	7		T218	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T195	7		T154	2		T200	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T126	2		T228	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T94	2		T221	9		T153	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T118	14		T221	2		T234	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	467	1			T11	2		T16	6		T30	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T15	2		T20	1		T195	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T188	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T148	3		T94	5		T95	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T55	3		T193	11		T118	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T14	3		T17	2		T19	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	2		T84	1		T96	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T189	13		T99	12		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T84	14		T93	15		T121	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T85	16		T86	4		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	1		T190	1		T113	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T16	4		T33	4		T194	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	3		T84	11		T81	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	7		T113	9		T78	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	17		T86	10		T117	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T97	9		T189	14		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	8		T122	1		T131	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	5		T55	7		T112	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	1		T103	1		T148	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T103	1		T113	15		T195	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T55	1		T95	1		T96	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16809	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T109	6		T229	2		T203	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T195	7		T126	2		T231	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T188	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T148	7		T94	2		T95	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T55	10		T193	10		T118	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	876	1			T19	9		T53	22		T54	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T84	8		T99	12		T199	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T99	12		T123	1		T235	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T84	12		T121	9		T104	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T85	12		T208	19		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	10		T113	3		T139	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	1		T33	4		T194	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	5		T84	11		T81	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	2		T113	8		T104	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	7		T86	10		T117	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T97	7		T131	14		T105	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T122	8		T131	9		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T55	2		T112	10		T201	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	8		T104	10		T123	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T113	10		T195	6		T119	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T55	9		T154	2		T200	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10