Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21977

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3653

1

T10

8

T12

9

T13

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20035

1

T22

1

T24

1

T25

1

auto[1]

5595

1

T12

9

T13

11

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T191	3		-	-		-	-
values[0]	29	1			T156	6		T236	9		T197	2
values[1]	748	1			T84	26		T55	13		T100	7
values[2]	683	1			T15	2		T20	1		T112	20
values[3]	547	1			T55	10		T113	17		T111	26
values[4]	668	1			T190	1		T85	3		T118	31
values[5]	679	1			T111	26		T95	11		T194	7
values[6]	562	1			T16	4		T20	1		T55	9
values[7]	627	1			T12	9		T13	11		T17	9
values[8]	725	1			T10	8		T84	22		T113	12
values[9]	3122	1			T10	8		T14	3		T16	1
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	830	1			T84	26		T55	13		T100	7
values[1]	738	1			T15	2		T20	1		T111	26
values[2]	602	1			T55	10		T113	17		T85	27
values[3]	725	1			T190	1		T85	3		T96	19
values[4]	677	1			T16	4		T111	26		T95	11
values[5]	472	1			T12	9		T13	11		T20	1
values[6]	2538	1			T14	3		T17	9		T19	10
values[7]	732	1			T10	8		T84	22		T33	8
values[8]	863	1			T10	8		T16	1		T17	2
values[9]	187	1			T20	1		T30	2		T96	8
minimum	17266	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T84	13		T100	7		T104	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T55	11		T113	11		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	1		T112	11		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T20	1		T111	14		T86	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T55	10		T113	9		T118	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T85	13		T98	1		T118	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T114	4		T196	6		T200	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T190	1		T85	2		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T111	12		T95	9		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T16	3		T194	6		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T20	1		T55	3		T94	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	7		T13	11		T103	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T14	3		T19	10		T53	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T17	9		T21	1		T99	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	6		T97	8		T195	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T84	12		T33	5		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T16	1		T84	9		T81	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	1		T17	1		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T20	1		T30	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T189	1		T123	14		T88	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17119	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T237	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T84	13		T215	13		T120	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T55	2		T113	14		T148	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	1		T112	9		T50	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T111	12		T86	9		T99	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T113	8		T118	10		T119	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T85	14		T118	16		T218	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T114	2		T200	2		T235	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T85	1		T96	18		T141	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T111	14		T95	2		T191	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	1		T194	1		T86	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T55	6		T94	1		T195	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	2		T30	11		T78	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T116	6		T92	27		T101	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	4		T99	11		T200	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T10	2		T97	8		T195	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T84	10		T33	3		T88	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T81	12		T194	11		T87	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	7		T17	1		T93	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T30	1		T96	7		T139	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T189	13		T88	2		T199	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T237	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T191	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T236	3		T238	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T156	1		T197	1		T239	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T84	13		T100	7		T104	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T55	11		T113	11		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	1		T112	11		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T20	1		T86	11		T99	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	10		T113	9		T118	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T111	14		T85	13		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T204	1		T114	4		T209	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T190	1		T85	2		T118	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T111	12		T95	9		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T194	6		T96	1		T195	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T20	1		T55	3		T195	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	3		T78	4		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T94	6		T115	1		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	7		T13	11		T17	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	6		T113	4		T193	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T84	12		T33	5		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T14	3		T16	1		T19	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T10	1		T17	1		T93	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T191	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T236	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T156	5		T197	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T84	13		T215	13		T109	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T55	2		T113	14		T148	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	1		T112	9		T50	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T86	9		T99	14		T217	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T113	8		T118	10		T217	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T111	12		T85	14		T218	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T114	2		T220	10		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T85	1		T118	16		T141	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T111	14		T95	2		T191	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T194	1		T96	18		T195	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T55	6		T195	8		T221	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	1		T78	2		T86	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T94	1		T109	6		T210	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	2		T21	4		T30	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	2		T113	8		T193	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T84	10		T33	3		T46	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T116	6		T92	27		T81	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T10	7		T17	1		T93	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T84	14		T100	1		T104	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T55	3		T113	15		T148	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	2		T112	10		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T20	1		T111	13		T86	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T55	1		T113	9		T118	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T85	15		T98	1		T118	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T114	5		T196	1		T200	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T190	1		T85	3		T96	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T111	15		T95	6		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	3		T194	2		T86	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T20	1		T55	7		T94	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	7		T13	1		T103	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T14	3		T19	1		T53	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T17	1		T21	5		T99	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	3		T97	9		T195	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T84	11		T33	4		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T16	1		T84	1		T81	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	8		T17	2		T93	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T20	1		T30	2		T96	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T189	14		T123	1		T88	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17250	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T237	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T84	12		T100	6		T104	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T55	10		T113	10		T123	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T112	10		T106	9		T241	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T111	13		T86	10		T99	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T55	9		T113	8		T118	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T85	12		T118	14		T218	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T114	1		T196	5		T200	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T104	10		T213	9		T122	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T111	11		T95	5		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	1		T194	5		T195	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T55	2		T94	2		T195	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	2		T13	10		T30	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	857	1			T19	9		T53	22		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	8		T99	12		T200	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	5		T97	7		T195	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T84	11		T33	4		T106	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T84	8		T81	10		T194	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T148	7		T222	10		T107	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T139	1		T121	9		T154	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T123	13		T88	1		T242	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T210	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T191	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T236	9		T238	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T156	6		T197	2		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T84	14		T100	1		T104	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T55	3		T113	15		T148	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	2		T112	10		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	1		T86	10		T99	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	1		T113	9		T118	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T111	13		T85	15		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T204	1		T114	5		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T190	1		T85	3		T118	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T111	15		T95	6		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T194	2		T96	19		T195	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T20	1		T55	7		T195	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	3		T78	6		T86	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T94	5		T115	1		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	7		T13	1		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	3		T113	9		T193	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T84	11		T33	4		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T14	3		T16	1		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T10	8		T17	2		T93	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T238	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T239	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T84	12		T100	6		T104	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T55	10		T113	10		T199	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T112	10		T106	9		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T86	10		T99	12		T104	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T55	9		T113	8		T118	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T111	13		T85	12		T213	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T114	1		T209	13		T240	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T118	14		T104	10		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T111	11		T95	5		T196	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T194	5		T195	6		T122	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T55	2		T195	7		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T16	1		T119	18		T207	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T94	2		T227	13		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	2		T13	10		T17	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	5		T113	3		T193	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T84	11		T33	4		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T19	9		T53	22		T54	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T148	7		T123	13		T88	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10