Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22285

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3345

1

T10

16

T16

1

T17

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20235

1

T22

1

T24

1

T25

1

auto[1]

5395

1

T12

9

T13

11

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	49	1			T125	1		T240	25		T254	7
values[0]	53	1			T205	3		T151	1		T255	3
values[1]	528	1			T12	9		T20	1		T96	19
values[2]	2437	1			T14	3		T19	10		T53	25
values[3]	743	1			T13	11		T16	1		T21	5
values[4]	768	1			T84	22		T55	9		T148	10
values[5]	725	1			T10	8		T17	9		T190	1
values[6]	642	1			T100	7		T194	23		T96	8
values[7]	695	1			T20	1		T103	1		T113	25
values[8]	665	1			T20	1		T103	1		T113	12
values[9]	1088	1			T10	8		T15	2		T16	4
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	768	1			T12	9		T20	1		T189	14
values[1]	2491	1			T14	3		T16	1		T19	10
values[2]	826	1			T13	11		T21	5		T84	35
values[3]	607	1			T10	8		T84	22		T30	26
values[4]	726	1			T17	9		T148	16		T96	8
values[5]	613	1			T20	1		T190	1		T100	7
values[6]	674	1			T103	2		T113	25		T85	27
values[7]	748	1			T20	1		T113	12		T85	3
values[8]	688	1			T10	8		T16	4		T17	2
values[9]	252	1			T15	2		T119	8		T232	12
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	7		T20	1		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T189	1		T118	10		T104	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T14	3		T19	10		T53	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	1		T55	11		T113	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T13	11		T21	1		T84	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T84	9		T123	14		T196	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	14		T111	14		T33	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	6		T84	12		T78	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T17	9		T148	8		T123	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T148	1		T96	1		T97	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T100	7		T194	12		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T20	1		T190	1		T111	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T103	1		T85	13		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T103	1		T113	11		T154	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T117	3		T191	1		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T20	1		T113	4		T85	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	3		T55	10		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	1		T17	1		T112	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T15	1		T232	1		T218	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T119	8		T207	18		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	2		T222	11		T207	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T189	13		T118	10		T241	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T116	6		T92	27		T81	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T55	2		T113	8		T88	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	4		T84	13		T55	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T219	21		T257	1		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	12		T111	12		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	2		T84	10		T78	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T148	2		T205	1		T217	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	5		T96	7		T97	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T194	11		T195	13		T87	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T111	14		T95	2		T195	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T85	14		T193	10		T189	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T113	14		T154	4		T199	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T117	1		T191	2		T107	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T113	8		T85	1		T86	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	1		T93	14		T139	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	7		T17	1		T112	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T15	1		T232	11		T218	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T207	18		T256	15		T258	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T125	1		T240	12		T254	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T259	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T205	3		T151	1		T255	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T239	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	7		T20	1		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T118	10		T104	11		T105	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T14	3		T19	10		T53	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T55	11		T189	1		T123	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T13	11		T21	1		T84	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T16	1		T84	9		T113	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T55	3		T148	8		T30	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T84	12		T78	4		T123	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T17	9		T30	1		T86	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	6		T190	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T100	7		T194	12		T195	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T96	1		T221	1		T106	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T103	1		T85	13		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T20	1		T113	11		T111	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T117	3		T191	1		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T20	1		T103	1		T113	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T15	1		T16	3		T55	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T10	1		T17	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T240	13		T254	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T259	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T260	19		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T96	18		T222	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T118	10		T241	7		T261	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T116	6		T92	27		T101	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	2		T189	13		T88	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T21	4		T84	13		T81	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T113	8		T159	2		T252	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T55	6		T148	2		T30	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T84	10		T78	2		T50	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T30	1		T86	9		T205	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	2		T148	5		T194	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T194	11		T195	13		T131	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T96	7		T221	15		T106	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T85	14		T193	10		T189	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T113	14		T111	14		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T117	1		T191	2		T196	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T113	8		T85	1		T86	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	1		T16	1		T93	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T10	7		T17	1		T112	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	7		T20	1		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T189	14		T118	11		T104	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T14	3		T19	1		T53	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	1		T55	3		T113	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	1		T21	5		T84	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T84	1		T123	1		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	19		T111	13		T33	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	3		T84	11		T78	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T17	1		T148	3		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T148	6		T96	8		T97	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T100	1		T194	12		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	1		T190	1		T111	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T103	1		T85	15		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T103	1		T113	15		T154	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T117	3		T191	3		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T20	1		T113	9		T85	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T16	3		T55	1		T93	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	8		T17	2		T112	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T15	2		T232	12		T218	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T119	1		T207	20		T256	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	2		T213	9		T205	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T118	9		T104	10		T105	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	848	1			T19	9		T53	22		T54	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T55	10		T113	8		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	10		T84	12		T55	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T84	8		T123	13		T196	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	7		T111	13		T33	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	5		T84	11		T194	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T17	8		T148	7		T123	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T97	7		T131	14		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T100	6		T194	11		T195	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T111	11		T95	5		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T85	12		T193	10		T211	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T113	10		T154	2		T199	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T117	1		T158	10		T227	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T113	3		T104	12		T122	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T16	1		T55	9		T139	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T112	10		T195	7		T114	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T218	4		T240	11		T262	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T119	7		T207	16		T258	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T125	1		T240	14		T254	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T259	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T205	1		T151	1		T255	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T239	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	7		T20	1		T96	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T118	11		T104	1		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T14	3		T19	1		T53	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T55	3		T189	14		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T13	1		T21	5		T84	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	1		T84	1		T113	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T55	7		T148	3		T30	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T84	11		T78	6		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	1		T30	2		T86	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	3		T190	1		T148	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T100	1		T194	12		T195	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T96	8		T221	16		T106	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T103	1		T85	15		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T20	1		T113	15		T111	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T117	3		T191	3		T196	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	1		T103	1		T113	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T15	2		T16	3		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T10	8		T17	2		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T240	11		T254	2		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T205	2		T260	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T239	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T12	2		T213	9		T222	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T118	9		T104	10		T105	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	825	1			T19	9		T53	22		T54	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T55	10		T123	2		T200	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	10		T84	12		T81	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T84	8		T113	8		T196	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	2		T148	7		T30	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T84	11		T123	13		T208	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T17	8		T86	10		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	5		T194	5		T97	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T100	6		T194	11		T195	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T106	1		T231	7		T263	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T85	12		T193	10		T211	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T113	10		T111	11		T95	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T117	1		T200	13		T105	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T113	3		T154	2		T199	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	1		T55	9		T139	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T112	10		T195	7		T104	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10