Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21858

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3772

1

T10

8

T15

2

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20040

1

T22

1

T24

1

T25

1

auto[1]

5590

1

T10

8

T13

11

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T262	12		T245	1		-	-
values[0]	56	1			T96	8		T199	2		T141	10
values[1]	591	1			T20	1		T84	22		T55	9
values[2]	532	1			T10	8		T15	2		T55	13
values[3]	643	1			T13	11		T17	9		T20	1
values[4]	679	1			T10	8		T21	5		T84	26
values[5]	767	1			T16	4		T30	2		T204	1
values[6]	725	1			T148	10		T95	11		T189	14
values[7]	587	1			T190	1		T100	7		T113	12
values[8]	2579	1			T14	3		T19	10		T53	25
values[9]	1221	1			T12	9		T16	1		T17	2
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	680	1			T15	2		T20	1		T84	22
values[1]	695	1			T10	8		T55	13		T103	1
values[2]	553	1			T13	11		T17	9		T20	1
values[3]	802	1			T10	8		T16	4		T21	5
values[4]	774	1			T99	24		T204	1		T213	10
values[5]	687	1			T190	1		T100	7		T148	10
values[6]	2331	1			T14	3		T19	10		T53	25
values[7]	711	1			T103	1		T111	26		T98	1
values[8]	811	1			T12	9		T16	1		T17	2
values[9]	327	1			T55	10		T121	21		T195	16
minimum	17259	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T84	12		T96	1		T195	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	1		T20	1		T55	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	6		T33	5		T51	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T55	11		T103	1		T30	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	11		T17	9		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T85	1		T94	6		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T16	3		T97	8		T99	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	1		T21	1		T84	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	1		T131	10		T141	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T99	13		T204	1		T213	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T190	1		T100	7		T194	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T148	8		T95	9		T86	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1153	1			T14	3		T19	10		T53	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T111	12		T85	1		T200	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T103	1		T98	1		T211	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T111	14		T195	14		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	7		T84	9		T81	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T16	1		T17	1		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T55	10		T104	13		T154	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T121	10		T195	8		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T191	1		T89	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T84	10		T96	7		T195	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T15	1		T55	6		T93	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	2		T33	3		T214	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T55	2		T30	11		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T113	8		T78	2		T88	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T94	1		T241	7		T218	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T16	1		T97	8		T99	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T10	7		T21	4		T84	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T50	12		T131	12		T141	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T99	11		T46	10		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T194	11		T191	2		T90	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T148	2		T95	2		T86	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T116	6		T92	27		T101	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T111	14		T85	1		T200	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T211	4		T196	2		T218	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T111	12		T195	13		T219	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	2		T81	12		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T17	1		T85	14		T194	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T154	4		T205	1		T200	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T121	11		T195	8		T221	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T191	11		T89	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T262	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T96	1		T199	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T141	1		T219	9		T153	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T84	12		T200	5		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	1		T55	3		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	6		T195	7		T51	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	1		T55	11		T112	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	11		T17	9		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T103	1		T85	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T113	9		T97	8		T99	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	1		T21	1		T84	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	3		T104	13		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T30	1		T204	1		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T191	1		T90	1		T106	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T148	8		T95	9		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T190	1		T100	7		T113	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T111	12		T86	11		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T14	3		T19	10		T53	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T111	14		T85	1		T194	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T12	7		T84	9		T55	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T16	1		T17	1		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T262	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T96	7		T199	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T141	9		T219	21		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T84	10		T200	11		T264	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T55	6		T93	14		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T10	2		T195	7		T120	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	1		T55	2		T112	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T33	3		T78	2		T50	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T86	3		T118	16		T119	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T113	8		T97	8		T99	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	7		T21	4		T84	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	1		T50	12		T131	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T30	1		T46	10		T222	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T191	2		T90	7		T106	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T148	2		T95	2		T189	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T113	8		T194	11		T201	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T111	14		T86	9		T189	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T116	6		T92	27		T101	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T111	12		T85	1		T194	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	2		T81	12		T113	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T17	1		T85	14		T96	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T84	11		T96	8		T195	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T15	2		T20	1		T55	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	3		T33	4		T51	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T55	3		T103	1		T30	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T17	1		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T85	1		T94	5		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	3		T97	9		T99	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T10	8		T21	5		T84	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T50	13		T131	13		T141	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T99	12		T204	1		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T190	1		T100	1		T194	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T148	3		T95	6		T86	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T14	3		T19	1		T53	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T111	15		T85	2		T200	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T103	1		T98	1		T211	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T111	13		T195	14		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	7		T84	1		T81	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T16	1		T17	2		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T55	1		T104	1		T154	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T121	12		T195	9		T221	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T191	12		T89	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T84	11		T195	6		T200	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T55	2		T199	8		T196	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	5		T33	4		T214	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T55	10		T30	7		T112	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T13	10		T17	8		T113	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T94	2		T105	16		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	1		T97	7		T99	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T84	12		T193	10		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T131	9		T141	2		T105	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T99	12		T213	9		T208	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T100	6		T194	11		T212	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	7		T95	5		T86	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	832	1			T19	9		T53	22		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T111	11		T200	13		T235	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T211	5		T104	10		T218	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T111	13		T195	13		T219	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T84	8		T81	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T85	12		T194	5		T122	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T55	9		T104	12		T154	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T121	9		T195	7		T265	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T262	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T96	8		T199	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T141	10		T219	22		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T84	11		T200	12		T264	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	1		T55	7		T93	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	3		T195	8		T51	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	2		T55	3		T112	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T17	1		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T103	1		T85	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T113	9		T97	9		T99	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	8		T21	5		T84	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	3		T104	1		T50	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T30	2		T204	1		T46	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T191	3		T90	8		T106	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T148	3		T95	6		T189	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T190	1		T100	1		T113	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T111	15		T86	10		T189	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T14	3		T19	1		T53	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T111	13		T85	2		T194	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T12	7		T84	1		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	440	1			T16	1		T17	2		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T262	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T219	8		T153	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T84	11		T200	4		T107	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T55	2		T30	7		T199	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T10	5		T195	6		T126	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T55	10		T112	10		T139	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	10		T17	8		T33	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T118	14		T119	18		T241	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T113	8		T97	7		T99	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T84	12		T94	2		T193	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T16	1		T104	12		T131	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T222	10		T227	10		T107	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T106	9		T126	14		T242	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T148	7		T95	5		T99	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T100	6		T113	3		T194	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T111	11		T86	10		T200	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	834	1			T19	9		T53	22		T54	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T111	13		T194	5		T195	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	2		T84	8		T55	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T85	12		T121	9		T195	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10