Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21954

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3676

1

T10

8

T15

2

T16

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20034

1

T22

1

T24

1

T25

1

auto[1]

5596

1

T13

11

T14

3

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	131	1			T191	3		T221	18		T232	12
values[0]	11	1			T205	3		T160	8		-	-
values[1]	764	1			T10	8		T84	22		T100	7
values[2]	842	1			T20	1		T30	24		T111	26
values[3]	631	1			T85	1		T96	19		T193	21
values[4]	2675	1			T14	3		T19	10		T20	1
values[5]	485	1			T93	15		T98	1		T99	24
values[6]	679	1			T17	11		T21	5		T190	1
values[7]	693	1			T13	11		T84	35		T113	17
values[8]	544	1			T15	2		T55	10		T103	1
values[9]	938	1			T10	8		T12	9		T16	5
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	744	1			T100	7		T148	16		T30	2
values[1]	794	1			T20	1		T30	24		T111	26
values[2]	674	1			T85	1		T194	7		T96	19
values[3]	2639	1			T14	3		T19	10		T20	1
values[4]	425	1			T17	2		T93	15		T98	1
values[5]	639	1			T17	9		T21	5		T84	9
values[6]	779	1			T13	11		T84	26		T103	1
values[7]	474	1			T15	2		T55	10		T204	1
values[8]	826	1			T10	8		T12	9		T16	5
values[9]	154	1			T55	9		T221	18		T207	5
minimum	17482	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T100	7		T148	8		T85	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T148	1		T30	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T20	1		T30	13		T78	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T111	12		T199	11		T266	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T104	11		T191	1		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T85	1		T194	6		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T14	3		T19	10		T53	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	1		T94	6		T194	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T93	1		T98	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	1		T99	13		T104	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T21	1		T84	9		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	9		T190	1		T104	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	11		T111	14		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T84	13		T103	1		T113	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T204	1		T141	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T55	10		T200	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T10	6		T12	7		T55	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T16	4		T20	1		T85	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T55	3		T267	1		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T221	3		T207	1		T268	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17173	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T10	1		T142	1		T235	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T148	2		T85	1		T86	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T148	5		T30	1		T139	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T30	11		T78	2		T193	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T111	14		T199	2		T221	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T191	14		T90	7		T50	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T194	1		T96	18		T118	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T116	6		T92	27		T81	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T94	1		T194	11		T189	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T93	14		T191	11		T214	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T17	1		T99	11		T114	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T21	4		T95	2		T201	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T131	12		T256	15		T269	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T111	12		T106	10		T107	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T84	13		T113	8		T189	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T141	9		T109	7		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	1		T200	16		T212	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	2		T12	2		T55	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T16	1		T85	14		T191	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T55	6		T267	12		T187	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T221	15		T207	4		T271	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T10	7		T142	12		T235	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T232	1		T110	1		T175	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T191	1		T221	3		T251	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T205	3		T160	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T84	12		T100	7		T148	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	1		T148	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T20	1		T30	13		T119	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T111	12		T194	6		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T193	11		T104	11		T123	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T85	1		T96	1		T118	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T14	3		T19	10		T53	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T20	1		T94	6		T194	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T93	1		T98	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T99	13		T104	13		T123	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T21	1		T103	1		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	10		T190	1		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	11		T84	9		T95	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T84	13		T113	9		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T111	14		T98	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	1		T55	10		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	6		T12	7		T55	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T16	4		T20	1		T85	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T232	11		T175	16		T273	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T191	2		T221	15		T248	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T160	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T84	10		T148	2		T33	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	7		T148	5		T30	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	11		T119	2		T240	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T111	14		T194	1		T217	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T193	10		T191	14		T90	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T96	18		T118	16		T88	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T116	6		T92	27		T81	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T94	1		T194	11		T189	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T93	14		T214	4		T274	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T99	11		T114	2		T88	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	4		T191	11		T201	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	1		T131	12		T256	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T95	2		T106	10		T107	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T84	13		T113	8		T189	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T111	12		T141	9		T210	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	1		T200	16		T119	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	2		T12	2		T55	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T16	1		T85	14		T131	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T100	1		T148	3		T85	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T148	6		T30	2		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T20	1		T30	17		T78	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T111	15		T199	5		T266	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T104	1		T191	15		T90	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T85	1		T194	2		T96	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T14	3		T19	1		T53	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T20	1		T94	5		T194	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T93	15		T98	1		T191	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	2		T99	12		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T21	5		T84	1		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	1		T190	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	1		T111	13		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T84	14		T103	1		T113	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T204	1		T141	10		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	2		T55	1		T200	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	3		T12	7		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T16	4		T20	1		T85	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T55	7		T267	13		T187	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T221	16		T207	5		T268	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17306	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T10	8		T142	13		T235	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T100	6		T148	7		T86	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T139	1		T99	12		T122	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T30	7		T193	10		T123	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T111	11		T199	8		T221	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T104	10		T107	4		T275	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T194	5		T118	14		T88	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T19	9		T53	22		T54	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T94	2		T194	11		T195	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T214	15		T212	3		T159	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T99	12		T104	12		T114	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T84	8		T95	5		T201	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	8		T104	12		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	10		T111	13		T105	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T84	12		T113	8		T118	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T109	7		T276	2		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T55	9		T200	13		T227	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	5		T12	2		T55	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T16	1		T85	12		T105	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T55	2		T277	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T221	2		T271	18		T278	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T84	11		T33	4		T205	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T233	10		T129	12		T279	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T232	12		T110	1		T175	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T191	3		T221	16		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T205	1		T160	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T84	11		T100	1		T148	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	8		T148	6		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T20	1		T30	17		T119	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T111	15		T194	2		T217	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T193	11		T104	1		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T85	1		T96	19		T118	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T14	3		T19	1		T53	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T20	1		T94	5		T194	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T93	15		T98	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T99	12		T104	1		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T21	5		T103	1		T191	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T17	3		T190	1		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	1		T84	1		T95	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T84	14		T113	9		T189	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T111	13		T98	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T15	2		T55	1		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	3		T12	7		T55	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T16	4		T20	1		T85	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T175	12		T280	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T221	2		T251	11		T278	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T205	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T84	11		T100	6		T148	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T139	1		T99	12		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T30	7		T119	2		T240	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T111	11		T194	5		T221	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T193	10		T104	10		T123	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T118	14		T88	1		T199	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	870	1			T19	9		T53	22		T54	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T94	2		T194	11		T195	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T214	15		T219	5		T212	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T99	12		T104	12		T123	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T201	6		T200	4		T227	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	8		T213	9		T131	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	10		T84	8		T95	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T84	12		T113	8		T118	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T111	13		T105	9		T276	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T55	9		T200	13		T119	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	5		T12	2		T55	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	1		T85	12		T105	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10