Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25630

1

T22

1

T24

1

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22210

1

T22

1

T24

1

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3420

1

T10

8

T12

9

T13

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20125

1

T22

1

T24

1

T25

1

auto[1]

5505

1

T14

3

T19

10

T20

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T10

7

T11

148

T12

8

auto[1]

3957

1

T22

1

T24

1

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T281	19		-	-		-	-
values[0]	74	1			T205	3		T282	1		T283	3
values[1]	772	1			T12	9		T20	1		T21	5
values[2]	655	1			T84	22		T30	2		T98	1
values[3]	669	1			T10	8		T17	9		T148	10
values[4]	591	1			T93	15		T112	20		T194	30
values[5]	2629	1			T10	8		T13	11		T14	3
values[6]	568	1			T15	2		T16	4		T85	27
values[7]	528	1			T17	2		T20	1		T113	12
values[8]	759	1			T84	9		T81	23		T97	16
values[9]	1129	1			T16	1		T84	26		T190	1
minimum	17237	1			T22	1		T24	1		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	898	1			T12	9		T20	1		T21	5
values[1]	634	1			T17	9		T113	25		T30	2
values[2]	763	1			T93	15		T148	10		T85	1
values[3]	2540	1			T10	8		T14	3		T19	10
values[4]	596	1			T10	8		T16	4		T20	1
values[5]	599	1			T13	11		T15	2		T17	2
values[6]	695	1			T20	1		T81	23		T113	12
values[7]	633	1			T84	9		T86	20		T97	16
values[8]	812	1			T16	1		T84	26		T100	7
values[9]	186	1			T190	1		T113	17		T94	7
minimum	17274	1			T22	1		T24	1		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

3530

1

T10

5

T12

2

T13

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T21	1		T55	10		T103	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	7		T20	1		T84	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	9		T30	1		T201	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T113	11		T189	1		T211	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T112	11		T139	7		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T93	1		T148	8		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T10	1		T14	3		T19	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T85	1		T104	24		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T55	11		T117	3		T123	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	6		T16	3		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T85	13		T78	4		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	11		T15	1		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T20	1		T81	11		T33	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T113	4		T284	1		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T272	1		T131	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T84	9		T86	11		T97	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T16	1		T84	13		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T100	7		T148	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T113	9		T94	6		T95	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T190	1		T96	1		T286	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17119	1			T11	148		T12	1		T16	80
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T287	8		T288	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T21	4		T86	3		T189	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	2		T84	10		T99	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T30	1		T201	2		T264	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T113	14		T189	13		T211	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T112	9		T139	2		T191	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T93	14		T148	2		T195	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T10	7		T116	6		T92	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T85	1		T131	14		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T55	2		T117	1		T205	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	2		T16	1		T55	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T85	14		T78	2		T96	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T15	1		T17	1		T193	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T81	12		T33	3		T200	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T113	8		T219	21		T212	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	10		T217	2		T119	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T86	9		T97	8		T118	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T84	13		T111	12		T121	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T148	5		T199	1		T50	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T113	8		T94	1		T95	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T96	7		T289	12		T290	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T22	1		T24	1		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T287	10		T288	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T281	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T260	13		T291	5		T145	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T205	3		T282	1		T283	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T21	1		T55	10		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	7		T20	1		T113	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T30	1		T98	1		T201	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T84	12		T211	6		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T10	1		T17	9		T139	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T148	8		T85	1		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T112	11		T194	18		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T93	1		T97	1		T104	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T14	3		T19	10		T53	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T10	6		T13	11		T20	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T85	13		T78	4		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	1		T16	3		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	1		T33	5		T123	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	1		T113	4		T193	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T81	11		T131	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T84	9		T97	8		T118	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T16	1		T84	13		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T190	1		T100	7		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T11	148		T12	1		T16	80
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T281	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T260	13		T291	3		T145	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T273	10		T288	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T21	4		T86	3		T189	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	2		T113	14		T99	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	1		T201	2		T264	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T84	10		T211	4		T196	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T10	7		T139	2		T191	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	2		T189	13		T195	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T112	9		T194	12		T46	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T93	14		T191	11		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T116	6		T92	27		T55	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	2		T55	6		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T85	14		T78	2		T96	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T16	1		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T33	3		T200	2		T292	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T17	1		T113	8		T193	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T81	12		T131	10		T217	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T97	8		T118	16		T199	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T84	13		T113	8		T111	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T148	5		T86	9		T96	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	1		T24	1		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T21	5		T55	1		T103	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	7		T20	1		T84	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T17	1		T30	2		T201	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T113	15		T189	14		T211	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T112	10		T139	8		T191	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T93	15		T148	3		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T10	8		T14	3		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T85	2		T104	2		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T55	3		T117	3		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	3		T16	3		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T85	15		T78	6		T96	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	1		T15	2		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T20	1		T81	13		T33	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T113	9		T284	1		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T272	1		T131	11		T217	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T84	1		T86	10		T97	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T16	1		T84	14		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T100	1		T148	6		T199	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T113	9		T94	5		T95	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T190	1		T96	8		T286	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17247	1			T22	1		T24	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T287	11		T288	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T55	9		T244	2		T212	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	2		T84	11		T99	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	8		T201	6		T240	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T113	10		T211	5		T221	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T112	10		T139	1		T218	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T148	7		T195	20		T104	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T19	9		T53	22		T54	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T104	22		T131	14		T200	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T55	10		T117	1		T123	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	5		T16	1		T55	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T85	12		T195	6		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	10		T193	10		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T81	10		T33	4		T123	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T113	3		T219	8		T212	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T119	2		T227	10		T107	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T84	8		T86	10		T97	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T84	12		T111	13		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T100	6		T207	16		T218	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T113	8		T94	2		T95	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T286	17		T290	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T145	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T287	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T281	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T260	14		T291	6		T145	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T205	1		T282	1		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T21	5		T55	1		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	7		T20	1		T113	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	2		T98	1		T201	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T84	11		T211	5		T196	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	8		T17	1		T139	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T148	3		T85	1		T189	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T112	10		T194	14		T46	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T93	15		T97	1		T104	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T14	3		T19	1		T53	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T10	3		T13	1		T20	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T85	15		T78	6		T96	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	2		T16	3		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T20	1		T33	4		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	2		T113	9		T193	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T81	13		T131	11		T217	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T84	1		T97	9		T118	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T16	1		T84	14		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T190	1		T100	1		T148	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17237	1			T22	1		T24	1		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T281	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T260	12		T291	2		T145	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T205	2		T283	2		T276	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T55	9		T244	2		T212	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	2		T113	10		T99	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T201	6		T240	5		T265	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T84	11		T211	5		T221	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T17	8		T139	1		T107	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T148	7		T195	20		T88	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T112	10		T194	16		T106	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T104	22		T123	1		T200	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T19	9		T53	22		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	5		T13	10		T55	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T85	12		T117	1		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T16	1		T213	9		T131	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T33	4		T123	2		T200	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T113	3		T193	10		T219	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T81	10		T227	10		T109	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T84	8		T97	7		T118	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T84	12		T113	8		T111	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T100	6		T86	10		T196	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22100

1

T22

1

T24

1

T25

1

auto[1]

auto[0]

3530

1

T10

5

T12

2

T13

10