Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.54	98.98	95.69	100.00	100.00	98.18	98.64	91.27

Total test records in report: 915

T773	/workspace/coverage/default/35.adc_ctrl_smoke.1308108498	Feb 07 01:27:11 PM PST 24	Feb 07 01:27:17 PM PST 24	6000450533 ps
T774	/workspace/coverage/default/3.adc_ctrl_fsm_reset.1611566265	Feb 07 01:19:09 PM PST 24	Feb 07 01:30:23 PM PST 24	128073084056 ps
T775	/workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1166923419	Feb 07 01:27:54 PM PST 24	Feb 07 01:47:32 PM PST 24	489670105126 ps
T294	/workspace/coverage/default/27.adc_ctrl_filters_interrupt.1630549009	Feb 07 01:26:12 PM PST 24	Feb 07 01:38:19 PM PST 24	331896164854 ps
T776	/workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.145525833	Feb 07 01:27:00 PM PST 24	Feb 07 01:30:15 PM PST 24	326299586737 ps
T777	/workspace/coverage/default/36.adc_ctrl_filters_polled.2110534521	Feb 07 01:27:19 PM PST 24	Feb 07 01:39:35 PM PST 24	327368250851 ps
T778	/workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2498219730	Feb 07 01:22:28 PM PST 24	Feb 07 01:26:12 PM PST 24	165821593608 ps
T779	/workspace/coverage/default/28.adc_ctrl_alert_test.4209057551	Feb 07 01:26:15 PM PST 24	Feb 07 01:26:18 PM PST 24	292598510 ps
T780	/workspace/coverage/default/14.adc_ctrl_filters_both.4030107762	Feb 07 01:20:58 PM PST 24	Feb 07 01:27:18 PM PST 24	165072895220 ps
T781	/workspace/coverage/default/39.adc_ctrl_smoke.4019402477	Feb 07 01:28:16 PM PST 24	Feb 07 01:28:24 PM PST 24	6150853745 ps
T42	/workspace/coverage/default/3.adc_ctrl_sec_cm.1345794667	Feb 07 01:19:14 PM PST 24	Feb 07 01:19:25 PM PST 24	4246978484 ps
T782	/workspace/coverage/default/12.adc_ctrl_filters_interrupt.4290076649	Feb 07 01:20:48 PM PST 24	Feb 07 01:33:42 PM PST 24	331677473704 ps
T783	/workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3747132121	Feb 07 01:26:57 PM PST 24	Feb 07 01:33:49 PM PST 24	170463845632 ps
T784	/workspace/coverage/default/41.adc_ctrl_poweron_counter.3823144929	Feb 07 01:28:32 PM PST 24	Feb 07 01:28:35 PM PST 24	3921746429 ps
T281	/workspace/coverage/default/21.adc_ctrl_clock_gating.2127429524	Feb 07 01:22:52 PM PST 24	Feb 07 01:27:10 PM PST 24	502859199534 ps
T202	/workspace/coverage/default/21.adc_ctrl_filters_both.36033703	Feb 07 01:22:53 PM PST 24	Feb 07 01:33:14 PM PST 24	488687812781 ps
T785	/workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3292780014	Feb 07 01:19:14 PM PST 24	Feb 07 01:22:35 PM PST 24	115589074997 ps
T786	/workspace/coverage/default/18.adc_ctrl_alert_test.2347789672	Feb 07 01:22:27 PM PST 24	Feb 07 01:22:29 PM PST 24	317769355 ps
T787	/workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.290260602	Feb 07 01:27:09 PM PST 24	Feb 07 01:33:07 PM PST 24	158736966888 ps
T788	/workspace/coverage/default/46.adc_ctrl_smoke.3878520777	Feb 07 01:29:36 PM PST 24	Feb 07 01:29:39 PM PST 24	5705107816 ps
T789	/workspace/coverage/default/43.adc_ctrl_alert_test.2801057928	Feb 07 01:29:15 PM PST 24	Feb 07 01:29:16 PM PST 24	504994548 ps
T224	/workspace/coverage/default/32.adc_ctrl_filters_both.2909908669	Feb 07 01:26:56 PM PST 24	Feb 07 01:28:21 PM PST 24	164788977332 ps
T182	/workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.266010408	Feb 07 01:26:59 PM PST 24	Feb 07 01:29:30 PM PST 24	211550112968 ps
T299	/workspace/coverage/default/7.adc_ctrl_clock_gating.344243542	Feb 07 01:20:02 PM PST 24	Feb 07 01:31:57 PM PST 24	323488258611 ps
T790	/workspace/coverage/default/19.adc_ctrl_filters_polled.1468129435	Feb 07 01:22:26 PM PST 24	Feb 07 01:25:47 PM PST 24	323221792065 ps
T791	/workspace/coverage/default/36.adc_ctrl_filters_wakeup.1652507339	Feb 07 01:27:37 PM PST 24	Feb 07 01:28:50 PM PST 24	168964034644 ps
T792	/workspace/coverage/default/36.adc_ctrl_poweron_counter.181548934	Feb 07 01:27:35 PM PST 24	Feb 07 01:27:38 PM PST 24	3457675682 ps
T793	/workspace/coverage/default/19.adc_ctrl_filters_interrupt.2030292303	Feb 07 01:22:27 PM PST 24	Feb 07 01:29:15 PM PST 24	162587845186 ps
T794	/workspace/coverage/default/0.adc_ctrl_filters_both.3615485149	Feb 07 01:19:05 PM PST 24	Feb 07 01:24:42 PM PST 24	491545658290 ps
T795	/workspace/coverage/default/9.adc_ctrl_smoke.2117422050	Feb 07 01:20:16 PM PST 24	Feb 07 01:20:32 PM PST 24	5968726041 ps
T146	/workspace/coverage/default/40.adc_ctrl_filters_both.3812136146	Feb 07 01:28:20 PM PST 24	Feb 07 01:33:00 PM PST 24	499872292908 ps
T796	/workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1005214161	Feb 07 01:29:16 PM PST 24	Feb 07 01:42:46 PM PST 24	332847734362 ps
T797	/workspace/coverage/default/0.adc_ctrl_alert_test.1031965467	Feb 07 01:19:12 PM PST 24	Feb 07 01:19:13 PM PST 24	323594905 ps
T798	/workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3152218188	Feb 07 01:29:14 PM PST 24	Feb 07 01:34:50 PM PST 24	166634560118 ps
T799	/workspace/coverage/default/16.adc_ctrl_filters_polled.3139202870	Feb 07 01:21:09 PM PST 24	Feb 07 01:27:02 PM PST 24	162822251995 ps
T800	/workspace/coverage/default/31.adc_ctrl_poweron_counter.2156234993	Feb 07 01:26:58 PM PST 24	Feb 07 01:27:00 PM PST 24	4358788486 ps
T280	/workspace/coverage/default/30.adc_ctrl_clock_gating.2186693226	Feb 07 01:26:27 PM PST 24	Feb 07 01:32:17 PM PST 24	317763085231 ps
T801	/workspace/coverage/default/40.adc_ctrl_lowpower_counter.3395072797	Feb 07 01:28:17 PM PST 24	Feb 07 01:29:04 PM PST 24	41257584015 ps
T802	/workspace/coverage/default/20.adc_ctrl_smoke.2033585269	Feb 07 01:22:36 PM PST 24	Feb 07 01:22:40 PM PST 24	6060621380 ps
T313	/workspace/coverage/default/46.adc_ctrl_clock_gating.138754565	Feb 07 01:29:36 PM PST 24	Feb 07 01:38:25 PM PST 24	488537600788 ps
T180	/workspace/coverage/default/23.adc_ctrl_fsm_reset.2439076680	Feb 07 01:23:33 PM PST 24	Feb 07 01:28:43 PM PST 24	87556509456 ps
T803	/workspace/coverage/default/35.adc_ctrl_lowpower_counter.700656541	Feb 07 01:27:25 PM PST 24	Feb 07 01:27:38 PM PST 24	23703901897 ps
T804	/workspace/coverage/default/4.adc_ctrl_filters_wakeup.892585727	Feb 07 01:19:31 PM PST 24	Feb 07 01:22:55 PM PST 24	333069447604 ps
T805	/workspace/coverage/default/12.adc_ctrl_poweron_counter.41442087	Feb 07 01:20:43 PM PST 24	Feb 07 01:20:56 PM PST 24	4924856681 ps
T806	/workspace/coverage/default/40.adc_ctrl_filters_polled.3404611044	Feb 07 01:28:21 PM PST 24	Feb 07 01:37:24 PM PST 24	490152110315 ps
T43	/workspace/coverage/default/2.adc_ctrl_sec_cm.3782548982	Feb 07 01:19:15 PM PST 24	Feb 07 01:19:26 PM PST 24	4445784390 ps
T807	/workspace/coverage/default/43.adc_ctrl_poweron_counter.353585629	Feb 07 01:29:11 PM PST 24	Feb 07 01:29:22 PM PST 24	4467207196 ps
T808	/workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1711573561	Feb 07 01:22:59 PM PST 24	Feb 07 01:24:43 PM PST 24	328479926533 ps
T809	/workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3981196317	Feb 07 01:26:10 PM PST 24	Feb 07 01:46:23 PM PST 24	492124316031 ps
T810	/workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3181395591	Feb 07 01:22:27 PM PST 24	Feb 07 01:25:30 PM PST 24	327486905645 ps
T811	/workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.866474973	Feb 07 01:25:55 PM PST 24	Feb 07 01:31:35 PM PST 24	160743282017 ps
T812	/workspace/coverage/default/9.adc_ctrl_alert_test.4130284965	Feb 07 01:20:18 PM PST 24	Feb 07 01:20:21 PM PST 24	312094722 ps
T813	/workspace/coverage/default/6.adc_ctrl_lowpower_counter.2205891653	Feb 07 01:20:06 PM PST 24	Feb 07 01:20:51 PM PST 24	33955616733 ps
T298	/workspace/coverage/default/19.adc_ctrl_clock_gating.3514149929	Feb 07 01:22:24 PM PST 24	Feb 07 01:33:49 PM PST 24	336602397355 ps
T309	/workspace/coverage/default/10.adc_ctrl_filters_wakeup.718786088	Feb 07 01:20:17 PM PST 24	Feb 07 01:23:35 PM PST 24	161601727337 ps
T239	/workspace/coverage/default/34.adc_ctrl_filters_wakeup.1440247868	Feb 07 01:27:11 PM PST 24	Feb 07 01:36:23 PM PST 24	500438509638 ps
T814	/workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1198333213	Feb 07 01:19:04 PM PST 24	Feb 07 01:38:47 PM PST 24	495961450688 ps
T815	/workspace/coverage/default/30.adc_ctrl_poweron_counter.246498029	Feb 07 01:26:28 PM PST 24	Feb 07 01:26:37 PM PST 24	4824871612 ps
T816	/workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1178101537	Feb 07 01:29:15 PM PST 24	Feb 07 01:30:49 PM PST 24	48414754484 ps
T817	/workspace/coverage/default/44.adc_ctrl_poweron_counter.3398076344	Feb 07 01:29:13 PM PST 24	Feb 07 01:29:19 PM PST 24	3663687303 ps
T818	/workspace/coverage/default/48.adc_ctrl_clock_gating.1258963740	Feb 07 01:29:56 PM PST 24	Feb 07 01:36:18 PM PST 24	164728521987 ps
T819	/workspace/coverage/default/26.adc_ctrl_poweron_counter.955807732	Feb 07 01:25:53 PM PST 24	Feb 07 01:26:03 PM PST 24	3027857542 ps
T147	/workspace/coverage/default/10.adc_ctrl_filters_both.1697931873	Feb 07 01:20:16 PM PST 24	Feb 07 01:23:26 PM PST 24	330434025425 ps
T820	/workspace/coverage/default/9.adc_ctrl_filters_interrupt.3610728062	Feb 07 01:20:18 PM PST 24	Feb 07 01:23:37 PM PST 24	324182749608 ps
T821	/workspace/coverage/default/29.adc_ctrl_stress_all.2068208698	Feb 07 01:26:29 PM PST 24	Feb 07 01:28:45 PM PST 24	237453146609 ps
T822	/workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4008890078	Feb 07 01:22:58 PM PST 24	Feb 07 01:23:30 PM PST 24	55370915317 ps
T823	/workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1088678034	Feb 07 01:21:37 PM PST 24	Feb 07 01:26:40 PM PST 24	488968326940 ps
T824	/workspace/coverage/default/21.adc_ctrl_filters_polled.80645591	Feb 07 01:22:58 PM PST 24	Feb 07 01:27:57 PM PST 24	498798265661 ps
T825	/workspace/coverage/default/36.adc_ctrl_smoke.2595774620	Feb 07 01:27:22 PM PST 24	Feb 07 01:27:26 PM PST 24	5926517975 ps
T826	/workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.72428635	Feb 07 01:26:08 PM PST 24	Feb 07 01:32:48 PM PST 24	165869944385 ps
T827	/workspace/coverage/default/36.adc_ctrl_fsm_reset.4100351679	Feb 07 01:27:38 PM PST 24	Feb 07 01:38:35 PM PST 24	126481897991 ps
T828	/workspace/coverage/default/22.adc_ctrl_smoke.1899078267	Feb 07 01:23:09 PM PST 24	Feb 07 01:23:24 PM PST 24	5697194652 ps
T829	/workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1361650893	Feb 07 01:22:54 PM PST 24	Feb 07 01:26:11 PM PST 24	166729979283 ps
T830	/workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3131621800	Feb 07 01:28:21 PM PST 24	Feb 07 01:29:54 PM PST 24	162194135992 ps
T831	/workspace/coverage/default/18.adc_ctrl_filters_polled.4280670579	Feb 07 01:21:52 PM PST 24	Feb 07 01:24:59 PM PST 24	164357154284 ps
T832	/workspace/coverage/default/47.adc_ctrl_alert_test.2073519650	Feb 07 01:29:53 PM PST 24	Feb 07 01:29:55 PM PST 24	305214921 ps
T833	/workspace/coverage/default/37.adc_ctrl_poweron_counter.2663768691	Feb 07 01:27:43 PM PST 24	Feb 07 01:27:46 PM PST 24	4024480141 ps
T834	/workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4171479465	Feb 07 01:20:17 PM PST 24	Feb 07 01:25:54 PM PST 24	160823589429 ps
T835	/workspace/coverage/default/20.adc_ctrl_poweron_counter.1130357847	Feb 07 01:22:37 PM PST 24	Feb 07 01:22:45 PM PST 24	2835032708 ps
T836	/workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4027094522	Feb 07 01:27:38 PM PST 24	Feb 07 01:32:37 PM PST 24	484553021298 ps
T837	/workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3201657141	Feb 07 01:20:56 PM PST 24	Feb 07 01:26:53 PM PST 24	168742109385 ps
T237	/workspace/coverage/default/3.adc_ctrl_filters_interrupt.2852071023	Feb 07 01:19:10 PM PST 24	Feb 07 01:28:21 PM PST 24	486542925261 ps
T838	/workspace/coverage/default/26.adc_ctrl_filters_polled.1221997848	Feb 07 01:25:47 PM PST 24	Feb 07 01:32:14 PM PST 24	332507823045 ps
T839	/workspace/coverage/default/32.adc_ctrl_fsm_reset.997992261	Feb 07 01:27:00 PM PST 24	Feb 07 01:34:11 PM PST 24	124577917224 ps
T840	/workspace/coverage/default/46.adc_ctrl_fsm_reset.1324442108	Feb 07 01:29:39 PM PST 24	Feb 07 01:36:19 PM PST 24	95617141607 ps
T841	/workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1868286856	Feb 07 01:29:03 PM PST 24	Feb 07 01:30:20 PM PST 24	332692341970 ps
T842	/workspace/coverage/default/26.adc_ctrl_filters_interrupt.2148305446	Feb 07 01:25:57 PM PST 24	Feb 07 01:28:37 PM PST 24	163715923100 ps
T843	/workspace/coverage/default/14.adc_ctrl_fsm_reset.4000203692	Feb 07 01:23:10 PM PST 24	Feb 07 01:28:44 PM PST 24	78724857244 ps
T844	/workspace/coverage/default/9.adc_ctrl_poweron_counter.1107171806	Feb 07 01:20:17 PM PST 24	Feb 07 01:20:27 PM PST 24	4193745172 ps
T845	/workspace/coverage/default/17.adc_ctrl_lowpower_counter.4263677446	Feb 07 01:21:39 PM PST 24	Feb 07 01:23:06 PM PST 24	40003254479 ps
T846	/workspace/coverage/default/25.adc_ctrl_clock_gating.2728129900	Feb 07 01:25:52 PM PST 24	Feb 07 01:28:57 PM PST 24	162407471389 ps
T847	/workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.293096532	Feb 07 01:19:28 PM PST 24	Feb 07 01:23:06 PM PST 24	324695818833 ps
T848	/workspace/coverage/default/3.adc_ctrl_filters_wakeup.1325949633	Feb 07 01:19:05 PM PST 24	Feb 07 01:31:34 PM PST 24	326326912029 ps
T238	/workspace/coverage/default/49.adc_ctrl_filters_wakeup.484169208	Feb 07 01:30:00 PM PST 24	Feb 07 01:33:16 PM PST 24	324487253404 ps
T849	/workspace/coverage/default/20.adc_ctrl_lowpower_counter.2732692930	Feb 07 01:22:34 PM PST 24	Feb 07 01:22:50 PM PST 24	26313064673 ps
T850	/workspace/coverage/default/31.adc_ctrl_clock_gating.2155960578	Feb 07 01:26:54 PM PST 24	Feb 07 01:33:15 PM PST 24	165823876002 ps
T851	/workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3802942006	Feb 07 01:27:55 PM PST 24	Feb 07 01:45:45 PM PST 24	482775412612 ps
T302	/workspace/coverage/default/45.adc_ctrl_clock_gating.2572897035	Feb 07 01:29:18 PM PST 24	Feb 07 01:34:27 PM PST 24	497122252272 ps
T852	/workspace/coverage/default/29.adc_ctrl_fsm_reset.3445118967	Feb 07 01:26:29 PM PST 24	Feb 07 01:32:55 PM PST 24	113824434831 ps
T853	/workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.334408325	Feb 07 01:20:03 PM PST 24	Feb 07 01:23:28 PM PST 24	166484541334 ps
T854	/workspace/coverage/default/4.adc_ctrl_filters_interrupt.2471982601	Feb 07 01:19:28 PM PST 24	Feb 07 01:21:00 PM PST 24	158566609328 ps
T855	/workspace/coverage/default/33.adc_ctrl_filters_polled.1177973390	Feb 07 01:26:59 PM PST 24	Feb 07 01:33:24 PM PST 24	327900147250 ps
T856	/workspace/coverage/default/11.adc_ctrl_fsm_reset.2253641807	Feb 07 01:20:38 PM PST 24	Feb 07 01:28:31 PM PST 24	99257491601 ps
T287	/workspace/coverage/default/7.adc_ctrl_filters_both.1274318393	Feb 07 01:20:07 PM PST 24	Feb 07 01:26:15 PM PST 24	485959434116 ps
T857	/workspace/coverage/default/39.adc_ctrl_filters_wakeup.2092022372	Feb 07 01:28:16 PM PST 24	Feb 07 01:28:44 PM PST 24	162920616320 ps
T858	/workspace/coverage/default/4.adc_ctrl_alert_test.1001466136	Feb 07 01:19:30 PM PST 24	Feb 07 01:19:34 PM PST 24	536936402 ps
T859	/workspace/coverage/default/30.adc_ctrl_stress_all.3950159976	Feb 07 01:26:27 PM PST 24	Feb 07 01:51:40 PM PST 24	690866619935 ps
T860	/workspace/coverage/default/17.adc_ctrl_stress_all.153859342	Feb 07 01:23:07 PM PST 24	Feb 07 01:28:35 PM PST 24	77812726600 ps
T861	/workspace/coverage/default/37.adc_ctrl_alert_test.2341441368	Feb 07 01:27:42 PM PST 24	Feb 07 01:27:43 PM PST 24	420844514 ps
T862	/workspace/coverage/default/6.adc_ctrl_filters_interrupt.725078893	Feb 07 01:19:58 PM PST 24	Feb 07 01:25:12 PM PST 24	479457125127 ps
T863	/workspace/coverage/default/48.adc_ctrl_smoke.2946058991	Feb 07 01:29:55 PM PST 24	Feb 07 01:30:08 PM PST 24	6017118635 ps
T864	/workspace/coverage/default/42.adc_ctrl_filters_polled.3284108888	Feb 07 01:28:53 PM PST 24	Feb 07 01:34:58 PM PST 24	165017996003 ps
T865	/workspace/coverage/default/10.adc_ctrl_lowpower_counter.112445505	Feb 07 01:20:47 PM PST 24	Feb 07 01:22:36 PM PST 24	45067094050 ps
T866	/workspace/coverage/default/32.adc_ctrl_lowpower_counter.2533575747	Feb 07 01:26:59 PM PST 24	Feb 07 01:27:58 PM PST 24	27572929533 ps
T288	/workspace/coverage/default/44.adc_ctrl_clock_gating.1392000173	Feb 07 01:29:15 PM PST 24	Feb 07 01:29:56 PM PST 24	165139559443 ps
T867	/workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.73757225	Feb 07 12:50:44 PM PST 24	Feb 07 12:50:46 PM PST 24	289207265 ps
T868	/workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2843717209	Feb 07 12:50:36 PM PST 24	Feb 07 12:50:38 PM PST 24	454540207 ps
T869	/workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4190840973	Feb 07 12:50:39 PM PST 24	Feb 07 12:50:41 PM PST 24	486495208 ps
T870	/workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.375607204	Feb 07 12:50:41 PM PST 24	Feb 07 12:50:43 PM PST 24	307255121 ps
T318	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3165074633	Feb 07 12:50:29 PM PST 24	Feb 07 12:50:40 PM PST 24	4069196048 ps
T871	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.463303162	Feb 07 12:50:12 PM PST 24	Feb 07 12:50:14 PM PST 24	1283695200 ps
T872	/workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1529978020	Feb 07 12:50:29 PM PST 24	Feb 07 12:50:39 PM PST 24	2613763385 ps
T873	/workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3259490427	Feb 07 12:50:39 PM PST 24	Feb 07 12:50:41 PM PST 24	361507636 ps
T874	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1634894019	Feb 07 12:50:35 PM PST 24	Feb 07 12:50:37 PM PST 24	484152103 ps
T875	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1370057419	Feb 07 12:50:37 PM PST 24	Feb 07 12:50:46 PM PST 24	8691830201 ps
T876	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2437173101	Feb 07 12:50:23 PM PST 24	Feb 07 12:52:34 PM PST 24	52087911337 ps
T877	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3118517444	Feb 07 12:50:15 PM PST 24	Feb 07 12:50:18 PM PST 24	587944300 ps
T878	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1728959168	Feb 07 12:50:32 PM PST 24	Feb 07 12:50:39 PM PST 24	748297074 ps
T879	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.781338867	Feb 07 12:50:16 PM PST 24	Feb 07 12:50:21 PM PST 24	959768152 ps
T880	/workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3418044422	Feb 07 12:50:33 PM PST 24	Feb 07 12:50:37 PM PST 24	4758279220 ps
T881	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1319848402	Feb 07 12:50:28 PM PST 24	Feb 07 12:50:31 PM PST 24	655163791 ps
T882	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2098133328	Feb 07 12:50:33 PM PST 24	Feb 07 12:50:36 PM PST 24	602698302 ps
T883	/workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.686462744	Feb 07 12:50:43 PM PST 24	Feb 07 12:50:46 PM PST 24	482253971 ps
T884	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2144524506	Feb 07 12:50:37 PM PST 24	Feb 07 12:50:39 PM PST 24	607924517 ps
T885	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3128954817	Feb 07 12:50:20 PM PST 24	Feb 07 12:50:23 PM PST 24	798752629 ps
T886	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1697414353	Feb 07 12:50:26 PM PST 24	Feb 07 12:50:39 PM PST 24	4598939805 ps
T887	/workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3042780888	Feb 07 12:50:34 PM PST 24	Feb 07 12:50:36 PM PST 24	539428267 ps
T888	/workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2475605550	Feb 07 12:50:40 PM PST 24	Feb 07 12:50:43 PM PST 24	511201207 ps
T889	/workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1679776154	Feb 07 12:50:33 PM PST 24	Feb 07 12:50:47 PM PST 24	4802173891 ps
T890	/workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2603912914	Feb 07 12:50:39 PM PST 24	Feb 07 12:50:41 PM PST 24	464081791 ps
T891	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2187177015	Feb 07 12:50:33 PM PST 24	Feb 07 12:50:56 PM PST 24	7848401968 ps
T892	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1637955638	Feb 07 12:50:16 PM PST 24	Feb 07 12:50:20 PM PST 24	454480567 ps
T893	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.480580751	Feb 07 12:50:32 PM PST 24	Feb 07 12:50:33 PM PST 24	887462606 ps
T894	/workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4273292626	Feb 07 12:50:41 PM PST 24	Feb 07 12:50:43 PM PST 24	427610534 ps
T895	/workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1060959440	Feb 07 12:50:39 PM PST 24	Feb 07 12:50:41 PM PST 24	324842792 ps
T896	/workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.804133846	Feb 07 12:50:28 PM PST 24	Feb 07 12:50:31 PM PST 24	346970635 ps
T897	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1152068192	Feb 07 12:50:15 PM PST 24	Feb 07 12:50:28 PM PST 24	4252540191 ps
T898	/workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3780178487	Feb 07 12:50:35 PM PST 24	Feb 07 12:50:37 PM PST 24	399015389 ps
T899	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3118705971	Feb 07 12:50:18 PM PST 24	Feb 07 12:50:21 PM PST 24	572428321 ps
T900	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2321010555	Feb 07 12:50:30 PM PST 24	Feb 07 12:50:37 PM PST 24	4375675237 ps
T901	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1465808503	Feb 07 12:50:36 PM PST 24	Feb 07 12:50:38 PM PST 24	483374532 ps
T902	/workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.569537375	Feb 07 12:50:22 PM PST 24	Feb 07 12:50:24 PM PST 24	371974928 ps
T903	/workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2483001192	Feb 07 12:50:44 PM PST 24	Feb 07 12:50:47 PM PST 24	357726665 ps
T904	/workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2733906404	Feb 07 12:50:38 PM PST 24	Feb 07 12:50:40 PM PST 24	497851800 ps
T905	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3997227943	Feb 07 12:50:35 PM PST 24	Feb 07 12:50:38 PM PST 24	1246400946 ps
T906	/workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2949600006	Feb 07 12:50:38 PM PST 24	Feb 07 12:50:44 PM PST 24	2110519846 ps
T907	/workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4100614299	Feb 07 12:50:40 PM PST 24	Feb 07 12:50:44 PM PST 24	513276617 ps
T908	/workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1808791911	Feb 07 12:50:27 PM PST 24	Feb 07 12:50:34 PM PST 24	2212241834 ps
T909	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3224910653	Feb 07 12:50:22 PM PST 24	Feb 07 12:50:24 PM PST 24	459589087 ps
T910	/workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.875807166	Feb 07 12:50:37 PM PST 24	Feb 07 12:50:40 PM PST 24	526644605 ps
T911	/workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2922205465	Feb 07 12:50:25 PM PST 24	Feb 07 12:50:35 PM PST 24	2463074872 ps
T912	/workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3404365565	Feb 07 12:50:42 PM PST 24	Feb 07 12:50:45 PM PST 24	459343253 ps
T913	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.991117852	Feb 07 12:50:31 PM PST 24	Feb 07 12:50:32 PM PST 24	581384347 ps
T914	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2127446583	Feb 07 12:50:37 PM PST 24	Feb 07 12:50:40 PM PST 24	508455145 ps
T915	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1394291872	Feb 07 12:50:35 PM PST 24	Feb 07 12:50:47 PM PST 24	4458562929 ps

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.853296850
Short name	T1
Test name
Test status
Simulation time	463245258 ps
CPU time	1.34 seconds
Started	Feb 07 12:50:22 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	201416 kb
Host	smart-cea64750-0bac-4948-98e4-14eac5c79e59
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853296850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.853296850
Directory	/workspace/3.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2081799391
Short name	T16
Test name
Test status
Simulation time	100330533842 ps
CPU time	125.43 seconds
Started	Feb 07 01:29:28 PM PST 24
Finished	Feb 07 01:31:34 PM PST 24
Peak memory	210264 kb
Host	smart-0b062ec3-65b3-4243-9f81-10ede4de32bb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081799391 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2081799391
Directory	/workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.430929523
Short name	T4
Test name
Test status
Simulation time	4541104487 ps
CPU time	4.31 seconds
Started	Feb 07 12:50:43 PM PST 24
Finished	Feb 07 12:50:49 PM PST 24
Peak memory	201776 kb
Host	smart-86e90505-821a-42f6-86d1-c2645ca2ddcc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430929523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in tg_err.430929523
Directory	/workspace/19.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/8.adc_ctrl_clock_gating.269584639
Short name	T84
Test name
Test status
Simulation time	483136849992 ps
CPU time	1103.99 seconds
Started	Feb 07 01:20:18 PM PST 24
Finished	Feb 07 01:38:43 PM PST 24
Peak memory	201620 kb
Host	smart-1b7300d4-d5a6-4cc8-9d60-a4aaa15a5d02
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269584639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin g.269584639
Directory	/workspace/8.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_both.395827081
Short name	T113
Test name
Test status
Simulation time	484029869428 ps
CPU time	282.09 seconds
Started	Feb 07 01:25:52 PM PST 24
Finished	Feb 07 01:30:36 PM PST 24
Peak memory	201644 kb
Host	smart-3964d676-b7dd-4d9f-a314-df5891141ea1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=395827081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.395827081
Directory	/workspace/25.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_polled.2349717882
Short name	T20
Test name
Test status
Simulation time	486075684107 ps
CPU time	503.63 seconds
Started	Feb 07 01:27:54 PM PST 24
Finished	Feb 07 01:36:24 PM PST 24
Peak memory	201616 kb
Host	smart-5b4e083b-9213-4338-8a1a-14667a228bb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349717882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2349717882
Directory	/workspace/38.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3856518013
Short name	T22
Test name
Test status
Simulation time	434155891 ps
CPU time	1.75 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:42 PM PST 24
Peak memory	201296 kb
Host	smart-3c6bae05-6bac-4433-ad72-8fa982df3d9a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856518013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3856518013
Directory	/workspace/17.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/default/25.adc_ctrl_stress_all.3780622207
Short name	T221
Test name
Test status
Simulation time	552081829028 ps
CPU time	534.02 seconds
Started	Feb 07 01:25:50 PM PST 24
Finished	Feb 07 01:34:48 PM PST 24
Peak memory	201592 kb
Host	smart-7b3be826-b8b0-4f81-9189-96c7a6b0b42a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780622207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all .3780622207
Directory	/workspace/25.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.adc_ctrl_clock_gating.1575542047
Short name	T55
Test name
Test status
Simulation time	489503026198 ps
CPU time	1135.61 seconds
Started	Feb 07 01:20:57 PM PST 24
Finished	Feb 07 01:39:53 PM PST 24
Peak memory	201616 kb
Host	smart-c37254a0-c584-44fe-ad89-c0f4f056b3be
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575542047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat ing.1575542047
Directory	/workspace/14.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_both.1272234882
Short name	T131
Test name
Test status
Simulation time	490189921163 ps
CPU time	1124.69 seconds
Started	Feb 07 01:23:09 PM PST 24
Finished	Feb 07 01:41:55 PM PST 24
Peak memory	201236 kb
Host	smart-a525e006-1add-40d2-8a43-80a72cc66d73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272234882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1272234882
Directory	/workspace/13.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1626264599
Short name	T207
Test name
Test status
Simulation time	417751374414 ps
CPU time	215.98 seconds
Started	Feb 07 01:23:18 PM PST 24
Finished	Feb 07 01:26:54 PM PST 24
Peak memory	210008 kb
Host	smart-45095286-4885-45b2-becd-0a5d1ce3e501
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626264599 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1626264599
Directory	/workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_wakeup.667513256
Short name	T104
Test name
Test status
Simulation time	492892894684 ps
CPU time	1051.93 seconds
Started	Feb 07 01:26:12 PM PST 24
Finished	Feb 07 01:43:46 PM PST 24
Peak memory	201560 kb
Host	smart-68c84a39-ca9a-4b1e-8fa1-927d450b6f7c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667513256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_ wakeup.667513256
Directory	/workspace/28.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_interrupt.3303738433
Short name	T191
Test name
Test status
Simulation time	483521415223 ps
CPU time	328.48 seconds
Started	Feb 07 01:29:15 PM PST 24
Finished	Feb 07 01:34:44 PM PST 24
Peak memory	201580 kb
Host	smart-bb2fdaa2-6bbf-40e7-a5da-08f605b79e1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303738433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3303738433
Directory	/workspace/44.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1355089605
Short name	T92
Test name
Test status
Simulation time	494371850401 ps
CPU time	169.91 seconds
Started	Feb 07 01:23:18 PM PST 24
Finished	Feb 07 01:26:09 PM PST 24
Peak memory	201548 kb
Host	smart-6f3ca2e7-6062-444a-81c3-127cee4ce258
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355089605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru pt_fixed.1355089605
Directory	/workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_both.1654871464
Short name	T109
Test name
Test status
Simulation time	492371340055 ps
CPU time	109.49 seconds
Started	Feb 07 01:26:59 PM PST 24
Finished	Feb 07 01:28:49 PM PST 24
Peak memory	201552 kb
Host	smart-b207903d-5508-4a2d-bb21-441339fba840
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654871464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1654871464
Directory	/workspace/33.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_both.2999942720
Short name	T240
Test name
Test status
Simulation time	331035342531 ps
CPU time	768.33 seconds
Started	Feb 07 01:20:19 PM PST 24
Finished	Feb 07 01:33:08 PM PST 24
Peak memory	201628 kb
Host	smart-76d5bbf5-98f6-4634-ad0a-5cc9e6d46b81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2999942720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2999942720
Directory	/workspace/8.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1450972815
Short name	T58
Test name
Test status
Simulation time	497616551 ps
CPU time	2.86 seconds
Started	Feb 07 12:50:25 PM PST 24
Finished	Feb 07 12:50:29 PM PST 24
Peak memory	209896 kb
Host	smart-0cda26bb-a369-4449-9b2b-561748a28f73
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450972815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1450972815
Directory	/workspace/10.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2974952304
Short name	T95
Test name
Test status
Simulation time	440271306162 ps
CPU time	591.43 seconds
Started	Feb 07 01:30:00 PM PST 24
Finished	Feb 07 01:39:52 PM PST 24
Peak memory	210256 kb
Host	smart-f443a21e-60ae-4d5e-b277-6e271f41dfab
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974952304 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2974952304
Directory	/workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_interrupt.2861147734
Short name	T50
Test name
Test status
Simulation time	492060873397 ps
CPU time	650.36 seconds
Started	Feb 07 01:19:11 PM PST 24
Finished	Feb 07 01:30:02 PM PST 24
Peak memory	201648 kb
Host	smart-fb51b6eb-faee-4b4c-84e6-48bff42bc9f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2861147734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2861147734
Directory	/workspace/1.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/24.adc_ctrl_clock_gating.1674046693
Short name	T233
Test name
Test status
Simulation time	486222693373 ps
CPU time	229.28 seconds
Started	Feb 07 01:25:36 PM PST 24
Finished	Feb 07 01:29:27 PM PST 24
Peak memory	201540 kb
Host	smart-a6dad3f7-5acb-4c7a-8b21-d0aba470a78b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674046693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat ing.1674046693
Directory	/workspace/24.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/17.adc_ctrl_clock_gating.1940585755
Short name	T214
Test name
Test status
Simulation time	504895957870 ps
CPU time	1239.58 seconds
Started	Feb 07 01:21:37 PM PST 24
Finished	Feb 07 01:42:23 PM PST 24
Peak memory	201576 kb
Host	smart-8a6016c8-465b-48d4-b047-9a1e1df6d6d5
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940585755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat ing.1940585755
Directory	/workspace/17.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_both.3804201776
Short name	T99
Test name
Test status
Simulation time	327846150282 ps
CPU time	125.14 seconds
Started	Feb 07 01:19:28 PM PST 24
Finished	Feb 07 01:21:36 PM PST 24
Peak memory	201640 kb
Host	smart-68a3b5a0-7cb1-4a88-99f4-5e8f707fb7cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804201776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3804201776
Directory	/workspace/4.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/29.adc_ctrl_clock_gating.1798077750
Short name	T218
Test name
Test status
Simulation time	326551920712 ps
CPU time	276.31 seconds
Started	Feb 07 01:26:17 PM PST 24
Finished	Feb 07 01:30:54 PM PST 24
Peak memory	201624 kb
Host	smart-3e875f9a-6090-47c2-8553-7966d99c6286
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798077750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat ing.1798077750
Directory	/workspace/29.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/1.adc_ctrl_sec_cm.1101162879
Short name	T39
Test name
Test status
Simulation time	3756691688 ps
CPU time	7.28 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:19:23 PM PST 24
Peak memory	216628 kb
Host	smart-ed8cfc6d-3445-4073-8e29-f01b9cab650c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101162879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1101162879
Directory	/workspace/1.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_both.1013686886
Short name	T200
Test name
Test status
Simulation time	495774980526 ps
CPU time	1243.09 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:39:58 PM PST 24
Peak memory	201596 kb
Host	smart-401be838-bfeb-406e-ab74-ef1ad6b6430a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1013686886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1013686886
Directory	/workspace/1.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/11.adc_ctrl_clock_gating.408856324
Short name	T195
Test name
Test status
Simulation time	492643291890 ps
CPU time	256.62 seconds
Started	Feb 07 01:20:38 PM PST 24
Finished	Feb 07 01:24:55 PM PST 24
Peak memory	201604 kb
Host	smart-fa264393-e87f-4fde-a1b0-d7a9cbbd1874
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408856324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati ng.408856324
Directory	/workspace/11.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2986480397
Short name	T199
Test name
Test status
Simulation time	304748222198 ps
CPU time	209.25 seconds
Started	Feb 07 01:27:20 PM PST 24
Finished	Feb 07 01:30:50 PM PST 24
Peak memory	210328 kb
Host	smart-720b37fe-325a-4429-8657-fe7a415fa2b1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986480397 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2986480397
Directory	/workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_wakeup.1673408662
Short name	T105
Test name
Test status
Simulation time	489752338898 ps
CPU time	169.98 seconds
Started	Feb 07 01:23:18 PM PST 24
Finished	Feb 07 01:26:09 PM PST 24
Peak memory	201624 kb
Host	smart-6d195dd2-04cd-4922-9384-6dc1ccc4da60
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673408662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters _wakeup.1673408662
Directory	/workspace/23.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_both.3272698161
Short name	T259
Test name
Test status
Simulation time	162951244771 ps
CPU time	387 seconds
Started	Feb 07 01:29:15 PM PST 24
Finished	Feb 07 01:35:43 PM PST 24
Peak memory	201608 kb
Host	smart-1cc9f5ae-52df-4116-b08a-1e382cba2564
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272698161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3272698161
Directory	/workspace/44.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/23.adc_ctrl_stress_all.942821637
Short name	T175
Test name
Test status
Simulation time	450289687954 ps
CPU time	532.17 seconds
Started	Feb 07 01:23:33 PM PST 24
Finished	Feb 07 01:32:25 PM PST 24
Peak memory	201884 kb
Host	smart-52079589-0c84-4c93-9770-af92bb91e7ce
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942821637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all. 942821637
Directory	/workspace/23.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.adc_ctrl_clock_gating.1120541702
Short name	T205
Test name
Test status
Simulation time	329062565927 ps
CPU time	205.18 seconds
Started	Feb 07 01:28:23 PM PST 24
Finished	Feb 07 01:31:53 PM PST 24
Peak memory	201572 kb
Host	smart-a446952f-6b9e-439b-95cb-dbf17d31c2d1
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120541702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat ing.1120541702
Directory	/workspace/40.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1463417408
Short name	T91
Test name
Test status
Simulation time	327059698380 ps
CPU time	530.01 seconds
Started	Feb 07 01:23:30 PM PST 24
Finished	Feb 07 01:32:21 PM PST 24
Peak memory	201632 kb
Host	smart-59b7166d-80a3-429b-9fce-3d50eae834db
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463417408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .adc_ctrl_filters_wakeup_fixed.1463417408
Directory	/workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2985012039
Short name	T29
Test name
Test status
Simulation time	23352288655 ps
CPU time	27.09 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:40 PM PST 24
Peak memory	201692 kb
Host	smart-4124b63a-4447-45c4-a7bc-8d4f81dd5bd8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985012039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_ bash.2985012039
Directory	/workspace/3.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_wakeup.355229786
Short name	T126
Test name
Test status
Simulation time	323895777734 ps
CPU time	66.65 seconds
Started	Feb 07 01:20:59 PM PST 24
Finished	Feb 07 01:22:07 PM PST 24
Peak memory	201636 kb
Host	smart-c45a4e67-53b7-4a2c-8622-674d8bd78b55
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355229786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_ wakeup.355229786
Directory	/workspace/14.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_interrupt.1095957074
Short name	T96
Test name
Test status
Simulation time	323980844958 ps
CPU time	732.27 seconds
Started	Feb 07 01:22:52 PM PST 24
Finished	Feb 07 01:35:05 PM PST 24
Peak memory	201556 kb
Host	smart-f377da43-f04a-4e0c-aefc-1e63778929a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095957074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1095957074
Directory	/workspace/21.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_both.907666893
Short name	T188
Test name
Test status
Simulation time	162151668589 ps
CPU time	353.35 seconds
Started	Feb 07 01:26:08 PM PST 24
Finished	Feb 07 01:32:06 PM PST 24
Peak memory	201536 kb
Host	smart-17abe190-91c4-4421-abfe-72963d53aa1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=907666893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.907666893
Directory	/workspace/27.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1269296534
Short name	T291
Test name
Test status
Simulation time	357375068600 ps
CPU time	717.71 seconds
Started	Feb 07 01:23:10 PM PST 24
Finished	Feb 07 01:35:09 PM PST 24
Peak memory	210076 kb
Host	smart-ade5ba24-b29a-49b6-bec3-60751691f9b4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269296534 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1269296534
Directory	/workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.adc_ctrl_clock_gating.3537100069
Short name	T219
Test name
Test status
Simulation time	495151812697 ps
CPU time	255.77 seconds
Started	Feb 07 01:21:55 PM PST 24
Finished	Feb 07 01:26:11 PM PST 24
Peak memory	201456 kb
Host	smart-4d17319a-e219-482a-86e9-ac434f66885f
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537100069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat ing.3537100069
Directory	/workspace/18.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_wakeup.1440247868
Short name	T239
Test name
Test status
Simulation time	500438509638 ps
CPU time	551.45 seconds
Started	Feb 07 01:27:11 PM PST 24
Finished	Feb 07 01:36:23 PM PST 24
Peak memory	201540 kb
Host	smart-5f946b0f-d207-4a8f-a8e1-5a02adaa19d4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440247868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters _wakeup.1440247868
Directory	/workspace/34.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/2.adc_ctrl_clock_gating.3474167666
Short name	T262
Test name
Test status
Simulation time	326009969601 ps
CPU time	612 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:29:27 PM PST 24
Peak memory	201572 kb
Host	smart-7eaaacb7-ed4e-45ad-8780-de87eadd8094
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474167666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati ng.3474167666
Directory	/workspace/2.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.266010408
Short name	T182
Test name
Test status
Simulation time	211550112968 ps
CPU time	150.63 seconds
Started	Feb 07 01:26:59 PM PST 24
Finished	Feb 07 01:29:30 PM PST 24
Peak memory	210256 kb
Host	smart-ba945dd5-df26-4acc-879b-68e38d25f8f5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266010408 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.266010408
Directory	/workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1973578131
Short name	T35
Test name
Test status
Simulation time	340974643 ps
CPU time	2.08 seconds
Started	Feb 07 12:50:21 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	201700 kb
Host	smart-4f6093a2-1eb0-4530-9044-6f3f5543db6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973578131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1973578131
Directory	/workspace/0.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/13.adc_ctrl_stress_all.1346760065
Short name	T112
Test name
Test status
Simulation time	281614138126 ps
CPU time	379.9 seconds
Started	Feb 07 01:21:03 PM PST 24
Finished	Feb 07 01:27:23 PM PST 24
Peak memory	211532 kb
Host	smart-a9f57490-7ef1-4496-893c-8488ce580b14
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346760065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all .1346760065
Directory	/workspace/13.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.adc_ctrl_stress_all.3427859725
Short name	T145
Test name
Test status
Simulation time	670478388951 ps
CPU time	1594.44 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:45:49 PM PST 24
Peak memory	201516 kb
Host	smart-30dc12ed-b14e-44de-b8b8-c149ef6ba3f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427859725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all. 3427859725
Directory	/workspace/2.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_wakeup.926708028
Short name	T123
Test name
Test status
Simulation time	497642909231 ps
CPU time	567.52 seconds
Started	Feb 07 01:23:17 PM PST 24
Finished	Feb 07 01:32:45 PM PST 24
Peak memory	201636 kb
Host	smart-a8c01bf2-fbd7-4f80-b0d0-ad2461fa37a6
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926708028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_ wakeup.926708028
Directory	/workspace/22.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_interrupt.2852071023
Short name	T237
Test name
Test status
Simulation time	486542925261 ps
CPU time	550.63 seconds
Started	Feb 07 01:19:10 PM PST 24
Finished	Feb 07 01:28:21 PM PST 24
Peak memory	201556 kb
Host	smart-3306f8fc-7540-48de-b48d-a65aab806b77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852071023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2852071023
Directory	/workspace/3.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_both.520887679
Short name	T265
Test name
Test status
Simulation time	164297749943 ps
CPU time	205.26 seconds
Started	Feb 07 01:23:19 PM PST 24
Finished	Feb 07 01:26:45 PM PST 24
Peak memory	201656 kb
Host	smart-d9ece0e1-a2b6-4bc2-b705-14dfaf63854f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520887679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.520887679
Directory	/workspace/22.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_wakeup.2929520606
Short name	T301
Test name
Test status
Simulation time	323943249702 ps
CPU time	725.07 seconds
Started	Feb 07 01:28:17 PM PST 24
Finished	Feb 07 01:40:26 PM PST 24
Peak memory	201576 kb
Host	smart-54fec875-7423-41d5-aff1-f93b6f264a13
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929520606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters _wakeup.2929520606
Directory	/workspace/40.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/1.adc_ctrl_clock_gating.4264582739
Short name	T107
Test name
Test status
Simulation time	498618539729 ps
CPU time	413.89 seconds
Started	Feb 07 01:19:11 PM PST 24
Finished	Feb 07 01:26:05 PM PST 24
Peak memory	201700 kb
Host	smart-e18ce5f9-596b-437d-8a70-964c32d4b90b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264582739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati ng.4264582739
Directory	/workspace/1.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/21.adc_ctrl_clock_gating.2127429524
Short name	T281
Test name
Test status
Simulation time	502859199534 ps
CPU time	257.49 seconds
Started	Feb 07 01:22:52 PM PST 24
Finished	Feb 07 01:27:10 PM PST 24
Peak memory	201620 kb
Host	smart-99a244b1-e52f-4bca-8e25-03b2a66fe265
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127429524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat ing.2127429524
Directory	/workspace/21.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/37.adc_ctrl_fsm_reset.132977116
Short name	T179
Test name
Test status
Simulation time	119822813030 ps
CPU time	470.68 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:35:34 PM PST 24
Peak memory	201892 kb
Host	smart-392a048f-37a4-41ee-b36d-15f54c024ff3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132977116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.132977116
Directory	/workspace/37.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/44.adc_ctrl_clock_gating.1392000173
Short name	T288
Test name
Test status
Simulation time	165139559443 ps
CPU time	40.53 seconds
Started	Feb 07 01:29:15 PM PST 24
Finished	Feb 07 01:29:56 PM PST 24
Peak memory	201536 kb
Host	smart-807cf710-b412-4442-9d24-839d337918d8
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392000173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat ing.1392000173
Directory	/workspace/44.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_wakeup.320473808
Short name	T286
Test name
Test status
Simulation time	493045782895 ps
CPU time	1085.87 seconds
Started	Feb 07 01:19:12 PM PST 24
Finished	Feb 07 01:37:18 PM PST 24
Peak memory	201644 kb
Host	smart-1072999a-4517-423f-86b7-502b82bb015e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320473808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w akeup.320473808
Directory	/workspace/1.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_both.1606081957
Short name	T203
Test name
Test status
Simulation time	494350317254 ps
CPU time	257.66 seconds
Started	Feb 07 01:20:50 PM PST 24
Finished	Feb 07 01:25:09 PM PST 24
Peak memory	201624 kb
Host	smart-de447737-423a-41d2-a575-9fefb4aaa7c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606081957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1606081957
Directory	/workspace/11.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_polled.4169449712
Short name	T127
Test name
Test status
Simulation time	325878142655 ps
CPU time	320.52 seconds
Started	Feb 07 01:20:43 PM PST 24
Finished	Feb 07 01:26:05 PM PST 24
Peak memory	201632 kb
Host	smart-d2b2d10c-92f3-486d-87d2-7c2a83acb86f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169449712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4169449712
Directory	/workspace/12.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/32.adc_ctrl_clock_gating.2378344402
Short name	T277
Test name
Test status
Simulation time	168079512853 ps
CPU time	107.91 seconds
Started	Feb 07 01:27:02 PM PST 24
Finished	Feb 07 01:28:51 PM PST 24
Peak memory	201608 kb
Host	smart-d6b67872-703d-4d6c-8277-7a3ec4480141
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378344402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat ing.2378344402
Directory	/workspace/32.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_interrupt.1851523678
Short name	T160
Test name
Test status
Simulation time	318671154485 ps
CPU time	208.47 seconds
Started	Feb 07 01:28:59 PM PST 24
Finished	Feb 07 01:32:29 PM PST 24
Peak memory	201580 kb
Host	smart-7e6fb4fa-c65c-499a-bfc6-c89a825bdd8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851523678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1851523678
Directory	/workspace/43.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_wakeup.484169208
Short name	T238
Test name
Test status
Simulation time	324487253404 ps
CPU time	195.56 seconds
Started	Feb 07 01:30:00 PM PST 24
Finished	Feb 07 01:33:16 PM PST 24
Peak memory	201696 kb
Host	smart-a2d981d0-8747-4d9d-8f44-a031dc25753a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484169208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_ wakeup.484169208
Directory	/workspace/49.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/12.adc_ctrl_alert_test.1573859038
Short name	T438
Test name
Test status
Simulation time	468686368 ps
CPU time	0.81 seconds
Started	Feb 07 01:20:44 PM PST 24
Finished	Feb 07 01:20:46 PM PST 24
Peak memory	201200 kb
Host	smart-17683515-10f5-4599-8813-48d0b9772996
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573859038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1573859038
Directory	/workspace/12.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_interrupt.4017572907
Short name	T156
Test name
Test status
Simulation time	488135352332 ps
CPU time	255.79 seconds
Started	Feb 07 01:20:40 PM PST 24
Finished	Feb 07 01:24:57 PM PST 24
Peak memory	201640 kb
Host	smart-733fe947-46f9-4cfa-a958-bce0e67e66b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017572907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.4017572907
Directory	/workspace/11.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_interrupt.3439138847
Short name	T308
Test name
Test status
Simulation time	494742405088 ps
CPU time	1111.14 seconds
Started	Feb 07 01:23:12 PM PST 24
Finished	Feb 07 01:41:43 PM PST 24
Peak memory	201596 kb
Host	smart-3efb80fb-1a0f-4576-84c4-7dfe65596df2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3439138847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3439138847
Directory	/workspace/22.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/45.adc_ctrl_fsm_reset.1761382565
Short name	T166
Test name
Test status
Simulation time	102380263602 ps
CPU time	409.69 seconds
Started	Feb 07 01:29:25 PM PST 24
Finished	Feb 07 01:36:15 PM PST 24
Peak memory	201876 kb
Host	smart-29f7a9f1-50ca-47c7-b9ce-5be90710a68f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761382565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1761382565
Directory	/workspace/45.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_both.1457309786
Short name	T223
Test name
Test status
Simulation time	487296479864 ps
CPU time	87.29 seconds
Started	Feb 07 01:19:55 PM PST 24
Finished	Feb 07 01:21:23 PM PST 24
Peak memory	201700 kb
Host	smart-b4a77afb-27a8-4af8-bcf9-9921c5499208
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457309786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1457309786
Directory	/workspace/5.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_wakeup.1183739706
Short name	T293
Test name
Test status
Simulation time	341809942708 ps
CPU time	767.62 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:33:05 PM PST 24
Peak memory	201496 kb
Host	smart-48e468ea-c88c-4752-bddd-9fc1bdaed264
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183739706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_ wakeup.1183739706
Directory	/workspace/9.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3395770507
Short name	T3
Test name
Test status
Simulation time	7792982324 ps
CPU time	21.61 seconds
Started	Feb 07 12:50:28 PM PST 24
Finished	Feb 07 12:50:50 PM PST 24
Peak memory	201724 kb
Host	smart-4819c925-f03f-4243-92d3-68efc431b23e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395770507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i ntg_err.3395770507
Directory	/workspace/13.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.966332912
Short name	T164
Test name
Test status
Simulation time	557209386 ps
CPU time	0.99 seconds
Started	Feb 07 12:50:11 PM PST 24
Finished	Feb 07 12:50:14 PM PST 24
Peak memory	201208 kb
Host	smart-488442ce-927d-4e92-82b0-8b4a5a46f39e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966332912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.966332912
Directory	/workspace/1.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_interrupt.3423362238
Short name	T289
Test name
Test status
Simulation time	497721964176 ps
CPU time	459.85 seconds
Started	Feb 07 01:19:10 PM PST 24
Finished	Feb 07 01:26:50 PM PST 24
Peak memory	201560 kb
Host	smart-fa2b9362-c68e-48e3-940b-b5194126a8c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423362238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3423362238
Directory	/workspace/0.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.751891131
Short name	T211
Test name
Test status
Simulation time	97551289574 ps
CPU time	108.99 seconds
Started	Feb 07 01:22:33 PM PST 24
Finished	Feb 07 01:24:23 PM PST 24
Peak memory	210248 kb
Host	smart-4b5cce73-d62b-47b9-9b64-35c870c541c3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751891131 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.751891131
Directory	/workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_both.36033703
Short name	T202
Test name
Test status
Simulation time	488687812781 ps
CPU time	621.31 seconds
Started	Feb 07 01:22:53 PM PST 24
Finished	Feb 07 01:33:14 PM PST 24
Peak memory	201508 kb
Host	smart-e904a281-76ff-4d96-a6ca-bf957580438b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36033703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.36033703
Directory	/workspace/21.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_polled.1826150505
Short name	T151
Test name
Test status
Simulation time	494709238289 ps
CPU time	270.53 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:30:05 PM PST 24
Peak memory	201636 kb
Host	smart-b6019042-ee4a-4b27-966b-0c8878066b9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826150505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1826150505
Directory	/workspace/25.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_polled.537021446
Short name	T245
Test name
Test status
Simulation time	328553972013 ps
CPU time	744.26 seconds
Started	Feb 07 01:26:13 PM PST 24
Finished	Feb 07 01:38:38 PM PST 24
Peak memory	201604 kb
Host	smart-8ed36cbf-31a9-4567-ba55-2cde7a796aef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537021446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.537021446
Directory	/workspace/27.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/28.adc_ctrl_clock_gating.1764468360
Short name	T206
Test name
Test status
Simulation time	162853845853 ps
CPU time	195.03 seconds
Started	Feb 07 01:26:03 PM PST 24
Finished	Feb 07 01:29:19 PM PST 24
Peak memory	201536 kb
Host	smart-6664c865-02d8-40fe-86f6-a9afceacf5d4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764468360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat ing.1764468360
Directory	/workspace/28.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/31.adc_ctrl_fsm_reset.1570211936
Short name	T742
Test name
Test status
Simulation time	101459097367 ps
CPU time	521.22 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:35:39 PM PST 24
Peak memory	201888 kb
Host	smart-320979bf-0bc9-49f4-bd24-be6feb42d648
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570211936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1570211936
Directory	/workspace/31.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/4.adc_ctrl_clock_gating.1019130976
Short name	T210
Test name
Test status
Simulation time	484682921744 ps
CPU time	993.22 seconds
Started	Feb 07 01:19:30 PM PST 24
Finished	Feb 07 01:36:06 PM PST 24
Peak memory	201540 kb
Host	smart-94982c86-1b61-4392-8aab-50a353543a10
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019130976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati ng.1019130976
Directory	/workspace/4.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_both.588310027
Short name	T121
Test name
Test status
Simulation time	163428236630 ps
CPU time	363.24 seconds
Started	Feb 07 01:20:21 PM PST 24
Finished	Feb 07 01:26:25 PM PST 24
Peak memory	201596 kb
Host	smart-24ed1ed2-f69a-4482-8c24-441e0879bc7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588310027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.588310027
Directory	/workspace/9.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3207625526
Short name	T317
Test name
Test status
Simulation time	8206434192 ps
CPU time	5.86 seconds
Started	Feb 07 12:50:20 PM PST 24
Finished	Feb 07 12:50:26 PM PST 24
Peak memory	201756 kb
Host	smart-c960234c-2834-4dfe-bf5c-a721d2e72620
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207625526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in tg_err.3207625526
Directory	/workspace/0.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.adc_ctrl_clock_gating.3437242429
Short name	T119
Test name
Test status
Simulation time	487931760810 ps
CPU time	185.56 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:23:24 PM PST 24
Peak memory	201524 kb
Host	smart-cf787188-8990-42ad-990d-ff13f96cecd3
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437242429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat ing.3437242429
Directory	/workspace/10.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/19.adc_ctrl_fsm_reset.2679430098
Short name	T181
Test name
Test status
Simulation time	83460727981 ps
CPU time	337.92 seconds
Started	Feb 07 01:22:36 PM PST 24
Finished	Feb 07 01:28:14 PM PST 24
Peak memory	201992 kb
Host	smart-32327c88-8b55-4170-9aef-2c64ebc48ea7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679430098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2679430098
Directory	/workspace/19.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_both.2857198725
Short name	T260
Test name
Test status
Simulation time	326022437017 ps
CPU time	211.13 seconds
Started	Feb 07 01:23:30 PM PST 24
Finished	Feb 07 01:27:02 PM PST 24
Peak memory	201664 kb
Host	smart-10ffe44b-8e28-4ede-ac71-0f8628ba12b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857198725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2857198725
Directory	/workspace/23.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/23.adc_ctrl_fsm_reset.2439076680
Short name	T180
Test name
Test status
Simulation time	87556509456 ps
CPU time	308.65 seconds
Started	Feb 07 01:23:33 PM PST 24
Finished	Feb 07 01:28:43 PM PST 24
Peak memory	201972 kb
Host	smart-568e83f2-a494-46bb-8cb7-fcfbcb7902b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439076680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2439076680
Directory	/workspace/23.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/36.adc_ctrl_clock_gating.131142128
Short name	T15
Test name
Test status
Simulation time	163487085554 ps
CPU time	15.6 seconds
Started	Feb 07 01:27:37 PM PST 24
Finished	Feb 07 01:27:53 PM PST 24
Peak memory	201532 kb
Host	smart-8e5d85d8-fa3a-42f1-8bb2-2604f834d0f5
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131142128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati ng.131142128
Directory	/workspace/36.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.419569600
Short name	T300
Test name
Test status
Simulation time	287267761178 ps
CPU time	239.91 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:31:43 PM PST 24
Peak memory	210276 kb
Host	smart-eb58b4c2-9c0e-43a9-aeb6-c090abce499d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419569600 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.419569600
Directory	/workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.adc_ctrl_clock_gating.1839308064
Short name	T226
Test name
Test status
Simulation time	492051468462 ps
CPU time	784.88 seconds
Started	Feb 07 01:27:54 PM PST 24
Finished	Feb 07 01:41:05 PM PST 24
Peak memory	201588 kb
Host	smart-41ae264d-9a49-40d3-a3f6-cee565b0bc90
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839308064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat ing.1839308064
Directory	/workspace/38.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4280747422
Short name	T236
Test name
Test status
Simulation time	54414296749 ps
CPU time	117.12 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:30:18 PM PST 24
Peak memory	201784 kb
Host	smart-c9f05f3d-83d2-4c4f-89e4-ecc255ed2199
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280747422 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.4280747422
Directory	/workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.adc_ctrl_clock_gating.2572897035
Short name	T302
Test name
Test status
Simulation time	497122252272 ps
CPU time	308.54 seconds
Started	Feb 07 01:29:18 PM PST 24
Finished	Feb 07 01:34:27 PM PST 24
Peak memory	201588 kb
Host	smart-35e2dce4-9106-4326-8e79-3b49c55f93ff
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572897035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat ing.2572897035
Directory	/workspace/45.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_both.1274318393
Short name	T287
Test name
Test status
Simulation time	485959434116 ps
CPU time	366.75 seconds
Started	Feb 07 01:20:07 PM PST 24
Finished	Feb 07 01:26:15 PM PST 24
Peak memory	201648 kb
Host	smart-5431c3ad-bbce-47d3-b398-e9ba4e61fe49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274318393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1274318393
Directory	/workspace/7.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1329252620
Short name	T65
Test name
Test status
Simulation time	911542305 ps
CPU time	1.87 seconds
Started	Feb 07 12:50:24 PM PST 24
Finished	Feb 07 12:50:27 PM PST 24
Peak memory	201668 kb
Host	smart-6cd9dd7c-5e12-45d9-b599-4add9b5ac336
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329252620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia sing.1329252620
Directory	/workspace/0.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2823180253
Short name	T369
Test name
Test status
Simulation time	26072737064 ps
CPU time	12.61 seconds
Started	Feb 07 12:50:23 PM PST 24
Finished	Feb 07 12:50:37 PM PST 24
Peak memory	201696 kb
Host	smart-5c7efa37-cc4f-458f-83e6-4da37cdbec17
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823180253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_ bash.2823180253
Directory	/workspace/0.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1221844469
Short name	T32
Test name
Test status
Simulation time	979484610 ps
CPU time	0.95 seconds
Started	Feb 07 12:50:20 PM PST 24
Finished	Feb 07 12:50:21 PM PST 24
Peak memory	201408 kb
Host	smart-3a5f7267-3917-485a-ba4d-078e03182e4c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221844469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r eset.1221844469
Directory	/workspace/0.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3828967512
Short name	T385
Test name
Test status
Simulation time	423237644 ps
CPU time	1.62 seconds
Started	Feb 07 12:50:19 PM PST 24
Finished	Feb 07 12:50:21 PM PST 24
Peak memory	201472 kb
Host	smart-400fdbda-194f-4118-b827-5abed6221ea9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828967512 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3828967512
Directory	/workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2623273557
Short name	T72
Test name
Test status
Simulation time	469907495 ps
CPU time	1.34 seconds
Started	Feb 07 12:50:19 PM PST 24
Finished	Feb 07 12:50:21 PM PST 24
Peak memory	201384 kb
Host	smart-7d3b22bd-ba9a-4cc6-84f5-f0d3ba8079dd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623273557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2623273557
Directory	/workspace/0.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.569537375
Short name	T902
Test name
Test status
Simulation time	371974928 ps
CPU time	1.44 seconds
Started	Feb 07 12:50:22 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	201156 kb
Host	smart-557302ec-d767-4730-8261-f8d00877bb5e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569537375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.569537375
Directory	/workspace/0.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4156486733
Short name	T374
Test name
Test status
Simulation time	4470890845 ps
CPU time	5.65 seconds
Started	Feb 07 12:50:21 PM PST 24
Finished	Feb 07 12:50:27 PM PST 24
Peak memory	201744 kb
Host	smart-8b94df84-07ed-48c4-a5b9-22229047d2ed
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156486733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c trl_same_csr_outstanding.4156486733
Directory	/workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1760764556
Short name	T66
Test name
Test status
Simulation time	627492073 ps
CPU time	3.11 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:20 PM PST 24
Peak memory	201676 kb
Host	smart-894cff6d-3937-41a4-9e2f-ec1f4626bd31
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760764556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia sing.1760764556
Directory	/workspace/1.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3392032171
Short name	T2
Test name
Test status
Simulation time	52594874294 ps
CPU time	40.56 seconds
Started	Feb 07 12:50:18 PM PST 24
Finished	Feb 07 12:50:59 PM PST 24
Peak memory	201708 kb
Host	smart-e8df0f19-fada-4ecc-9bc2-27f3eafff0d5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392032171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_ bash.3392032171
Directory	/workspace/1.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.781338867
Short name	T879
Test name
Test status
Simulation time	959768152 ps
CPU time	2.74 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:21 PM PST 24
Peak memory	201328 kb
Host	smart-20f3e6c4-c1dc-4171-b58c-675cf22c8658
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781338867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re set.781338867
Directory	/workspace/1.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3224910653
Short name	T909
Test name
Test status
Simulation time	459589087 ps
CPU time	1.5 seconds
Started	Feb 07 12:50:22 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	201480 kb
Host	smart-f16c5eb1-bbc2-4761-b2b8-8722ae658fac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224910653 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3224910653
Directory	/workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3960908996
Short name	T335
Test name
Test status
Simulation time	444236913 ps
CPU time	1.51 seconds
Started	Feb 07 12:50:17 PM PST 24
Finished	Feb 07 12:50:20 PM PST 24
Peak memory	201396 kb
Host	smart-e3724a78-5263-4e5e-9098-0c0f8dddd9eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960908996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3960908996
Directory	/workspace/1.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1403832295
Short name	T163
Test name
Test status
Simulation time	2675720355 ps
CPU time	9.22 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:26 PM PST 24
Peak memory	201528 kb
Host	smart-7c4d9141-e357-4add-a33a-e3747d5af295
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403832295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c trl_same_csr_outstanding.1403832295
Directory	/workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1637955638
Short name	T892
Test name
Test status
Simulation time	454480567 ps
CPU time	2.2 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:20 PM PST 24
Peak memory	201768 kb
Host	smart-56e08675-49bc-4eea-8b60-7d2d0fe01428
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637955638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1637955638
Directory	/workspace/1.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.973014069
Short name	T9
Test name
Test status
Simulation time	8405671604 ps
CPU time	11.59 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	201684 kb
Host	smart-a00badca-38df-478e-948d-20ff5ae96a72
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973014069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int g_err.973014069
Directory	/workspace/1.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.480580751
Short name	T893
Test name
Test status
Simulation time	887462606 ps
CPU time	0.99 seconds
Started	Feb 07 12:50:32 PM PST 24
Finished	Feb 07 12:50:33 PM PST 24
Peak memory	201420 kb
Host	smart-ba3b5e49-1391-44c7-a65f-40cf0716743f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480580751 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.480580751
Directory	/workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2776380803
Short name	T70
Test name
Test status
Simulation time	370398839 ps
CPU time	1.57 seconds
Started	Feb 07 12:50:32 PM PST 24
Finished	Feb 07 12:50:35 PM PST 24
Peak memory	201424 kb
Host	smart-b1029464-443e-491d-a47e-fa20068f8c65
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776380803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2776380803
Directory	/workspace/10.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.804133846
Short name	T896
Test name
Test status
Simulation time	346970635 ps
CPU time	1.44 seconds
Started	Feb 07 12:50:28 PM PST 24
Finished	Feb 07 12:50:31 PM PST 24
Peak memory	201412 kb
Host	smart-56b5fae5-d1d9-49e0-96bd-153343aa88f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804133846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.804133846
Directory	/workspace/10.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3418044422
Short name	T880
Test name
Test status
Simulation time	4758279220 ps
CPU time	3.56 seconds
Started	Feb 07 12:50:33 PM PST 24
Finished	Feb 07 12:50:37 PM PST 24
Peak memory	201712 kb
Host	smart-d84eccbb-6509-4b5a-9262-22a6ac663ca9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418044422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ ctrl_same_csr_outstanding.3418044422
Directory	/workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1439089562
Short name	T345
Test name
Test status
Simulation time	4695514785 ps
CPU time	12.16 seconds
Started	Feb 07 12:50:25 PM PST 24
Finished	Feb 07 12:50:38 PM PST 24
Peak memory	201748 kb
Host	smart-127f3570-dfa9-43b7-af07-8e2d1f3222ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439089562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i ntg_err.1439089562
Directory	/workspace/10.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2941270310
Short name	T383
Test name
Test status
Simulation time	531500910 ps
CPU time	1.29 seconds
Started	Feb 07 12:50:26 PM PST 24
Finished	Feb 07 12:50:28 PM PST 24
Peak memory	201696 kb
Host	smart-f5e09fb0-da7d-46f5-aea8-747ab6896610
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941270310 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2941270310
Directory	/workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4038326678
Short name	T377
Test name
Test status
Simulation time	388862450 ps
CPU time	1.12 seconds
Started	Feb 07 12:50:27 PM PST 24
Finished	Feb 07 12:50:29 PM PST 24
Peak memory	201176 kb
Host	smart-6bde0c27-e0d1-4898-a18e-2ae28b31a062
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038326678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.4038326678
Directory	/workspace/11.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.912411857
Short name	T350
Test name
Test status
Simulation time	304184570 ps
CPU time	1.01 seconds
Started	Feb 07 12:50:25 PM PST 24
Finished	Feb 07 12:50:27 PM PST 24
Peak memory	201376 kb
Host	smart-0f7b153f-420d-439f-b698-d742cb5bb11c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912411857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.912411857
Directory	/workspace/11.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1808791911
Short name	T908
Test name
Test status
Simulation time	2212241834 ps
CPU time	5.71 seconds
Started	Feb 07 12:50:27 PM PST 24
Finished	Feb 07 12:50:34 PM PST 24
Peak memory	201300 kb
Host	smart-9aaa310b-1039-413b-9b88-77d93c3bf44a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808791911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ ctrl_same_csr_outstanding.1808791911
Directory	/workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2098133328
Short name	T882
Test name
Test status
Simulation time	602698302 ps
CPU time	1.49 seconds
Started	Feb 07 12:50:33 PM PST 24
Finished	Feb 07 12:50:36 PM PST 24
Peak memory	201640 kb
Host	smart-9b4b1588-6953-412b-b7f3-72629f9ada7f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098133328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2098133328
Directory	/workspace/11.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1697414353
Short name	T886
Test name
Test status
Simulation time	4598939805 ps
CPU time	11.22 seconds
Started	Feb 07 12:50:26 PM PST 24
Finished	Feb 07 12:50:39 PM PST 24
Peak memory	201756 kb
Host	smart-fdd67960-b594-474e-9d47-03aa6a92f681
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697414353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i ntg_err.1697414353
Directory	/workspace/11.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.991117852
Short name	T913
Test name
Test status
Simulation time	581384347 ps
CPU time	1.11 seconds
Started	Feb 07 12:50:31 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	201456 kb
Host	smart-6c722971-4b61-480c-897f-23226044c21a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991117852 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.991117852
Directory	/workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3282055155
Short name	T31
Test name
Test status
Simulation time	299863626 ps
CPU time	1.44 seconds
Started	Feb 07 12:50:33 PM PST 24
Finished	Feb 07 12:50:36 PM PST 24
Peak memory	201296 kb
Host	smart-f4eaf2f4-0187-463c-b82e-140a1f8632a6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282055155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3282055155
Directory	/workspace/12.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1060959440
Short name	T895
Test name
Test status
Simulation time	324842792 ps
CPU time	1.34 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201188 kb
Host	smart-fe2afe25-2834-4ee7-b2bb-20d8a7f9c8d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060959440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1060959440
Directory	/workspace/12.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2516016166
Short name	T75
Test name
Test status
Simulation time	5107064247 ps
CPU time	17.82 seconds
Started	Feb 07 12:50:32 PM PST 24
Finished	Feb 07 12:50:51 PM PST 24
Peak memory	201792 kb
Host	smart-25c1d4bf-6194-4c78-ac6d-5e968a42b1be
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516016166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ ctrl_same_csr_outstanding.2516016166
Directory	/workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4281099159
Short name	T34
Test name
Test status
Simulation time	399010473 ps
CPU time	2.71 seconds
Started	Feb 07 12:50:28 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	201736 kb
Host	smart-0fff97a1-24f3-469f-a91b-8f59f82e4987
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281099159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4281099159
Directory	/workspace/12.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2200320530
Short name	T361
Test name
Test status
Simulation time	4459945216 ps
CPU time	11.8 seconds
Started	Feb 07 12:50:27 PM PST 24
Finished	Feb 07 12:50:40 PM PST 24
Peak memory	201788 kb
Host	smart-2b57f1d8-5149-48e7-a496-2ef34cb05a8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200320530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i ntg_err.2200320530
Directory	/workspace/12.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1728959168
Short name	T878
Test name
Test status
Simulation time	748297074 ps
CPU time	1.03 seconds
Started	Feb 07 12:50:32 PM PST 24
Finished	Feb 07 12:50:39 PM PST 24
Peak memory	201492 kb
Host	smart-b5e707dd-69ef-49cb-b245-576a2abd3a90
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728959168 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1728959168
Directory	/workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.297621524
Short name	T73
Test name
Test status
Simulation time	543162236 ps
CPU time	0.93 seconds
Started	Feb 07 12:50:32 PM PST 24
Finished	Feb 07 12:50:34 PM PST 24
Peak memory	201404 kb
Host	smart-7f606221-4550-4ade-859e-b3c1b8e5968a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297621524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.297621524
Directory	/workspace/13.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3600175467
Short name	T375
Test name
Test status
Simulation time	556109847 ps
CPU time	0.9 seconds
Started	Feb 07 12:50:32 PM PST 24
Finished	Feb 07 12:50:34 PM PST 24
Peak memory	201208 kb
Host	smart-17c7f4fd-b902-47e8-bb16-be9fbe255a52
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600175467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3600175467
Directory	/workspace/13.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3174052787
Short name	T74
Test name
Test status
Simulation time	5089693237 ps
CPU time	10.89 seconds
Started	Feb 07 12:50:32 PM PST 24
Finished	Feb 07 12:50:44 PM PST 24
Peak memory	201796 kb
Host	smart-3558360b-f312-4c5e-849a-27862beb5c1e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174052787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ ctrl_same_csr_outstanding.3174052787
Directory	/workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3248821761
Short name	T352
Test name
Test status
Simulation time	693700524 ps
CPU time	1.7 seconds
Started	Feb 07 12:50:30 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	217480 kb
Host	smart-0b039537-fad3-40a9-9bbe-0f209c026a82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248821761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3248821761
Directory	/workspace/13.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1634894019
Short name	T874
Test name
Test status
Simulation time	484152103 ps
CPU time	1.02 seconds
Started	Feb 07 12:50:35 PM PST 24
Finished	Feb 07 12:50:37 PM PST 24
Peak memory	201488 kb
Host	smart-f200c1e1-1699-45b7-8924-71f5785d9e02
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634894019 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1634894019
Directory	/workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.960496705
Short name	T357
Test name
Test status
Simulation time	443979043 ps
CPU time	1.06 seconds
Started	Feb 07 12:50:30 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	201440 kb
Host	smart-37451f53-0924-47bc-927e-8ea6caa726bd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960496705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.960496705
Directory	/workspace/14.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2576145212
Short name	T340
Test name
Test status
Simulation time	508007847 ps
CPU time	1.22 seconds
Started	Feb 07 12:50:29 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	201392 kb
Host	smart-4c20aa09-6463-4f3f-a501-39a3c47b433a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576145212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2576145212
Directory	/workspace/14.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1529978020
Short name	T872
Test name
Test status
Simulation time	2613763385 ps
CPU time	8.28 seconds
Started	Feb 07 12:50:29 PM PST 24
Finished	Feb 07 12:50:39 PM PST 24
Peak memory	201524 kb
Host	smart-dc046b2c-dd14-46a3-90aa-ead9bb2b95ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529978020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ ctrl_same_csr_outstanding.1529978020
Directory	/workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3997227943
Short name	T905
Test name
Test status
Simulation time	1246400946 ps
CPU time	2.53 seconds
Started	Feb 07 12:50:35 PM PST 24
Finished	Feb 07 12:50:38 PM PST 24
Peak memory	201712 kb
Host	smart-2ec6ad0f-09fe-4fb9-9bb1-2791c5608973
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997227943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3997227943
Directory	/workspace/14.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3165074633
Short name	T318
Test name
Test status
Simulation time	4069196048 ps
CPU time	10.09 seconds
Started	Feb 07 12:50:29 PM PST 24
Finished	Feb 07 12:50:40 PM PST 24
Peak memory	201732 kb
Host	smart-3ee9813b-73db-410e-9595-84a1e28f6b6d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165074633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i ntg_err.3165074633
Directory	/workspace/14.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1465808503
Short name	T901
Test name
Test status
Simulation time	483374532 ps
CPU time	1.1 seconds
Started	Feb 07 12:50:36 PM PST 24
Finished	Feb 07 12:50:38 PM PST 24
Peak memory	201416 kb
Host	smart-296f2271-0ac1-49d6-a73c-47b928f987b3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465808503 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1465808503
Directory	/workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2706913583
Short name	T62
Test name
Test status
Simulation time	347477077 ps
CPU time	1.14 seconds
Started	Feb 07 12:50:26 PM PST 24
Finished	Feb 07 12:50:28 PM PST 24
Peak memory	201396 kb
Host	smart-cca6b007-269d-4256-8368-9c793fd41d78
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706913583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2706913583
Directory	/workspace/15.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2843717209
Short name	T868
Test name
Test status
Simulation time	454540207 ps
CPU time	0.86 seconds
Started	Feb 07 12:50:36 PM PST 24
Finished	Feb 07 12:50:38 PM PST 24
Peak memory	201112 kb
Host	smart-3b31e9df-0570-4d03-82ed-ce938c9ff17b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843717209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2843717209
Directory	/workspace/15.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1679776154
Short name	T889
Test name
Test status
Simulation time	4802173891 ps
CPU time	14.08 seconds
Started	Feb 07 12:50:33 PM PST 24
Finished	Feb 07 12:50:47 PM PST 24
Peak memory	201772 kb
Host	smart-7e39a897-5124-411d-a973-ae8a95f7ea37
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679776154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ ctrl_same_csr_outstanding.1679776154
Directory	/workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3795591149
Short name	T162
Test name
Test status
Simulation time	618277878 ps
CPU time	1.48 seconds
Started	Feb 07 12:50:35 PM PST 24
Finished	Feb 07 12:50:37 PM PST 24
Peak memory	201716 kb
Host	smart-c51f4862-e58e-460b-86a6-32e803aa2f47
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795591149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3795591149
Directory	/workspace/15.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2187177015
Short name	T891
Test name
Test status
Simulation time	7848401968 ps
CPU time	21.34 seconds
Started	Feb 07 12:50:33 PM PST 24
Finished	Feb 07 12:50:56 PM PST 24
Peak memory	201600 kb
Host	smart-693c1f1f-cecc-46d6-ae15-dcc036a94aa5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187177015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i ntg_err.2187177015
Directory	/workspace/15.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1823244120
Short name	T326
Test name
Test status
Simulation time	548646678 ps
CPU time	1.35 seconds
Started	Feb 07 12:50:44 PM PST 24
Finished	Feb 07 12:50:47 PM PST 24
Peak memory	201464 kb
Host	smart-67f527b4-53db-41d2-988f-1dadf0fa2342
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823244120 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1823244120
Directory	/workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2144524506
Short name	T884
Test name
Test status
Simulation time	607924517 ps
CPU time	1.09 seconds
Started	Feb 07 12:50:37 PM PST 24
Finished	Feb 07 12:50:39 PM PST 24
Peak memory	201368 kb
Host	smart-1972a7b3-1834-485d-b175-0e04a9cee8ce
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144524506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2144524506
Directory	/workspace/16.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2475605550
Short name	T888
Test name
Test status
Simulation time	511201207 ps
CPU time	0.98 seconds
Started	Feb 07 12:50:40 PM PST 24
Finished	Feb 07 12:50:43 PM PST 24
Peak memory	201468 kb
Host	smart-137e1a98-b4cf-4703-9c19-00fc7642ca76
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475605550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2475605550
Directory	/workspace/16.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.147058890
Short name	T367
Test name
Test status
Simulation time	4863389683 ps
CPU time	3.76 seconds
Started	Feb 07 12:50:36 PM PST 24
Finished	Feb 07 12:50:40 PM PST 24
Peak memory	201752 kb
Host	smart-5bc131d4-c8e4-4477-8dfd-201534e02ec8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147058890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c trl_same_csr_outstanding.147058890
Directory	/workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3396298753
Short name	T56
Test name
Test status
Simulation time	481345891 ps
CPU time	1.57 seconds
Started	Feb 07 12:50:28 PM PST 24
Finished	Feb 07 12:50:31 PM PST 24
Peak memory	201616 kb
Host	smart-4594da0c-3dee-490c-8342-ab74f222cd36
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396298753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3396298753
Directory	/workspace/16.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1394291872
Short name	T915
Test name
Test status
Simulation time	4458562929 ps
CPU time	11.43 seconds
Started	Feb 07 12:50:35 PM PST 24
Finished	Feb 07 12:50:47 PM PST 24
Peak memory	201780 kb
Host	smart-43559749-a15a-4677-af7f-9e35678cff2a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394291872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i ntg_err.1394291872
Directory	/workspace/16.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2084838337
Short name	T324
Test name
Test status
Simulation time	580593709 ps
CPU time	1.42 seconds
Started	Feb 07 12:50:42 PM PST 24
Finished	Feb 07 12:50:45 PM PST 24
Peak memory	201360 kb
Host	smart-466d7a27-cd5b-43dd-95f9-c0a8530dd6cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084838337 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2084838337
Directory	/workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.112715792
Short name	T69
Test name
Test status
Simulation time	523040839 ps
CPU time	1.02 seconds
Started	Feb 07 12:50:43 PM PST 24
Finished	Feb 07 12:50:46 PM PST 24
Peak memory	201364 kb
Host	smart-547af5ec-f17c-425a-a1f5-2c57165dcdaf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112715792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.112715792
Directory	/workspace/17.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2949600006
Short name	T906
Test name
Test status
Simulation time	2110519846 ps
CPU time	5.04 seconds
Started	Feb 07 12:50:38 PM PST 24
Finished	Feb 07 12:50:44 PM PST 24
Peak memory	201416 kb
Host	smart-2c92678f-a2ec-48de-8cf3-fc588c27a9e2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949600006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ ctrl_same_csr_outstanding.2949600006
Directory	/workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1597483140
Short name	T381
Test name
Test status
Simulation time	859050133 ps
CPU time	2.38 seconds
Started	Feb 07 12:50:35 PM PST 24
Finished	Feb 07 12:50:38 PM PST 24
Peak memory	209924 kb
Host	smart-9bd82a6f-2a2c-4f18-a390-7682076551ec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597483140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1597483140
Directory	/workspace/17.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.135689098
Short name	T353
Test name
Test status
Simulation time	8653613885 ps
CPU time	11.74 seconds
Started	Feb 07 12:50:44 PM PST 24
Finished	Feb 07 12:50:57 PM PST 24
Peak memory	201800 kb
Host	smart-b1bc2bf1-5f60-4922-9dcd-1d1176691f86
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135689098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in tg_err.135689098
Directory	/workspace/17.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3797090699
Short name	T330
Test name
Test status
Simulation time	354910043 ps
CPU time	0.95 seconds
Started	Feb 07 12:50:35 PM PST 24
Finished	Feb 07 12:50:37 PM PST 24
Peak memory	201396 kb
Host	smart-9e897884-8ea3-4b3c-b464-60b29cdbb92b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797090699 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3797090699
Directory	/workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1689994059
Short name	T6
Test name
Test status
Simulation time	459449982 ps
CPU time	1.04 seconds
Started	Feb 07 12:50:36 PM PST 24
Finished	Feb 07 12:50:38 PM PST 24
Peak memory	201416 kb
Host	smart-cbf9fa46-c6e1-459f-9654-27bf81db51c5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689994059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1689994059
Directory	/workspace/18.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2733906404
Short name	T904
Test name
Test status
Simulation time	497851800 ps
CPU time	0.84 seconds
Started	Feb 07 12:50:38 PM PST 24
Finished	Feb 07 12:50:40 PM PST 24
Peak memory	201196 kb
Host	smart-578cd3a0-3e7f-4768-91c9-16dbc4fa16ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733906404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2733906404
Directory	/workspace/18.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1032188469
Short name	T27
Test name
Test status
Simulation time	3993854915 ps
CPU time	15.18 seconds
Started	Feb 07 12:50:36 PM PST 24
Finished	Feb 07 12:50:52 PM PST 24
Peak memory	201736 kb
Host	smart-7da74275-b902-48b9-ae44-44e5954be222
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032188469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ ctrl_same_csr_outstanding.1032188469
Directory	/workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4234563262
Short name	T57
Test name
Test status
Simulation time	442536925 ps
CPU time	3.19 seconds
Started	Feb 07 12:50:34 PM PST 24
Finished	Feb 07 12:50:38 PM PST 24
Peak memory	217912 kb
Host	smart-f2dd71f5-f9ac-46ba-88bf-95915c448a31
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234563262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4234563262
Directory	/workspace/18.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1370057419
Short name	T875
Test name
Test status
Simulation time	8691830201 ps
CPU time	7.36 seconds
Started	Feb 07 12:50:37 PM PST 24
Finished	Feb 07 12:50:46 PM PST 24
Peak memory	201788 kb
Host	smart-922ab9ec-89fb-4687-9c8f-40553455525e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370057419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i ntg_err.1370057419
Directory	/workspace/18.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2127446583
Short name	T914
Test name
Test status
Simulation time	508455145 ps
CPU time	1.35 seconds
Started	Feb 07 12:50:37 PM PST 24
Finished	Feb 07 12:50:40 PM PST 24
Peak memory	201480 kb
Host	smart-e5e6ed97-af1e-40b4-ac91-18e7a435f999
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127446583 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2127446583
Directory	/workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1246969651
Short name	T358
Test name
Test status
Simulation time	356025789 ps
CPU time	1.55 seconds
Started	Feb 07 12:50:44 PM PST 24
Finished	Feb 07 12:50:46 PM PST 24
Peak memory	201416 kb
Host	smart-f120d2b6-895d-4c86-981e-59795682e35d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246969651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1246969651
Directory	/workspace/19.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4273292626
Short name	T894
Test name
Test status
Simulation time	427610534 ps
CPU time	0.72 seconds
Started	Feb 07 12:50:41 PM PST 24
Finished	Feb 07 12:50:43 PM PST 24
Peak memory	201104 kb
Host	smart-77ac4b9a-d888-4850-b26d-8fbefc5e17b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273292626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.4273292626
Directory	/workspace/19.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1918188771
Short name	T5
Test name
Test status
Simulation time	2922709481 ps
CPU time	2.01 seconds
Started	Feb 07 12:50:33 PM PST 24
Finished	Feb 07 12:50:36 PM PST 24
Peak memory	201540 kb
Host	smart-08738c05-bed9-40be-bb79-17b21c6a838a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918188771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ ctrl_same_csr_outstanding.1918188771
Directory	/workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1888525657
Short name	T60
Test name
Test status
Simulation time	1116540926 ps
CPU time	2.98 seconds
Started	Feb 07 12:50:44 PM PST 24
Finished	Feb 07 12:50:48 PM PST 24
Peak memory	217960 kb
Host	smart-2914fece-76ef-4535-b67a-a18d049c5a20
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888525657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1888525657
Directory	/workspace/19.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3906701898
Short name	T71
Test name
Test status
Simulation time	728996704 ps
CPU time	2.28 seconds
Started	Feb 07 12:50:22 PM PST 24
Finished	Feb 07 12:50:25 PM PST 24
Peak memory	201564 kb
Host	smart-00b94ed5-a64b-4690-85c2-f6edde5a731f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906701898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia sing.3906701898
Directory	/workspace/2.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.563400713
Short name	T379
Test name
Test status
Simulation time	53328909443 ps
CPU time	107.31 seconds
Started	Feb 07 12:50:25 PM PST 24
Finished	Feb 07 12:52:13 PM PST 24
Peak memory	201756 kb
Host	smart-0c7ef5e4-fcb3-4283-8aaa-a69693241629
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563400713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b ash.563400713
Directory	/workspace/2.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2255622369
Short name	T372
Test name
Test status
Simulation time	1096763437 ps
CPU time	2.12 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:19 PM PST 24
Peak memory	201420 kb
Host	smart-0b308fcf-3be5-42b1-96fb-377740ea92d3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255622369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r eset.2255622369
Directory	/workspace/2.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1466433631
Short name	T365
Test name
Test status
Simulation time	371809375 ps
CPU time	1.32 seconds
Started	Feb 07 12:50:14 PM PST 24
Finished	Feb 07 12:50:16 PM PST 24
Peak memory	201480 kb
Host	smart-62cc5a36-e792-493b-9c98-3dadbcf98f72
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466433631 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1466433631
Directory	/workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1798267557
Short name	T373
Test name
Test status
Simulation time	458934295 ps
CPU time	1.45 seconds
Started	Feb 07 12:50:21 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	201312 kb
Host	smart-e5ebfc93-90d8-4ee9-ad91-65410144cb2d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798267557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1798267557
Directory	/workspace/2.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2454241890
Short name	T386
Test name
Test status
Simulation time	492379072 ps
CPU time	0.87 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:17 PM PST 24
Peak memory	201136 kb
Host	smart-d673b4f4-edd9-4e65-b6b2-bd8eb94fbad4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454241890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2454241890
Directory	/workspace/2.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.648001294
Short name	T333
Test name
Test status
Simulation time	4997978337 ps
CPU time	4.21 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:17 PM PST 24
Peak memory	201820 kb
Host	smart-b0929c8a-de3e-4f3e-8113-91ef4ed01f0a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648001294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct rl_same_csr_outstanding.648001294
Directory	/workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3128954817
Short name	T885
Test name
Test status
Simulation time	798752629 ps
CPU time	1.97 seconds
Started	Feb 07 12:50:20 PM PST 24
Finished	Feb 07 12:50:23 PM PST 24
Peak memory	201720 kb
Host	smart-1b3d9e00-62b0-4230-8071-2a380d7ea9b5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128954817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3128954817
Directory	/workspace/2.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.516820515
Short name	T320
Test name
Test status
Simulation time	7816351860 ps
CPU time	21.82 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:36 PM PST 24
Peak memory	201712 kb
Host	smart-97e37d31-fc48-43c5-a36a-5dbc6375b9c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516820515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int g_err.516820515
Directory	/workspace/2.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.73757225
Short name	T867
Test name
Test status
Simulation time	289207265 ps
CPU time	0.95 seconds
Started	Feb 07 12:50:44 PM PST 24
Finished	Feb 07 12:50:46 PM PST 24
Peak memory	201152 kb
Host	smart-f8d987a3-108e-4db0-a28e-276f2a62d5a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73757225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.73757225
Directory	/workspace/20.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.269381079
Short name	T376
Test name
Test status
Simulation time	394712379 ps
CPU time	1.55 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201188 kb
Host	smart-096a8e3f-2e81-4867-8775-ff5e91e16a14
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269381079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.269381079
Directory	/workspace/21.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4100614299
Short name	T907
Test name
Test status
Simulation time	513276617 ps
CPU time	1.95 seconds
Started	Feb 07 12:50:40 PM PST 24
Finished	Feb 07 12:50:44 PM PST 24
Peak memory	201468 kb
Host	smart-a207ff17-eb74-4f8d-a7fa-8318c851ef0e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100614299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4100614299
Directory	/workspace/22.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1921767475
Short name	T354
Test name
Test status
Simulation time	375056299 ps
CPU time	1.58 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201172 kb
Host	smart-fbe97e74-ec86-4122-93b2-59ab2e9cebb8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921767475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1921767475
Directory	/workspace/23.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1958452179
Short name	T346
Test name
Test status
Simulation time	334373479 ps
CPU time	1.43 seconds
Started	Feb 07 12:50:38 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201388 kb
Host	smart-964bdd3c-e82b-46e6-88c3-9b529e03c6d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958452179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1958452179
Directory	/workspace/24.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3211709900
Short name	T332
Test name
Test status
Simulation time	519799238 ps
CPU time	1.85 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201212 kb
Host	smart-b890bb92-6624-4ccb-8d87-9bb203d63255
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211709900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3211709900
Directory	/workspace/25.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1265073878
Short name	T67
Test name
Test status
Simulation time	319384695 ps
CPU time	1.32 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201184 kb
Host	smart-c7a55245-15e3-4aae-9ce1-44a6db4a7bcf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265073878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1265073878
Directory	/workspace/26.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.686462744
Short name	T883
Test name
Test status
Simulation time	482253971 ps
CPU time	1.77 seconds
Started	Feb 07 12:50:43 PM PST 24
Finished	Feb 07 12:50:46 PM PST 24
Peak memory	201204 kb
Host	smart-8d1f7330-447b-49f6-9145-4fe288c0436a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686462744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.686462744
Directory	/workspace/27.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3780178487
Short name	T898
Test name
Test status
Simulation time	399015389 ps
CPU time	0.68 seconds
Started	Feb 07 12:50:35 PM PST 24
Finished	Feb 07 12:50:37 PM PST 24
Peak memory	201188 kb
Host	smart-10b8f047-c7c2-4206-925e-f3e7acd2bb4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780178487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3780178487
Directory	/workspace/28.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.875807166
Short name	T910
Test name
Test status
Simulation time	526644605 ps
CPU time	1.19 seconds
Started	Feb 07 12:50:37 PM PST 24
Finished	Feb 07 12:50:40 PM PST 24
Peak memory	201372 kb
Host	smart-9a894d4c-310a-4a82-960f-390cfaf8aabe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875807166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.875807166
Directory	/workspace/29.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.777542366
Short name	T7
Test name
Test status
Simulation time	1056735773 ps
CPU time	5.42 seconds
Started	Feb 07 12:50:20 PM PST 24
Finished	Feb 07 12:50:27 PM PST 24
Peak memory	201620 kb
Host	smart-2a02b4f3-d9a3-4f0e-accc-dc9e21aca6f6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777542366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias ing.777542366
Directory	/workspace/3.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.463303162
Short name	T871
Test name
Test status
Simulation time	1283695200 ps
CPU time	1.54 seconds
Started	Feb 07 12:50:12 PM PST 24
Finished	Feb 07 12:50:14 PM PST 24
Peak memory	201368 kb
Host	smart-d14ef0a0-e608-427a-b4f3-12e16bfe420b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463303162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re set.463303162
Directory	/workspace/3.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3118705971
Short name	T899
Test name
Test status
Simulation time	572428321 ps
CPU time	2.03 seconds
Started	Feb 07 12:50:18 PM PST 24
Finished	Feb 07 12:50:21 PM PST 24
Peak memory	201472 kb
Host	smart-baa48e85-0242-42fe-8864-8827ea4f5fda
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118705971 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3118705971
Directory	/workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3798075248
Short name	T329
Test name
Test status
Simulation time	445315055 ps
CPU time	1.18 seconds
Started	Feb 07 12:50:18 PM PST 24
Finished	Feb 07 12:50:20 PM PST 24
Peak memory	201080 kb
Host	smart-ee244633-c1cc-4f57-b32d-1228c3d3a5cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798075248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3798075248
Directory	/workspace/3.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3899704535
Short name	T63
Test name
Test status
Simulation time	2061259726 ps
CPU time	5.63 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:22 PM PST 24
Peak memory	201448 kb
Host	smart-58460b0e-eaec-44e8-9636-afd8afe17028
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899704535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c trl_same_csr_outstanding.3899704535
Directory	/workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2876927019
Short name	T76
Test name
Test status
Simulation time	588754943 ps
CPU time	3.32 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:21 PM PST 24
Peak memory	217892 kb
Host	smart-a4480203-bc36-46b1-8e5a-1d1060778a7c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876927019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2876927019
Directory	/workspace/3.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.209335662
Short name	T380
Test name
Test status
Simulation time	8570092700 ps
CPU time	21.4 seconds
Started	Feb 07 12:50:23 PM PST 24
Finished	Feb 07 12:50:46 PM PST 24
Peak memory	201652 kb
Host	smart-9491fe4e-b96e-41de-a37d-1894a37bab3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209335662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int g_err.209335662
Directory	/workspace/3.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.375607204
Short name	T870
Test name
Test status
Simulation time	307255121 ps
CPU time	1.34 seconds
Started	Feb 07 12:50:41 PM PST 24
Finished	Feb 07 12:50:43 PM PST 24
Peak memory	201208 kb
Host	smart-d3ed5422-7030-401e-974f-2f1ddb0240de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375607204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.375607204
Directory	/workspace/30.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1691715616
Short name	T25
Test name
Test status
Simulation time	456159902 ps
CPU time	1.17 seconds
Started	Feb 07 12:50:44 PM PST 24
Finished	Feb 07 12:50:47 PM PST 24
Peak memory	201424 kb
Host	smart-f91612a2-a866-488e-a2a2-b11efeafb5dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691715616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1691715616
Directory	/workspace/31.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2483001192
Short name	T903
Test name
Test status
Simulation time	357726665 ps
CPU time	1.49 seconds
Started	Feb 07 12:50:44 PM PST 24
Finished	Feb 07 12:50:47 PM PST 24
Peak memory	201208 kb
Host	smart-2cdaad29-fcc5-4dab-b945-533dcb9eaba2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483001192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2483001192
Directory	/workspace/32.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2219096018
Short name	T336
Test name
Test status
Simulation time	331775608 ps
CPU time	1.11 seconds
Started	Feb 07 12:50:40 PM PST 24
Finished	Feb 07 12:50:43 PM PST 24
Peak memory	201268 kb
Host	smart-7423ae92-9aab-425d-bc86-9f5f239abf94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219096018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2219096018
Directory	/workspace/33.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1777596658
Short name	T337
Test name
Test status
Simulation time	420831272 ps
CPU time	0.86 seconds
Started	Feb 07 12:50:43 PM PST 24
Finished	Feb 07 12:50:45 PM PST 24
Peak memory	201224 kb
Host	smart-c9976de8-761e-45f1-bbf2-0986131f7726
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777596658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1777596658
Directory	/workspace/34.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1324521272
Short name	T342
Test name
Test status
Simulation time	487433098 ps
CPU time	1.02 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201464 kb
Host	smart-64a604f5-116c-4940-a100-62d30e3f7220
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324521272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1324521272
Directory	/workspace/35.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3071502602
Short name	T347
Test name
Test status
Simulation time	604193019 ps
CPU time	0.71 seconds
Started	Feb 07 12:50:37 PM PST 24
Finished	Feb 07 12:50:39 PM PST 24
Peak memory	201184 kb
Host	smart-42c513ce-71ee-4ebf-ac01-6cab66683617
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071502602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3071502602
Directory	/workspace/36.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4190840973
Short name	T869
Test name
Test status
Simulation time	486495208 ps
CPU time	0.92 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201220 kb
Host	smart-ad8334b0-43d0-4a83-a41b-5fb77ffe31f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190840973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4190840973
Directory	/workspace/37.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3259490427
Short name	T873
Test name
Test status
Simulation time	361507636 ps
CPU time	1.05 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201388 kb
Host	smart-e7c6e351-943f-4abb-bd19-92eee5606aa0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259490427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3259490427
Directory	/workspace/38.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.284550572
Short name	T331
Test name
Test status
Simulation time	485550068 ps
CPU time	1.63 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:42 PM PST 24
Peak memory	201200 kb
Host	smart-67993f4f-b66e-4d9b-a668-a1693da7d8f0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284550572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.284550572
Directory	/workspace/39.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4171475510
Short name	T351
Test name
Test status
Simulation time	777403176 ps
CPU time	2.24 seconds
Started	Feb 07 12:50:16 PM PST 24
Finished	Feb 07 12:50:20 PM PST 24
Peak memory	201580 kb
Host	smart-f853f945-38f5-4667-812b-f918d27b7433
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171475510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia sing.4171475510
Directory	/workspace/4.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2437173101
Short name	T876
Test name
Test status
Simulation time	52087911337 ps
CPU time	131.11 seconds
Started	Feb 07 12:50:23 PM PST 24
Finished	Feb 07 12:52:34 PM PST 24
Peak memory	201748 kb
Host	smart-c977073a-a77d-4572-bda7-075db1c420a1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437173101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_ bash.2437173101
Directory	/workspace/4.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.378162105
Short name	T366
Test name
Test status
Simulation time	1085595791 ps
CPU time	3.13 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:19 PM PST 24
Peak memory	201308 kb
Host	smart-9260bf74-ceb5-4fa5-b188-9003e5f370c4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378162105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re set.378162105
Directory	/workspace/4.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2653476967
Short name	T327
Test name
Test status
Simulation time	552474237 ps
CPU time	2.09 seconds
Started	Feb 07 12:50:26 PM PST 24
Finished	Feb 07 12:50:29 PM PST 24
Peak memory	201480 kb
Host	smart-844e7f4e-a506-466a-b8d9-70827d22ee53
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653476967 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2653476967
Directory	/workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1142078779
Short name	T387
Test name
Test status
Simulation time	331417482 ps
CPU time	0.94 seconds
Started	Feb 07 12:50:22 PM PST 24
Finished	Feb 07 12:50:24 PM PST 24
Peak memory	201412 kb
Host	smart-e9a6e766-702e-42c6-805a-eb6208337c39
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142078779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1142078779
Directory	/workspace/4.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2951916789
Short name	T368
Test name
Test status
Simulation time	500367870 ps
CPU time	0.91 seconds
Started	Feb 07 12:50:17 PM PST 24
Finished	Feb 07 12:50:19 PM PST 24
Peak memory	201176 kb
Host	smart-e5968686-7af5-45e9-bacc-e9f23488676b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951916789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2951916789
Directory	/workspace/4.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2840079490
Short name	T28
Test name
Test status
Simulation time	2272733339 ps
CPU time	3.27 seconds
Started	Feb 07 12:50:13 PM PST 24
Finished	Feb 07 12:50:17 PM PST 24
Peak memory	201552 kb
Host	smart-e35927c2-6368-4bbc-b5ac-244761a03466
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840079490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c trl_same_csr_outstanding.2840079490
Directory	/workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3118517444
Short name	T877
Test name
Test status
Simulation time	587944300 ps
CPU time	2.13 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:18 PM PST 24
Peak memory	201584 kb
Host	smart-f19af5cb-36b6-46f0-ba1b-1fa963f69281
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118517444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3118517444
Directory	/workspace/4.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1152068192
Short name	T897
Test name
Test status
Simulation time	4252540191 ps
CPU time	12.28 seconds
Started	Feb 07 12:50:15 PM PST 24
Finished	Feb 07 12:50:28 PM PST 24
Peak memory	201648 kb
Host	smart-ad5e6e9c-9a09-4f3f-ab1b-5ee8cc07a17a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152068192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in tg_err.1152068192
Directory	/workspace/4.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2758117121
Short name	T323
Test name
Test status
Simulation time	426189084 ps
CPU time	0.69 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201380 kb
Host	smart-601fd7ce-efaf-4426-a28a-c612e24072d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758117121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2758117121
Directory	/workspace/40.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1066837200
Short name	T343
Test name
Test status
Simulation time	347402315 ps
CPU time	1.47 seconds
Started	Feb 07 12:50:40 PM PST 24
Finished	Feb 07 12:50:43 PM PST 24
Peak memory	201228 kb
Host	smart-e927e75d-1629-4b1c-b7c2-e178bf8c219c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066837200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1066837200
Directory	/workspace/41.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2952881056
Short name	T61
Test name
Test status
Simulation time	364184422 ps
CPU time	0.84 seconds
Started	Feb 07 12:50:40 PM PST 24
Finished	Feb 07 12:50:42 PM PST 24
Peak memory	201412 kb
Host	smart-4927cebb-9b7f-4594-9975-671f5b0ec200
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952881056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2952881056
Directory	/workspace/42.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1246090444
Short name	T24
Test name
Test status
Simulation time	538165369 ps
CPU time	0.85 seconds
Started	Feb 07 12:50:41 PM PST 24
Finished	Feb 07 12:50:43 PM PST 24
Peak memory	201184 kb
Host	smart-a96452bd-9d27-4e30-8005-7d3933949467
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246090444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1246090444
Directory	/workspace/43.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1234858318
Short name	T370
Test name
Test status
Simulation time	331045960 ps
CPU time	0.76 seconds
Started	Feb 07 12:50:47 PM PST 24
Finished	Feb 07 12:50:48 PM PST 24
Peak memory	201384 kb
Host	smart-a9cab78b-45bb-47e0-9887-695b25c2022b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234858318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1234858318
Directory	/workspace/44.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.435036837
Short name	T384
Test name
Test status
Simulation time	297581583 ps
CPU time	0.99 seconds
Started	Feb 07 12:50:44 PM PST 24
Finished	Feb 07 12:50:46 PM PST 24
Peak memory	201168 kb
Host	smart-f5c37127-133f-4c6f-9478-e8f3a0ce8cdf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435036837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.435036837
Directory	/workspace/45.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3404365565
Short name	T912
Test name
Test status
Simulation time	459343253 ps
CPU time	0.85 seconds
Started	Feb 07 12:50:42 PM PST 24
Finished	Feb 07 12:50:45 PM PST 24
Peak memory	201336 kb
Host	smart-4bca941e-2bc3-411e-9963-827d8b8b8331
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404365565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3404365565
Directory	/workspace/46.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.444154300
Short name	T356
Test name
Test status
Simulation time	418939452 ps
CPU time	0.73 seconds
Started	Feb 07 12:50:40 PM PST 24
Finished	Feb 07 12:50:43 PM PST 24
Peak memory	201260 kb
Host	smart-15b3a9a1-1ffa-4122-aa6a-e854d9a4a81a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444154300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.444154300
Directory	/workspace/47.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2325003100
Short name	T339
Test name
Test status
Simulation time	398387429 ps
CPU time	1.55 seconds
Started	Feb 07 12:50:48 PM PST 24
Finished	Feb 07 12:50:50 PM PST 24
Peak memory	201116 kb
Host	smart-7708b9ac-37a5-4ba8-8ead-4053113aa8d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325003100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2325003100
Directory	/workspace/48.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2603912914
Short name	T890
Test name
Test status
Simulation time	464081791 ps
CPU time	1.14 seconds
Started	Feb 07 12:50:39 PM PST 24
Finished	Feb 07 12:50:41 PM PST 24
Peak memory	201168 kb
Host	smart-9ce39140-9182-481c-b730-293712073eca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603912914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2603912914
Directory	/workspace/49.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3892113342
Short name	T349
Test name
Test status
Simulation time	525093289 ps
CPU time	1.4 seconds
Started	Feb 07 12:50:30 PM PST 24
Finished	Feb 07 12:50:33 PM PST 24
Peak memory	201480 kb
Host	smart-9ff7b1c5-f6e3-4bda-87f5-b825618bd2dd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892113342 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3892113342
Directory	/workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2964503457
Short name	T68
Test name
Test status
Simulation time	444702557 ps
CPU time	1.51 seconds
Started	Feb 07 12:50:24 PM PST 24
Finished	Feb 07 12:50:26 PM PST 24
Peak memory	201384 kb
Host	smart-91716388-061d-4ae3-8211-6c9afbde8302
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964503457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2964503457
Directory	/workspace/5.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3929799195
Short name	T328
Test name
Test status
Simulation time	417352243 ps
CPU time	1.16 seconds
Started	Feb 07 12:50:23 PM PST 24
Finished	Feb 07 12:50:25 PM PST 24
Peak memory	201176 kb
Host	smart-835430ba-007d-4d67-b0d9-3135520b7fce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929799195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3929799195
Directory	/workspace/5.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3076641213
Short name	T360
Test name
Test status
Simulation time	2978168936 ps
CPU time	4.52 seconds
Started	Feb 07 12:50:31 PM PST 24
Finished	Feb 07 12:50:37 PM PST 24
Peak memory	201536 kb
Host	smart-83136e03-baf3-4252-b2a4-053c02f2f44c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076641213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c trl_same_csr_outstanding.3076641213
Directory	/workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2993782995
Short name	T77
Test name
Test status
Simulation time	608479928 ps
CPU time	1.99 seconds
Started	Feb 07 12:50:27 PM PST 24
Finished	Feb 07 12:50:30 PM PST 24
Peak memory	201756 kb
Host	smart-810780c5-8d53-4cbb-bbe9-fef159ffb481
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993782995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2993782995
Directory	/workspace/5.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3025692040
Short name	T338
Test name
Test status
Simulation time	4265579040 ps
CPU time	12.2 seconds
Started	Feb 07 12:50:31 PM PST 24
Finished	Feb 07 12:50:44 PM PST 24
Peak memory	201772 kb
Host	smart-95eb18c7-4521-41c2-97ca-743fdae9ef52
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025692040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in tg_err.3025692040
Directory	/workspace/5.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1319848402
Short name	T881
Test name
Test status
Simulation time	655163791 ps
CPU time	1.65 seconds
Started	Feb 07 12:50:28 PM PST 24
Finished	Feb 07 12:50:31 PM PST 24
Peak memory	201732 kb
Host	smart-2091b183-0b91-44dc-97e3-5636b4e5fb7e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319848402 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1319848402
Directory	/workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3510188066
Short name	T334
Test name
Test status
Simulation time	694618495 ps
CPU time	0.95 seconds
Started	Feb 07 12:50:23 PM PST 24
Finished	Feb 07 12:50:25 PM PST 24
Peak memory	201364 kb
Host	smart-e7de188a-cd0e-455f-b16c-7144031a0dd5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510188066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3510188066
Directory	/workspace/6.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4098342452
Short name	T362
Test name
Test status
Simulation time	525046101 ps
CPU time	1.83 seconds
Started	Feb 07 12:50:28 PM PST 24
Finished	Feb 07 12:50:31 PM PST 24
Peak memory	201184 kb
Host	smart-c3c26d50-7520-400b-8880-fd0fcc63b28c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098342452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4098342452
Directory	/workspace/6.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2922205465
Short name	T911
Test name
Test status
Simulation time	2463074872 ps
CPU time	9.69 seconds
Started	Feb 07 12:50:25 PM PST 24
Finished	Feb 07 12:50:35 PM PST 24
Peak memory	201500 kb
Host	smart-c0b3b6a1-4c2b-41b2-b41c-4463bf51863e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922205465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c trl_same_csr_outstanding.2922205465
Directory	/workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2061974043
Short name	T344
Test name
Test status
Simulation time	720482183 ps
CPU time	2.65 seconds
Started	Feb 07 12:50:23 PM PST 24
Finished	Feb 07 12:50:27 PM PST 24
Peak memory	201584 kb
Host	smart-4e15aa83-3551-45cc-b29d-d838190e2e03
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061974043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2061974043
Directory	/workspace/6.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2321010555
Short name	T900
Test name
Test status
Simulation time	4375675237 ps
CPU time	6 seconds
Started	Feb 07 12:50:30 PM PST 24
Finished	Feb 07 12:50:37 PM PST 24
Peak memory	201664 kb
Host	smart-a5fb81d4-4a43-4903-bcab-def2e17cd7fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321010555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in tg_err.2321010555
Directory	/workspace/6.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2119871453
Short name	T325
Test name
Test status
Simulation time	489182317 ps
CPU time	0.97 seconds
Started	Feb 07 12:50:25 PM PST 24
Finished	Feb 07 12:50:27 PM PST 24
Peak memory	201396 kb
Host	smart-6064eba2-1c35-44e6-9af6-6558832491a6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119871453 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2119871453
Directory	/workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3499026173
Short name	T26
Test name
Test status
Simulation time	335526643 ps
CPU time	1.14 seconds
Started	Feb 07 12:50:27 PM PST 24
Finished	Feb 07 12:50:29 PM PST 24
Peak memory	201364 kb
Host	smart-cb0d16ca-8aff-4ab5-9b20-f34ee5d7f7bf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499026173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3499026173
Directory	/workspace/7.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2525185200
Short name	T363
Test name
Test status
Simulation time	461174612 ps
CPU time	0.88 seconds
Started	Feb 07 12:50:31 PM PST 24
Finished	Feb 07 12:50:33 PM PST 24
Peak memory	201368 kb
Host	smart-3cb52116-d679-414e-9969-f61c5b022356
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525185200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2525185200
Directory	/workspace/7.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.536633379
Short name	T341
Test name
Test status
Simulation time	4735752376 ps
CPU time	6.58 seconds
Started	Feb 07 12:50:26 PM PST 24
Finished	Feb 07 12:50:34 PM PST 24
Peak memory	201776 kb
Host	smart-b5174a20-4bec-4b13-9b16-bd6a3429ef52
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536633379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct rl_same_csr_outstanding.536633379
Directory	/workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.901399389
Short name	T59
Test name
Test status
Simulation time	508430303 ps
CPU time	2.8 seconds
Started	Feb 07 12:50:28 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	217488 kb
Host	smart-dc3b0d6e-931d-4aca-87e2-68c111c49751
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901399389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.901399389
Directory	/workspace/7.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.189017595
Short name	T8
Test name
Test status
Simulation time	4643354878 ps
CPU time	4.3 seconds
Started	Feb 07 12:50:34 PM PST 24
Finished	Feb 07 12:50:39 PM PST 24
Peak memory	201776 kb
Host	smart-f30c76a5-7106-48e0-af97-57a6cf1227c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189017595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int g_err.189017595
Directory	/workspace/7.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.508730828
Short name	T161
Test name
Test status
Simulation time	504700941 ps
CPU time	1.39 seconds
Started	Feb 07 12:50:26 PM PST 24
Finished	Feb 07 12:50:29 PM PST 24
Peak memory	201528 kb
Host	smart-b3eb33a9-094f-420c-92b6-f7247c37edac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508730828 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.508730828
Directory	/workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3847325510
Short name	T64
Test name
Test status
Simulation time	486076416 ps
CPU time	1.59 seconds
Started	Feb 07 12:50:26 PM PST 24
Finished	Feb 07 12:50:28 PM PST 24
Peak memory	201376 kb
Host	smart-61eb20e4-97e3-4983-ac40-d37359d67b56
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847325510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3847325510
Directory	/workspace/8.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2811006040
Short name	T378
Test name
Test status
Simulation time	461604207 ps
CPU time	1.37 seconds
Started	Feb 07 12:50:30 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	201144 kb
Host	smart-ea37ddc6-3598-456b-8810-d0232cb6f249
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811006040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2811006040
Directory	/workspace/8.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1336677345
Short name	T355
Test name
Test status
Simulation time	2308866474 ps
CPU time	6.19 seconds
Started	Feb 07 12:50:25 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	201456 kb
Host	smart-ad1c2942-951e-47bf-8d08-ce23cad85fa8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336677345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c trl_same_csr_outstanding.1336677345
Directory	/workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3190280962
Short name	T23
Test name
Test status
Simulation time	749425216 ps
CPU time	2.19 seconds
Started	Feb 07 12:50:24 PM PST 24
Finished	Feb 07 12:50:27 PM PST 24
Peak memory	201652 kb
Host	smart-3a38a402-ba12-461b-9fb3-06e9860361f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190280962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3190280962
Directory	/workspace/8.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1677202608
Short name	T359
Test name
Test status
Simulation time	8523210480 ps
CPU time	7.15 seconds
Started	Feb 07 12:50:27 PM PST 24
Finished	Feb 07 12:50:35 PM PST 24
Peak memory	201720 kb
Host	smart-2df19ad6-f09b-47f8-913b-e0b9b33bbc88
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677202608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in tg_err.1677202608
Directory	/workspace/8.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4236339449
Short name	T382
Test name
Test status
Simulation time	420146259 ps
CPU time	1.34 seconds
Started	Feb 07 12:50:33 PM PST 24
Finished	Feb 07 12:50:36 PM PST 24
Peak memory	201416 kb
Host	smart-a34efcab-7f96-4b38-bf8b-886dee3e1104
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236339449 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4236339449
Directory	/workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1823758316
Short name	T371
Test name
Test status
Simulation time	647345950 ps
CPU time	0.99 seconds
Started	Feb 07 12:50:26 PM PST 24
Finished	Feb 07 12:50:29 PM PST 24
Peak memory	201408 kb
Host	smart-4a268561-5665-43c9-a2b0-a4a7d81e1530
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823758316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1823758316
Directory	/workspace/9.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3042780888
Short name	T887
Test name
Test status
Simulation time	539428267 ps
CPU time	1.23 seconds
Started	Feb 07 12:50:34 PM PST 24
Finished	Feb 07 12:50:36 PM PST 24
Peak memory	201124 kb
Host	smart-93f0fd20-6036-415d-b137-7fb79708362b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042780888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3042780888
Directory	/workspace/9.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3523965774
Short name	T348
Test name
Test status
Simulation time	5084667717 ps
CPU time	4.84 seconds
Started	Feb 07 12:50:33 PM PST 24
Finished	Feb 07 12:50:39 PM PST 24
Peak memory	201592 kb
Host	smart-c3cdd163-5518-4edb-b2bf-6c8af2985c83
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523965774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c trl_same_csr_outstanding.3523965774
Directory	/workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1390280753
Short name	T364
Test name
Test status
Simulation time	596049214 ps
CPU time	1.62 seconds
Started	Feb 07 12:50:30 PM PST 24
Finished	Feb 07 12:50:32 PM PST 24
Peak memory	201720 kb
Host	smart-c68916ee-9cfd-45bf-b90a-cce3c1abbf03
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390280753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1390280753
Directory	/workspace/9.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1901926944
Short name	T319
Test name
Test status
Simulation time	8409908129 ps
CPU time	3.96 seconds
Started	Feb 07 12:50:23 PM PST 24
Finished	Feb 07 12:50:27 PM PST 24
Peak memory	201704 kb
Host	smart-44115594-7859-4803-9e79-50f5fecfe354
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901926944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in tg_err.1901926944
Directory	/workspace/9.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.adc_ctrl_alert_test.1031965467
Short name	T797
Test name
Test status
Simulation time	323594905 ps
CPU time	0.99 seconds
Started	Feb 07 01:19:12 PM PST 24
Finished	Feb 07 01:19:13 PM PST 24
Peak memory	201120 kb
Host	smart-358ab42a-6e81-442a-ab8b-cfc49ff20040
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031965467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1031965467
Directory	/workspace/0.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.adc_ctrl_clock_gating.2202540331
Short name	T244
Test name
Test status
Simulation time	168209887325 ps
CPU time	350.67 seconds
Started	Feb 07 01:19:03 PM PST 24
Finished	Feb 07 01:24:55 PM PST 24
Peak memory	201612 kb
Host	smart-5782f3a8-18bf-401f-882a-70b6b733962f
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202540331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati ng.2202540331
Directory	/workspace/0.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_both.3615485149
Short name	T794
Test name
Test status
Simulation time	491545658290 ps
CPU time	336.75 seconds
Started	Feb 07 01:19:05 PM PST 24
Finished	Feb 07 01:24:42 PM PST 24
Peak memory	201620 kb
Host	smart-71b5222c-6cd3-4e41-b41f-72d611a72af1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615485149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3615485149
Directory	/workspace/0.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3854060602
Short name	T531
Test name
Test status
Simulation time	491462065003 ps
CPU time	142.47 seconds
Started	Feb 07 01:19:10 PM PST 24
Finished	Feb 07 01:21:33 PM PST 24
Peak memory	201536 kb
Host	smart-58a08eff-4fd0-43c3-9dff-6f70ffa909e3
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854060602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup t_fixed.3854060602
Directory	/workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_polled.1704292390
Short name	T692
Test name
Test status
Simulation time	328969924433 ps
CPU time	811.2 seconds
Started	Feb 07 01:19:05 PM PST 24
Finished	Feb 07 01:32:37 PM PST 24
Peak memory	201712 kb
Host	smart-9dd5efbb-77af-4f4b-b094-a3cd155c001a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704292390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1704292390
Directory	/workspace/0.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1435638781
Short name	T705
Test name
Test status
Simulation time	168366900549 ps
CPU time	100.66 seconds
Started	Feb 07 01:19:09 PM PST 24
Finished	Feb 07 01:20:51 PM PST 24
Peak memory	201600 kb
Host	smart-626ed8de-8614-4a33-acfa-77c966c7f895
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435638781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe d.1435638781
Directory	/workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_wakeup.3542235878
Short name	T676
Test name
Test status
Simulation time	512617437096 ps
CPU time	198.62 seconds
Started	Feb 07 01:19:08 PM PST 24
Finished	Feb 07 01:22:27 PM PST 24
Peak memory	201648 kb
Host	smart-4bebe793-9537-44bd-955a-02d3209b9155
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542235878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_ wakeup.3542235878
Directory	/workspace/0.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1955667763
Short name	T559
Test name
Test status
Simulation time	162520347138 ps
CPU time	183.75 seconds
Started	Feb 07 01:19:09 PM PST 24
Finished	Feb 07 01:22:14 PM PST 24
Peak memory	201608 kb
Host	smart-bb59bbc7-4888-43f4-ad55-ff2671ee9206
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955667763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. adc_ctrl_filters_wakeup_fixed.1955667763
Directory	/workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/0.adc_ctrl_fsm_reset.3227619487
Short name	T173
Test name
Test status
Simulation time	61628489130 ps
CPU time	233.48 seconds
Started	Feb 07 01:19:08 PM PST 24
Finished	Feb 07 01:23:03 PM PST 24
Peak memory	201852 kb
Host	smart-8a897b27-5473-43fe-8a00-c42200f37ef3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227619487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3227619487
Directory	/workspace/0.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/0.adc_ctrl_lowpower_counter.1831346959
Short name	T393
Test name
Test status
Simulation time	31927958750 ps
CPU time	20.91 seconds
Started	Feb 07 01:19:10 PM PST 24
Finished	Feb 07 01:19:32 PM PST 24
Peak memory	201380 kb
Host	smart-f0c60176-0485-486d-a63c-4b8ec046f0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831346959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1831346959
Directory	/workspace/0.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/0.adc_ctrl_poweron_counter.2196431358
Short name	T457
Test name
Test status
Simulation time	4350671049 ps
CPU time	11.26 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:19:27 PM PST 24
Peak memory	201408 kb
Host	smart-355d3702-bf89-4cdf-a81c-ad503ff07cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196431358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2196431358
Directory	/workspace/0.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/0.adc_ctrl_sec_cm.858803430
Short name	T41
Test name
Test status
Simulation time	8685074878 ps
CPU time	2.29 seconds
Started	Feb 07 01:19:12 PM PST 24
Finished	Feb 07 01:19:15 PM PST 24
Peak memory	217572 kb
Host	smart-8b18103a-40a9-4cfb-8a9a-c2a5d19c8463
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858803430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.858803430
Directory	/workspace/0.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.adc_ctrl_smoke.1759612714
Short name	T453
Test name
Test status
Simulation time	5994942326 ps
CPU time	4.29 seconds
Started	Feb 07 01:19:04 PM PST 24
Finished	Feb 07 01:19:09 PM PST 24
Peak memory	201400 kb
Host	smart-2c1b7666-9d86-4505-8860-a0ca7b795f13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759612714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1759612714
Directory	/workspace/0.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.adc_ctrl_stress_all.3296710043
Short name	T415
Test name
Test status
Simulation time	86978692950 ps
CPU time	47.78 seconds
Started	Feb 07 01:19:16 PM PST 24
Finished	Feb 07 01:20:04 PM PST 24
Peak memory	201696 kb
Host	smart-91178ba9-70ef-4a9c-ba82-ef48dfaa84c3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296710043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all. 3296710043
Directory	/workspace/0.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1254255913
Short name	T94
Test name
Test status
Simulation time	89112738580 ps
CPU time	105.46 seconds
Started	Feb 07 01:19:09 PM PST 24
Finished	Feb 07 01:20:55 PM PST 24
Peak memory	202116 kb
Host	smart-c30118be-382b-4d0e-ba28-77c2c193cd27
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254255913 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1254255913
Directory	/workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.adc_ctrl_alert_test.3812768072
Short name	T506
Test name
Test status
Simulation time	497606699 ps
CPU time	1.23 seconds
Started	Feb 07 01:19:16 PM PST 24
Finished	Feb 07 01:19:18 PM PST 24
Peak memory	201220 kb
Host	smart-34b1528d-3223-44b8-b6f7-7f9103c937c1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812768072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3812768072
Directory	/workspace/1.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2519545358
Short name	T608
Test name
Test status
Simulation time	164624688902 ps
CPU time	379.96 seconds
Started	Feb 07 01:19:11 PM PST 24
Finished	Feb 07 01:25:31 PM PST 24
Peak memory	201552 kb
Host	smart-768f290d-34e7-47a9-b872-148f21ea5349
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519545358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup t_fixed.2519545358
Directory	/workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_polled.1598553708
Short name	T713
Test name
Test status
Simulation time	494201501593 ps
CPU time	261.24 seconds
Started	Feb 07 01:19:13 PM PST 24
Finished	Feb 07 01:23:34 PM PST 24
Peak memory	201548 kb
Host	smart-4d668d7a-540c-40b6-8846-0ab0d78b5bce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598553708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1598553708
Directory	/workspace/1.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2178842813
Short name	T446
Test name
Test status
Simulation time	330030495644 ps
CPU time	737.3 seconds
Started	Feb 07 01:19:11 PM PST 24
Finished	Feb 07 01:31:29 PM PST 24
Peak memory	201612 kb
Host	smart-50c096e9-0d04-4975-a0e9-b14bcfd4d1eb
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178842813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe d.2178842813
Directory	/workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.678865136
Short name	T651
Test name
Test status
Simulation time	334001490504 ps
CPU time	389.77 seconds
Started	Feb 07 01:19:11 PM PST 24
Finished	Feb 07 01:25:42 PM PST 24
Peak memory	201632 kb
Host	smart-6b5dc2b3-8e84-4f28-80b2-b3ed3066a182
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678865136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a dc_ctrl_filters_wakeup_fixed.678865136
Directory	/workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_fsm_reset.2338204373
Short name	T432
Test name
Test status
Simulation time	74037292184 ps
CPU time	328.01 seconds
Started	Feb 07 01:19:12 PM PST 24
Finished	Feb 07 01:24:41 PM PST 24
Peak memory	201904 kb
Host	smart-d78ea4c5-e118-4483-83cc-44f5d5ca1ea9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338204373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2338204373
Directory	/workspace/1.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/1.adc_ctrl_lowpower_counter.4044566793
Short name	T557
Test name
Test status
Simulation time	46522597282 ps
CPU time	53.94 seconds
Started	Feb 07 01:19:10 PM PST 24
Finished	Feb 07 01:20:05 PM PST 24
Peak memory	201428 kb
Host	smart-6a99c66e-de6f-44cb-9b29-9f31276a0c4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044566793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4044566793
Directory	/workspace/1.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/1.adc_ctrl_poweron_counter.1373063773
Short name	T702
Test name
Test status
Simulation time	2676715390 ps
CPU time	2.19 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:19:17 PM PST 24
Peak memory	201376 kb
Host	smart-9c900cc4-05af-4737-82f6-9859efe68688
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373063773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1373063773
Directory	/workspace/1.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/1.adc_ctrl_smoke.1998150160
Short name	T595
Test name
Test status
Simulation time	5966682078 ps
CPU time	14.13 seconds
Started	Feb 07 01:19:11 PM PST 24
Finished	Feb 07 01:19:26 PM PST 24
Peak memory	201336 kb
Host	smart-827a6c5f-796b-45ef-a21f-d3941f40cf2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998150160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1998150160
Directory	/workspace/1.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.adc_ctrl_stress_all.3092590928
Short name	T756
Test name
Test status
Simulation time	40271974610 ps
CPU time	100.28 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:20:55 PM PST 24
Peak memory	201388 kb
Host	smart-c775acbc-6e3d-443f-bf66-ed04bc7c65d1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092590928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all. 3092590928
Directory	/workspace/1.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3292780014
Short name	T785
Test name
Test status
Simulation time	115589074997 ps
CPU time	200.95 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:22:35 PM PST 24
Peak memory	210220 kb
Host	smart-c420f87c-27b4-47e6-bf52-795af8404f94
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292780014 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3292780014
Directory	/workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.adc_ctrl_alert_test.2871104721
Short name	T419
Test name
Test status
Simulation time	335946493 ps
CPU time	1.01 seconds
Started	Feb 07 01:20:44 PM PST 24
Finished	Feb 07 01:20:46 PM PST 24
Peak memory	201264 kb
Host	smart-c9e65f1d-8e42-42bb-8487-a293349bb1c8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871104721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2871104721
Directory	/workspace/10.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_both.1697931873
Short name	T147
Test name
Test status
Simulation time	330434025425 ps
CPU time	189.2 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:23:26 PM PST 24
Peak memory	201544 kb
Host	smart-448a6ebd-6a38-4c44-b44f-907af6cec1af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697931873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1697931873
Directory	/workspace/10.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_interrupt.1877365053
Short name	T248
Test name
Test status
Simulation time	333879597236 ps
CPU time	754.31 seconds
Started	Feb 07 01:20:20 PM PST 24
Finished	Feb 07 01:32:55 PM PST 24
Peak memory	201628 kb
Host	smart-996b8485-d495-4300-ae09-f540e0bd69ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877365053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1877365053
Directory	/workspace/10.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3032793582
Short name	T101
Test name
Test status
Simulation time	161187611372 ps
CPU time	176.15 seconds
Started	Feb 07 01:20:21 PM PST 24
Finished	Feb 07 01:23:18 PM PST 24
Peak memory	201544 kb
Host	smart-70bc7498-e293-40b8-950a-8b670dcecb12
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032793582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru pt_fixed.3032793582
Directory	/workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_polled.2479474992
Short name	T624
Test name
Test status
Simulation time	330810259565 ps
CPU time	762.62 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:32:59 PM PST 24
Peak memory	201720 kb
Host	smart-3036ec53-15d7-46d9-9e18-c12d301cec7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479474992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2479474992
Directory	/workspace/10.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3638764426
Short name	T397
Test name
Test status
Simulation time	161701791523 ps
CPU time	354.68 seconds
Started	Feb 07 01:20:19 PM PST 24
Finished	Feb 07 01:26:15 PM PST 24
Peak memory	201652 kb
Host	smart-351000a4-a7dd-49cd-aed9-affe5f210867
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638764426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix ed.3638764426
Directory	/workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_wakeup.718786088
Short name	T309
Test name
Test status
Simulation time	161601727337 ps
CPU time	197.06 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:23:35 PM PST 24
Peak memory	201524 kb
Host	smart-370b6e96-f330-475a-b981-0d4e620e9a11
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718786088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_ wakeup.718786088
Directory	/workspace/10.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3384853954
Short name	T627
Test name
Test status
Simulation time	169075061808 ps
CPU time	88.16 seconds
Started	Feb 07 01:20:15 PM PST 24
Finished	Feb 07 01:21:44 PM PST 24
Peak memory	201520 kb
Host	smart-9900e603-4792-459f-8e5e-ae1d92329a8b
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384853954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .adc_ctrl_filters_wakeup_fixed.3384853954
Directory	/workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_fsm_reset.2737028836
Short name	T321
Test name
Test status
Simulation time	135625994266 ps
CPU time	535.35 seconds
Started	Feb 07 01:20:39 PM PST 24
Finished	Feb 07 01:29:35 PM PST 24
Peak memory	201940 kb
Host	smart-55cba2d6-32f8-402f-9552-b1bbc5711b07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737028836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2737028836
Directory	/workspace/10.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/10.adc_ctrl_lowpower_counter.112445505
Short name	T865
Test name
Test status
Simulation time	45067094050 ps
CPU time	108.17 seconds
Started	Feb 07 01:20:47 PM PST 24
Finished	Feb 07 01:22:36 PM PST 24
Peak memory	201384 kb
Host	smart-2b4c3536-b0c7-400a-9ef5-882128f7c192
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112445505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.112445505
Directory	/workspace/10.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/10.adc_ctrl_poweron_counter.419809936
Short name	T466
Test name
Test status
Simulation time	3368739106 ps
CPU time	2.56 seconds
Started	Feb 07 01:20:22 PM PST 24
Finished	Feb 07 01:20:25 PM PST 24
Peak memory	201376 kb
Host	smart-482a5662-5532-4cff-bda1-08873a4183bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419809936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.419809936
Directory	/workspace/10.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/10.adc_ctrl_smoke.2714792328
Short name	T492
Test name
Test status
Simulation time	6175758136 ps
CPU time	4.26 seconds
Started	Feb 07 01:20:18 PM PST 24
Finished	Feb 07 01:20:23 PM PST 24
Peak memory	201420 kb
Host	smart-ca228b37-2429-449c-be6c-93996788a3a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714792328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2714792328
Directory	/workspace/10.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.adc_ctrl_stress_all.3705021163
Short name	T269
Test name
Test status
Simulation time	376752319154 ps
CPU time	898.32 seconds
Started	Feb 07 01:20:40 PM PST 24
Finished	Feb 07 01:35:39 PM PST 24
Peak memory	201596 kb
Host	smart-7b8c65ed-148b-4472-8b52-09de38827622
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705021163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all .3705021163
Directory	/workspace/10.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3962685049
Short name	T198
Test name
Test status
Simulation time	185242155340 ps
CPU time	51.92 seconds
Started	Feb 07 01:20:36 PM PST 24
Finished	Feb 07 01:21:28 PM PST 24
Peak memory	201784 kb
Host	smart-6a7cbc00-f46f-46d7-90a6-423689f0c59e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962685049 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3962685049
Directory	/workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.adc_ctrl_alert_test.1096931968
Short name	T691
Test name
Test status
Simulation time	289793137 ps
CPU time	0.99 seconds
Started	Feb 07 01:20:43 PM PST 24
Finished	Feb 07 01:20:45 PM PST 24
Peak memory	201236 kb
Host	smart-7a76de2c-9b72-41ff-804d-2ba178f106d7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096931968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1096931968
Directory	/workspace/11.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4235924127
Short name	T635
Test name
Test status
Simulation time	334011854528 ps
CPU time	739.19 seconds
Started	Feb 07 01:20:40 PM PST 24
Finished	Feb 07 01:33:00 PM PST 24
Peak memory	201544 kb
Host	smart-5c7ab6e1-97ae-424a-b227-ef08d920de66
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235924127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru pt_fixed.4235924127
Directory	/workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_polled.1198747623
Short name	T570
Test name
Test status
Simulation time	325677880021 ps
CPU time	758.07 seconds
Started	Feb 07 01:20:44 PM PST 24
Finished	Feb 07 01:33:22 PM PST 24
Peak memory	201616 kb
Host	smart-426b320d-db42-4f29-ace7-5451a2fb4d94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1198747623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1198747623
Directory	/workspace/11.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1351357916
Short name	T571
Test name
Test status
Simulation time	326221875063 ps
CPU time	58.56 seconds
Started	Feb 07 01:20:35 PM PST 24
Finished	Feb 07 01:21:34 PM PST 24
Peak memory	201520 kb
Host	smart-d8dcc790-5194-4186-ab9e-f93e6d56545c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351357916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix ed.1351357916
Directory	/workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_wakeup.627168250
Short name	T285
Test name
Test status
Simulation time	169736986496 ps
CPU time	401.07 seconds
Started	Feb 07 01:20:42 PM PST 24
Finished	Feb 07 01:27:23 PM PST 24
Peak memory	201616 kb
Host	smart-f71fad46-2cd2-47cb-a84c-bb5f1fc5584e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627168250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_ wakeup.627168250
Directory	/workspace/11.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3760400058
Short name	T45
Test name
Test status
Simulation time	492051476800 ps
CPU time	542.39 seconds
Started	Feb 07 01:20:46 PM PST 24
Finished	Feb 07 01:29:49 PM PST 24
Peak memory	201668 kb
Host	smart-a2457dbc-a5c5-4b58-8be1-cafb96bc42da
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760400058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .adc_ctrl_filters_wakeup_fixed.3760400058
Directory	/workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_fsm_reset.2253641807
Short name	T856
Test name
Test status
Simulation time	99257491601 ps
CPU time	472.29 seconds
Started	Feb 07 01:20:38 PM PST 24
Finished	Feb 07 01:28:31 PM PST 24
Peak memory	201864 kb
Host	smart-04ad277d-2298-41a2-ad19-b3be3cdea201
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253641807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2253641807
Directory	/workspace/11.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/11.adc_ctrl_lowpower_counter.1163474376
Short name	T411
Test name
Test status
Simulation time	43223317445 ps
CPU time	27.42 seconds
Started	Feb 07 01:20:35 PM PST 24
Finished	Feb 07 01:21:03 PM PST 24
Peak memory	201460 kb
Host	smart-60d49244-2c97-44e7-b153-0b3dc6d40108
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163474376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1163474376
Directory	/workspace/11.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/11.adc_ctrl_poweron_counter.353200393
Short name	T629
Test name
Test status
Simulation time	4350893593 ps
CPU time	11.67 seconds
Started	Feb 07 01:20:42 PM PST 24
Finished	Feb 07 01:20:55 PM PST 24
Peak memory	201352 kb
Host	smart-e48d9500-807c-4bed-b28d-473b26545518
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353200393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.353200393
Directory	/workspace/11.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/11.adc_ctrl_smoke.228778604
Short name	T48
Test name
Test status
Simulation time	6194118895 ps
CPU time	14.84 seconds
Started	Feb 07 01:20:43 PM PST 24
Finished	Feb 07 01:20:59 PM PST 24
Peak memory	201340 kb
Host	smart-9dea3ab8-15a1-4c57-975a-afc593dd9852
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228778604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.228778604
Directory	/workspace/11.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.adc_ctrl_stress_all.3101981087
Short name	T124
Test name
Test status
Simulation time	167473084564 ps
CPU time	95.57 seconds
Started	Feb 07 01:20:40 PM PST 24
Finished	Feb 07 01:22:16 PM PST 24
Peak memory	201496 kb
Host	smart-1d7fa0a6-7460-4680-b1a6-34117c850bbb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101981087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all .3101981087
Directory	/workspace/11.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1284499918
Short name	T607
Test name
Test status
Simulation time	94444831883 ps
CPU time	103.13 seconds
Started	Feb 07 01:20:36 PM PST 24
Finished	Feb 07 01:22:19 PM PST 24
Peak memory	209968 kb
Host	smart-f86e6e47-c251-4507-ba11-e516b6b09fa2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284499918 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1284499918
Directory	/workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.adc_ctrl_clock_gating.1046586996
Short name	T268
Test name
Test status
Simulation time	329573576660 ps
CPU time	425.04 seconds
Started	Feb 07 01:20:43 PM PST 24
Finished	Feb 07 01:27:49 PM PST 24
Peak memory	201608 kb
Host	smart-4f572092-09af-4941-9d94-ec826f74accb
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046586996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat ing.1046586996
Directory	/workspace/12.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_both.1694730125
Short name	T193
Test name
Test status
Simulation time	162512193917 ps
CPU time	92.14 seconds
Started	Feb 07 01:20:45 PM PST 24
Finished	Feb 07 01:22:17 PM PST 24
Peak memory	201572 kb
Host	smart-26d0a4c0-7244-4f5d-a789-10e26a85a8aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694730125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1694730125
Directory	/workspace/12.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_interrupt.4290076649
Short name	T782
Test name
Test status
Simulation time	331677473704 ps
CPU time	773.44 seconds
Started	Feb 07 01:20:48 PM PST 24
Finished	Feb 07 01:33:42 PM PST 24
Peak memory	201580 kb
Host	smart-a1cb3d20-7f91-4ad0-a8b1-12674d1193ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290076649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.4290076649
Directory	/workspace/12.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2895005435
Short name	T464
Test name
Test status
Simulation time	492901050303 ps
CPU time	305.95 seconds
Started	Feb 07 01:20:47 PM PST 24
Finished	Feb 07 01:25:54 PM PST 24
Peak memory	201560 kb
Host	smart-1086b438-35e4-4c19-9a6e-3d496ebe9370
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895005435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru pt_fixed.2895005435
Directory	/workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1857136926
Short name	T672
Test name
Test status
Simulation time	163359897216 ps
CPU time	100.66 seconds
Started	Feb 07 01:20:44 PM PST 24
Finished	Feb 07 01:22:25 PM PST 24
Peak memory	201612 kb
Host	smart-93481192-ec29-44ea-8a26-f5018e833677
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857136926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix ed.1857136926
Directory	/workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_wakeup.2527351094
Short name	T130
Test name
Test status
Simulation time	513826548308 ps
CPU time	92.65 seconds
Started	Feb 07 01:20:50 PM PST 24
Finished	Feb 07 01:22:23 PM PST 24
Peak memory	201668 kb
Host	smart-a2da5af2-b1ed-40c9-b8d9-4532011edda7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527351094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters _wakeup.2527351094
Directory	/workspace/12.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2853473793
Short name	T502
Test name
Test status
Simulation time	489636427179 ps
CPU time	1103.18 seconds
Started	Feb 07 01:20:47 PM PST 24
Finished	Feb 07 01:39:11 PM PST 24
Peak memory	201536 kb
Host	smart-4c0268be-4723-4ff1-a180-b79cb078e937
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853473793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .adc_ctrl_filters_wakeup_fixed.2853473793
Directory	/workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_fsm_reset.183327205
Short name	T643
Test name
Test status
Simulation time	78846354292 ps
CPU time	290.18 seconds
Started	Feb 07 01:20:48 PM PST 24
Finished	Feb 07 01:25:39 PM PST 24
Peak memory	201932 kb
Host	smart-59074a19-7e32-4c23-bdaf-2a0885d90a7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183327205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.183327205
Directory	/workspace/12.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/12.adc_ctrl_lowpower_counter.979671017
Short name	T485
Test name
Test status
Simulation time	24144151029 ps
CPU time	29.55 seconds
Started	Feb 07 01:20:46 PM PST 24
Finished	Feb 07 01:21:16 PM PST 24
Peak memory	201400 kb
Host	smart-e307df7c-62d6-42e2-aa9f-c4d6fe324234
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979671017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.979671017
Directory	/workspace/12.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/12.adc_ctrl_poweron_counter.41442087
Short name	T805
Test name
Test status
Simulation time	4924856681 ps
CPU time	12.88 seconds
Started	Feb 07 01:20:43 PM PST 24
Finished	Feb 07 01:20:56 PM PST 24
Peak memory	201392 kb
Host	smart-f7bcacbc-55bb-484e-b7b4-109ffce78fb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41442087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.41442087
Directory	/workspace/12.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/12.adc_ctrl_smoke.1646738602
Short name	T510
Test name
Test status
Simulation time	5838058066 ps
CPU time	2.56 seconds
Started	Feb 07 01:20:46 PM PST 24
Finished	Feb 07 01:20:49 PM PST 24
Peak memory	201340 kb
Host	smart-9eae6a3e-4d3f-4374-b17a-2bdd4f5c94a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646738602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1646738602
Directory	/workspace/12.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.adc_ctrl_stress_all.831870036
Short name	T176
Test name
Test status
Simulation time	498904085714 ps
CPU time	484.94 seconds
Started	Feb 07 01:20:47 PM PST 24
Finished	Feb 07 01:28:52 PM PST 24
Peak memory	201928 kb
Host	smart-2c65f626-b4d4-4563-871d-fd102a8d2501
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831870036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all. 831870036
Directory	/workspace/12.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.188342576
Short name	T154
Test name
Test status
Simulation time	100694115659 ps
CPU time	57.08 seconds
Started	Feb 07 01:20:44 PM PST 24
Finished	Feb 07 01:21:42 PM PST 24
Peak memory	210056 kb
Host	smart-7215b332-a847-4978-b0a9-9953316e1822
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188342576 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.188342576
Directory	/workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.adc_ctrl_alert_test.3050751569
Short name	T480
Test name
Test status
Simulation time	303333073 ps
CPU time	1.35 seconds
Started	Feb 07 01:21:03 PM PST 24
Finished	Feb 07 01:21:05 PM PST 24
Peak memory	201132 kb
Host	smart-651a55fb-35a7-4814-9110-1830956d6564
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050751569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3050751569
Directory	/workspace/13.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.adc_ctrl_clock_gating.2596889483
Short name	T683
Test name
Test status
Simulation time	333542757713 ps
CPU time	621.3 seconds
Started	Feb 07 01:20:57 PM PST 24
Finished	Feb 07 01:31:19 PM PST 24
Peak memory	201588 kb
Host	smart-2b93bdef-8bc6-4854-b192-aa69ff7a8c2e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596889483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat ing.2596889483
Directory	/workspace/13.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_interrupt.4004504249
Short name	T93
Test name
Test status
Simulation time	162850503413 ps
CPU time	36.2 seconds
Started	Feb 07 01:20:42 PM PST 24
Finished	Feb 07 01:21:19 PM PST 24
Peak memory	201620 kb
Host	smart-5b172218-22fd-439c-8bf4-52edf0fba5ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004504249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4004504249
Directory	/workspace/13.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.247630444
Short name	T680
Test name
Test status
Simulation time	165145174338 ps
CPU time	205.83 seconds
Started	Feb 07 01:20:48 PM PST 24
Finished	Feb 07 01:24:15 PM PST 24
Peak memory	201668 kb
Host	smart-f3f451ea-888d-4d18-ad82-59d420540b1f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=247630444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup t_fixed.247630444
Directory	/workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_polled.2907470720
Short name	T115
Test name
Test status
Simulation time	173383826706 ps
CPU time	269.06 seconds
Started	Feb 07 01:20:49 PM PST 24
Finished	Feb 07 01:25:18 PM PST 24
Peak memory	201536 kb
Host	smart-ff159b52-1499-4dd2-a7ac-ea686585605a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907470720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2907470720
Directory	/workspace/13.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3148060674
Short name	T421
Test name
Test status
Simulation time	492191688713 ps
CPU time	288.27 seconds
Started	Feb 07 01:20:47 PM PST 24
Finished	Feb 07 01:25:35 PM PST 24
Peak memory	201536 kb
Host	smart-5c8adf36-77c1-48af-a790-6fe11bad875a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148060674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix ed.3148060674
Directory	/workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_wakeup.2292458658
Short name	T158
Test name
Test status
Simulation time	494615304029 ps
CPU time	298.76 seconds
Started	Feb 07 01:20:56 PM PST 24
Finished	Feb 07 01:25:55 PM PST 24
Peak memory	201672 kb
Host	smart-63240b5c-37bb-4044-b494-23c026500f9e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292458658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters _wakeup.2292458658
Directory	/workspace/13.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2102581946
Short name	T716
Test name
Test status
Simulation time	167618807579 ps
CPU time	43.56 seconds
Started	Feb 07 01:21:00 PM PST 24
Finished	Feb 07 01:21:44 PM PST 24
Peak memory	201624 kb
Host	smart-5a388933-4417-45a9-aa13-74c1015183ab
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102581946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .adc_ctrl_filters_wakeup_fixed.2102581946
Directory	/workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_fsm_reset.2534953702
Short name	T566
Test name
Test status
Simulation time	72710872244 ps
CPU time	343.51 seconds
Started	Feb 07 01:23:10 PM PST 24
Finished	Feb 07 01:28:54 PM PST 24
Peak memory	201576 kb
Host	smart-d946597c-41ed-4d0f-a3ed-0de094abc62d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534953702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2534953702
Directory	/workspace/13.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/13.adc_ctrl_lowpower_counter.892692980
Short name	T671
Test name
Test status
Simulation time	31592667195 ps
CPU time	69.29 seconds
Started	Feb 07 01:20:58 PM PST 24
Finished	Feb 07 01:22:08 PM PST 24
Peak memory	201392 kb
Host	smart-402376ea-1b73-4d64-8b38-84ae37b280c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=892692980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.892692980
Directory	/workspace/13.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/13.adc_ctrl_poweron_counter.3018183086
Short name	T593
Test name
Test status
Simulation time	4063700365 ps
CPU time	10.1 seconds
Started	Feb 07 01:22:59 PM PST 24
Finished	Feb 07 01:23:11 PM PST 24
Peak memory	199792 kb
Host	smart-5cc80b5b-ef5b-4a86-a8e1-0999cd5397e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018183086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3018183086
Directory	/workspace/13.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/13.adc_ctrl_smoke.1515638229
Short name	T437
Test name
Test status
Simulation time	5849259811 ps
CPU time	7.98 seconds
Started	Feb 07 01:20:50 PM PST 24
Finished	Feb 07 01:20:58 PM PST 24
Peak memory	201424 kb
Host	smart-b3186113-1cae-4ddb-8d2c-b729b4b90061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515638229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1515638229
Directory	/workspace/13.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.adc_ctrl_alert_test.917064408
Short name	T475
Test name
Test status
Simulation time	468875714 ps
CPU time	0.85 seconds
Started	Feb 07 01:23:09 PM PST 24
Finished	Feb 07 01:23:11 PM PST 24
Peak memory	200852 kb
Host	smart-a65ecfd7-c000-41ef-82b2-1cdb4796fd8f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917064408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.917064408
Directory	/workspace/14.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_both.4030107762
Short name	T780
Test name
Test status
Simulation time	165072895220 ps
CPU time	378.84 seconds
Started	Feb 07 01:20:58 PM PST 24
Finished	Feb 07 01:27:18 PM PST 24
Peak memory	201564 kb
Host	smart-a2e4ff88-f93b-4728-9df4-5a81cbd76cd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030107762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4030107762
Directory	/workspace/14.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_interrupt.2371606220
Short name	T273
Test name
Test status
Simulation time	327324489834 ps
CPU time	206.42 seconds
Started	Feb 07 01:20:57 PM PST 24
Finished	Feb 07 01:24:24 PM PST 24
Peak memory	201664 kb
Host	smart-06c84961-0cc6-4bda-97a4-6af3f2c7a280
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371606220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2371606220
Directory	/workspace/14.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3201657141
Short name	T837
Test name
Test status
Simulation time	168742109385 ps
CPU time	356.37 seconds
Started	Feb 07 01:20:56 PM PST 24
Finished	Feb 07 01:26:53 PM PST 24
Peak memory	201556 kb
Host	smart-272fea6b-6c40-4109-9bb9-e309e12ab706
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201657141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru pt_fixed.3201657141
Directory	/workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_polled.173703198
Short name	T578
Test name
Test status
Simulation time	166202292137 ps
CPU time	331.51 seconds
Started	Feb 07 01:23:10 PM PST 24
Finished	Feb 07 01:28:43 PM PST 24
Peak memory	201360 kb
Host	smart-a6c0a54e-cc14-46b8-8eee-57b874b526e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173703198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.173703198
Directory	/workspace/14.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3010732828
Short name	T484
Test name
Test status
Simulation time	164806949274 ps
CPU time	85.5 seconds
Started	Feb 07 01:23:10 PM PST 24
Finished	Feb 07 01:24:36 PM PST 24
Peak memory	201304 kb
Host	smart-9e0192f9-37a3-452d-ae8c-1abc7bbfa214
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010732828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix ed.3010732828
Directory	/workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3550603914
Short name	T515
Test name
Test status
Simulation time	496567763312 ps
CPU time	531.51 seconds
Started	Feb 07 01:20:56 PM PST 24
Finished	Feb 07 01:29:48 PM PST 24
Peak memory	201572 kb
Host	smart-f77220cb-18e5-4c7b-9ba8-07a2285184af
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550603914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14 .adc_ctrl_filters_wakeup_fixed.3550603914
Directory	/workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_fsm_reset.4000203692
Short name	T843
Test name
Test status
Simulation time	78724857244 ps
CPU time	332.67 seconds
Started	Feb 07 01:23:10 PM PST 24
Finished	Feb 07 01:28:44 PM PST 24
Peak memory	201640 kb
Host	smart-b02dabd8-8e4a-4f27-b94b-149a2cd460f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000203692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.4000203692
Directory	/workspace/14.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/14.adc_ctrl_lowpower_counter.3147809584
Short name	T448
Test name
Test status
Simulation time	26074712279 ps
CPU time	15.76 seconds
Started	Feb 07 01:21:03 PM PST 24
Finished	Feb 07 01:21:20 PM PST 24
Peak memory	201284 kb
Host	smart-b52b98a8-bd74-4c1c-8bce-3fce145d4f41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147809584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3147809584
Directory	/workspace/14.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/14.adc_ctrl_poweron_counter.2498846230
Short name	T645
Test name
Test status
Simulation time	4502179871 ps
CPU time	3.09 seconds
Started	Feb 07 01:20:55 PM PST 24
Finished	Feb 07 01:20:58 PM PST 24
Peak memory	201356 kb
Host	smart-8bd280e4-befa-4105-a085-b5f200f4b50c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498846230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2498846230
Directory	/workspace/14.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/14.adc_ctrl_smoke.2317431996
Short name	T455
Test name
Test status
Simulation time	5977700578 ps
CPU time	7.67 seconds
Started	Feb 07 01:23:09 PM PST 24
Finished	Feb 07 01:23:17 PM PST 24
Peak memory	200960 kb
Host	smart-f4e02604-b148-4082-943f-e4c7a00c62eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317431996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2317431996
Directory	/workspace/14.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.adc_ctrl_stress_all.4048310323
Short name	T196
Test name
Test status
Simulation time	373783304800 ps
CPU time	433.98 seconds
Started	Feb 07 01:22:59 PM PST 24
Finished	Feb 07 01:30:15 PM PST 24
Peak memory	199964 kb
Host	smart-fd6420ae-95fa-455d-8a96-7fd77eeda900
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048310323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all .4048310323
Directory	/workspace/14.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1950281093
Short name	T51
Test name
Test status
Simulation time	152283305837 ps
CPU time	307.64 seconds
Started	Feb 07 01:20:59 PM PST 24
Finished	Feb 07 01:26:08 PM PST 24
Peak memory	210488 kb
Host	smart-661a9aa0-cd73-465c-a67e-2e46c2132f88
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950281093 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1950281093
Directory	/workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.adc_ctrl_alert_test.4142824806
Short name	T37
Test name
Test status
Simulation time	281093044 ps
CPU time	1.25 seconds
Started	Feb 07 01:21:10 PM PST 24
Finished	Feb 07 01:21:12 PM PST 24
Peak memory	201240 kb
Host	smart-f137838d-d808-4443-a74a-02fd91189c8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142824806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.4142824806
Directory	/workspace/15.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.adc_ctrl_clock_gating.1890770704
Short name	T212
Test name
Test status
Simulation time	359492241700 ps
CPU time	357.05 seconds
Started	Feb 07 01:21:08 PM PST 24
Finished	Feb 07 01:27:06 PM PST 24
Peak memory	201540 kb
Host	smart-736b445e-4866-4ab2-bd87-9b3f5a99124a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890770704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat ing.1890770704
Directory	/workspace/15.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_both.2402313475
Short name	T231
Test name
Test status
Simulation time	166747135934 ps
CPU time	379.2 seconds
Started	Feb 07 01:21:10 PM PST 24
Finished	Feb 07 01:27:29 PM PST 24
Peak memory	201612 kb
Host	smart-c1dff151-1e76-4a9d-9126-7925074c9c72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402313475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2402313475
Directory	/workspace/15.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_interrupt.174967355
Short name	T232
Test name
Test status
Simulation time	168311951817 ps
CPU time	105.76 seconds
Started	Feb 07 01:21:08 PM PST 24
Finished	Feb 07 01:22:54 PM PST 24
Peak memory	201596 kb
Host	smart-7f61fe55-03ae-464f-bc75-e52befc4df30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=174967355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.174967355
Directory	/workspace/15.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4030663593
Short name	T116
Test name
Test status
Simulation time	321041248436 ps
CPU time	203.66 seconds
Started	Feb 07 01:21:12 PM PST 24
Finished	Feb 07 01:24:36 PM PST 24
Peak memory	201620 kb
Host	smart-4674bd18-ef85-4090-b0c6-3e86245f18cf
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030663593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru pt_fixed.4030663593
Directory	/workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_polled.1666121930
Short name	T468
Test name
Test status
Simulation time	328635467849 ps
CPU time	380.26 seconds
Started	Feb 07 01:21:11 PM PST 24
Finished	Feb 07 01:27:32 PM PST 24
Peak memory	201620 kb
Host	smart-5c6ef0ed-06e6-4753-99f5-08defe0433ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666121930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1666121930
Directory	/workspace/15.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.499969066
Short name	T482
Test name
Test status
Simulation time	482704887541 ps
CPU time	252.97 seconds
Started	Feb 07 01:21:09 PM PST 24
Finished	Feb 07 01:25:22 PM PST 24
Peak memory	201580 kb
Host	smart-afa1f2a6-543b-4923-93fd-91539d60872e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=499969066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe d.499969066
Directory	/workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_wakeup.3437262901
Short name	T727
Test name
Test status
Simulation time	501359729075 ps
CPU time	1170.39 seconds
Started	Feb 07 01:21:08 PM PST 24
Finished	Feb 07 01:40:39 PM PST 24
Peak memory	201532 kb
Host	smart-a20b5429-1cee-497a-a935-16f51bbb5dcb
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437262901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters _wakeup.3437262901
Directory	/workspace/15.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1377029341
Short name	T682
Test name
Test status
Simulation time	163674628680 ps
CPU time	382.01 seconds
Started	Feb 07 01:21:08 PM PST 24
Finished	Feb 07 01:27:31 PM PST 24
Peak memory	201588 kb
Host	smart-77b5639e-59ce-41c1-8aea-9bb0f374da6b
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377029341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .adc_ctrl_filters_wakeup_fixed.1377029341
Directory	/workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_fsm_reset.2365584516
Short name	T574
Test name
Test status
Simulation time	124308652371 ps
CPU time	407.92 seconds
Started	Feb 07 01:21:08 PM PST 24
Finished	Feb 07 01:27:57 PM PST 24
Peak memory	201952 kb
Host	smart-aef0a4c3-15f1-4334-b584-8df1fc033cda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365584516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2365584516
Directory	/workspace/15.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/15.adc_ctrl_lowpower_counter.3970764105
Short name	T420
Test name
Test status
Simulation time	31696047536 ps
CPU time	19.04 seconds
Started	Feb 07 01:21:08 PM PST 24
Finished	Feb 07 01:21:28 PM PST 24
Peak memory	201396 kb
Host	smart-cab56136-f86e-4521-9420-0bdd6bcf3076
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970764105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3970764105
Directory	/workspace/15.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/15.adc_ctrl_poweron_counter.1432828763
Short name	T503
Test name
Test status
Simulation time	4276087464 ps
CPU time	3.34 seconds
Started	Feb 07 01:21:09 PM PST 24
Finished	Feb 07 01:21:13 PM PST 24
Peak memory	201368 kb
Host	smart-b6a80af6-d5d8-426a-927c-607845cce8ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432828763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1432828763
Directory	/workspace/15.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/15.adc_ctrl_smoke.3073782317
Short name	T699
Test name
Test status
Simulation time	5814266261 ps
CPU time	14.46 seconds
Started	Feb 07 01:21:03 PM PST 24
Finished	Feb 07 01:21:18 PM PST 24
Peak memory	201232 kb
Host	smart-b3d054e0-c4c7-4938-8c06-34cfe461d3b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073782317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3073782317
Directory	/workspace/15.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.adc_ctrl_stress_all.765119026
Short name	T745
Test name
Test status
Simulation time	8065199043 ps
CPU time	5.7 seconds
Started	Feb 07 01:21:09 PM PST 24
Finished	Feb 07 01:21:15 PM PST 24
Peak memory	201420 kb
Host	smart-25b07c7d-5a88-4358-befe-52fa7da37dac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765119026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all. 765119026
Directory	/workspace/15.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3254315197
Short name	T270
Test name
Test status
Simulation time	110698241636 ps
CPU time	231.18 seconds
Started	Feb 07 01:21:09 PM PST 24
Finished	Feb 07 01:25:01 PM PST 24
Peak memory	209968 kb
Host	smart-c8a8ab98-22b6-4e50-a8e4-b28e2cfcdf07
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254315197 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3254315197
Directory	/workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.adc_ctrl_alert_test.1481052681
Short name	T430
Test name
Test status
Simulation time	295588898 ps
CPU time	0.97 seconds
Started	Feb 07 01:21:39 PM PST 24
Finished	Feb 07 01:21:44 PM PST 24
Peak memory	201036 kb
Host	smart-c2f19eb0-50e0-432c-a5aa-1a42aeaa7053
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481052681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1481052681
Directory	/workspace/16.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.adc_ctrl_clock_gating.3086877846
Short name	T216
Test name
Test status
Simulation time	164541481584 ps
CPU time	95.57 seconds
Started	Feb 07 01:21:29 PM PST 24
Finished	Feb 07 01:23:05 PM PST 24
Peak memory	201544 kb
Host	smart-900e51d5-5b13-4916-bb4d-1dc1180d9bda
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086877846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat ing.3086877846
Directory	/workspace/16.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_both.3875212047
Short name	T596
Test name
Test status
Simulation time	328178828197 ps
CPU time	748.94 seconds
Started	Feb 07 01:21:30 PM PST 24
Finished	Feb 07 01:33:59 PM PST 24
Peak memory	201708 kb
Host	smart-fbf3172e-4e88-46fb-856c-3573d1ca2fe9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875212047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3875212047
Directory	/workspace/16.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_interrupt.2070192653
Short name	T267
Test name
Test status
Simulation time	504442390451 ps
CPU time	210.83 seconds
Started	Feb 07 01:21:31 PM PST 24
Finished	Feb 07 01:25:02 PM PST 24
Peak memory	201648 kb
Host	smart-aa85889d-7295-440c-92dc-ae8134d59072
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070192653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2070192653
Directory	/workspace/16.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1820043409
Short name	T389
Test name
Test status
Simulation time	326564103922 ps
CPU time	364.11 seconds
Started	Feb 07 01:21:31 PM PST 24
Finished	Feb 07 01:27:36 PM PST 24
Peak memory	201504 kb
Host	smart-c6497e23-e59d-4196-8412-e935b3a273b6
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820043409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru pt_fixed.1820043409
Directory	/workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_polled.3139202870
Short name	T799
Test name
Test status
Simulation time	162822251995 ps
CPU time	352.23 seconds
Started	Feb 07 01:21:09 PM PST 24
Finished	Feb 07 01:27:02 PM PST 24
Peak memory	201628 kb
Host	smart-65687e44-3701-4c76-8458-98e29bc972e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139202870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3139202870
Directory	/workspace/16.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.572543801
Short name	T426
Test name
Test status
Simulation time	486862779738 ps
CPU time	1149.87 seconds
Started	Feb 07 01:21:27 PM PST 24
Finished	Feb 07 01:40:38 PM PST 24
Peak memory	201516 kb
Host	smart-3b6c16e6-d933-4ac7-bc29-2e55cd655500
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=572543801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe d.572543801
Directory	/workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_wakeup.3653653873
Short name	T283
Test name
Test status
Simulation time	484214656980 ps
CPU time	1028.21 seconds
Started	Feb 07 01:21:31 PM PST 24
Finished	Feb 07 01:38:40 PM PST 24
Peak memory	201588 kb
Host	smart-ae286f82-17fc-44b2-a6c8-7685089b1fd3
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653653873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters _wakeup.3653653873
Directory	/workspace/16.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1245357762
Short name	T401
Test name
Test status
Simulation time	496557659049 ps
CPU time	1028.89 seconds
Started	Feb 07 01:21:30 PM PST 24
Finished	Feb 07 01:38:39 PM PST 24
Peak memory	201548 kb
Host	smart-acea922f-1948-4b3a-bcbf-0a9b19206950
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245357762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .adc_ctrl_filters_wakeup_fixed.1245357762
Directory	/workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_fsm_reset.3667873917
Short name	T496
Test name
Test status
Simulation time	125384784639 ps
CPU time	650.2 seconds
Started	Feb 07 01:21:31 PM PST 24
Finished	Feb 07 01:32:21 PM PST 24
Peak memory	201868 kb
Host	smart-910b6c6c-fd12-4b00-9a0b-391ffc00d544
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667873917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3667873917
Directory	/workspace/16.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/16.adc_ctrl_lowpower_counter.3084393611
Short name	T732
Test name
Test status
Simulation time	40522388044 ps
CPU time	45.53 seconds
Started	Feb 07 01:21:30 PM PST 24
Finished	Feb 07 01:22:16 PM PST 24
Peak memory	201280 kb
Host	smart-68894168-2f7e-4636-b8c4-586900e96b0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084393611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3084393611
Directory	/workspace/16.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/16.adc_ctrl_poweron_counter.3234733106
Short name	T456
Test name
Test status
Simulation time	5548794868 ps
CPU time	4.15 seconds
Started	Feb 07 01:21:30 PM PST 24
Finished	Feb 07 01:21:35 PM PST 24
Peak memory	201380 kb
Host	smart-92d495c1-9cae-4f4e-b91c-708a3387c291
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234733106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3234733106
Directory	/workspace/16.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/16.adc_ctrl_smoke.3057878425
Short name	T487
Test name
Test status
Simulation time	5520170841 ps
CPU time	3.63 seconds
Started	Feb 07 01:23:10 PM PST 24
Finished	Feb 07 01:23:14 PM PST 24
Peak memory	201128 kb
Host	smart-5026c55c-1bc4-406d-830f-1c8291a728c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057878425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3057878425
Directory	/workspace/16.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.adc_ctrl_stress_all.1462497650
Short name	T650
Test name
Test status
Simulation time	197354177232 ps
CPU time	111.23 seconds
Started	Feb 07 01:21:30 PM PST 24
Finished	Feb 07 01:23:22 PM PST 24
Peak memory	201540 kb
Host	smart-8b104cbd-e81e-44ef-8f30-558d3fcb128c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462497650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all .1462497650
Directory	/workspace/16.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1213912964
Short name	T257
Test name
Test status
Simulation time	405747404944 ps
CPU time	150.51 seconds
Started	Feb 07 01:21:27 PM PST 24
Finished	Feb 07 01:23:59 PM PST 24
Peak memory	210256 kb
Host	smart-49052f5f-b1d1-479a-9d0f-15f865d4f055
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213912964 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1213912964
Directory	/workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.adc_ctrl_alert_test.744862845
Short name	T512
Test name
Test status
Simulation time	565606313 ps
CPU time	0.73 seconds
Started	Feb 07 01:21:52 PM PST 24
Finished	Feb 07 01:21:53 PM PST 24
Peak memory	201276 kb
Host	smart-5cc1ee3a-5569-4997-b7ab-5824f1842c37
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744862845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.744862845
Directory	/workspace/17.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_both.3025292071
Short name	T657
Test name
Test status
Simulation time	163255035584 ps
CPU time	388.1 seconds
Started	Feb 07 01:21:36 PM PST 24
Finished	Feb 07 01:28:11 PM PST 24
Peak memory	201632 kb
Host	smart-048ca552-3746-455f-811b-f83c4ed7b2b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025292071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3025292071
Directory	/workspace/17.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_interrupt.4117824430
Short name	T87
Test name
Test status
Simulation time	164044734113 ps
CPU time	163.82 seconds
Started	Feb 07 01:21:37 PM PST 24
Finished	Feb 07 01:24:27 PM PST 24
Peak memory	201528 kb
Host	smart-a14ca00a-aae4-4584-b4bd-aa5b931de93d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117824430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4117824430
Directory	/workspace/17.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1088678034
Short name	T823
Test name
Test status
Simulation time	488968326940 ps
CPU time	296.67 seconds
Started	Feb 07 01:21:37 PM PST 24
Finished	Feb 07 01:26:40 PM PST 24
Peak memory	201660 kb
Host	smart-1230f422-a876-4779-aca5-33feabe30200
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088678034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru pt_fixed.1088678034
Directory	/workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_polled.2380084049
Short name	T282
Test name
Test status
Simulation time	165782241175 ps
CPU time	200.33 seconds
Started	Feb 07 01:23:07 PM PST 24
Finished	Feb 07 01:26:28 PM PST 24
Peak memory	199044 kb
Host	smart-525a147a-1d39-4400-97d3-cc5c14fce967
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380084049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2380084049
Directory	/workspace/17.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2664922187
Short name	T617
Test name
Test status
Simulation time	486632254476 ps
CPU time	553.68 seconds
Started	Feb 07 01:21:38 PM PST 24
Finished	Feb 07 01:30:57 PM PST 24
Peak memory	201656 kb
Host	smart-56b3140a-cac7-400d-9859-ad1337cc5383
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664922187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix ed.2664922187
Directory	/workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_wakeup.1878160173
Short name	T150
Test name
Test status
Simulation time	329571763582 ps
CPU time	129.11 seconds
Started	Feb 07 01:21:38 PM PST 24
Finished	Feb 07 01:23:52 PM PST 24
Peak memory	201188 kb
Host	smart-2345aeee-c818-4d6c-9c70-d0041f1036f2
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878160173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters _wakeup.1878160173
Directory	/workspace/17.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1297249151
Short name	T474
Test name
Test status
Simulation time	166956869747 ps
CPU time	118.26 seconds
Started	Feb 07 01:21:37 PM PST 24
Finished	Feb 07 01:23:41 PM PST 24
Peak memory	201628 kb
Host	smart-36697d61-9fe8-4db8-a38d-0bcaa4faa8a1
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297249151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .adc_ctrl_filters_wakeup_fixed.1297249151
Directory	/workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_fsm_reset.1962659415
Short name	T729
Test name
Test status
Simulation time	99673862737 ps
CPU time	436.59 seconds
Started	Feb 07 01:21:53 PM PST 24
Finished	Feb 07 01:29:10 PM PST 24
Peak memory	201900 kb
Host	smart-b60921cd-cf52-44b0-a4ad-f68affab26a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962659415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1962659415
Directory	/workspace/17.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/17.adc_ctrl_lowpower_counter.4263677446
Short name	T845
Test name
Test status
Simulation time	40003254479 ps
CPU time	82.92 seconds
Started	Feb 07 01:21:39 PM PST 24
Finished	Feb 07 01:23:06 PM PST 24
Peak memory	201012 kb
Host	smart-15332b1a-38fd-4a19-9f5f-5ff4019af045
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263677446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4263677446
Directory	/workspace/17.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/17.adc_ctrl_poweron_counter.706433446
Short name	T522
Test name
Test status
Simulation time	5120734967 ps
CPU time	6.32 seconds
Started	Feb 07 01:21:39 PM PST 24
Finished	Feb 07 01:21:50 PM PST 24
Peak memory	201176 kb
Host	smart-f8c15827-46eb-4e41-beea-f9de9655b71c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706433446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.706433446
Directory	/workspace/17.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/17.adc_ctrl_smoke.1982787026
Short name	T499
Test name
Test status
Simulation time	5842749934 ps
CPU time	4.7 seconds
Started	Feb 07 01:21:37 PM PST 24
Finished	Feb 07 01:21:48 PM PST 24
Peak memory	201328 kb
Host	smart-1f0375bc-4356-47ba-ba87-4407d7425c7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982787026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1982787026
Directory	/workspace/17.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.adc_ctrl_stress_all.153859342
Short name	T860
Test name
Test status
Simulation time	77812726600 ps
CPU time	327.84 seconds
Started	Feb 07 01:23:07 PM PST 24
Finished	Feb 07 01:28:35 PM PST 24
Peak memory	199624 kb
Host	smart-f5ed45a9-cd25-43c2-ba1e-118cccccc4a6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153859342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all. 153859342
Directory	/workspace/17.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3721728385
Short name	T114
Test name
Test status
Simulation time	20039915874 ps
CPU time	36.61 seconds
Started	Feb 07 01:21:53 PM PST 24
Finished	Feb 07 01:22:30 PM PST 24
Peak memory	201840 kb
Host	smart-3af97161-94ff-447f-943d-0d4a571c3a4d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721728385 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3721728385
Directory	/workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.adc_ctrl_alert_test.2347789672
Short name	T786
Test name
Test status
Simulation time	317769355 ps
CPU time	0.81 seconds
Started	Feb 07 01:22:27 PM PST 24
Finished	Feb 07 01:22:29 PM PST 24
Peak memory	201256 kb
Host	smart-bae72468-16fa-42c6-b3e0-1ab6f3201951
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347789672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2347789672
Directory	/workspace/18.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_both.2807806704
Short name	T155
Test name
Test status
Simulation time	340823635237 ps
CPU time	96.21 seconds
Started	Feb 07 01:21:53 PM PST 24
Finished	Feb 07 01:23:29 PM PST 24
Peak memory	201612 kb
Host	smart-e7616ef9-f679-4a72-8335-a406156cbec6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2807806704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2807806704
Directory	/workspace/18.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_interrupt.548994572
Short name	T89
Test name
Test status
Simulation time	337337800864 ps
CPU time	788.2 seconds
Started	Feb 07 01:21:55 PM PST 24
Finished	Feb 07 01:35:03 PM PST 24
Peak memory	201516 kb
Host	smart-5e59b5de-7ff9-4fbf-8377-c5dda62bd084
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548994572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.548994572
Directory	/workspace/18.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1400175718
Short name	T723
Test name
Test status
Simulation time	167817152759 ps
CPU time	182.48 seconds
Started	Feb 07 01:21:55 PM PST 24
Finished	Feb 07 01:24:58 PM PST 24
Peak memory	201544 kb
Host	smart-4f6e303e-97c9-4152-82dd-7cfed2e12a96
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400175718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru pt_fixed.1400175718
Directory	/workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_polled.4280670579
Short name	T831
Test name
Test status
Simulation time	164357154284 ps
CPU time	186.56 seconds
Started	Feb 07 01:21:52 PM PST 24
Finished	Feb 07 01:24:59 PM PST 24
Peak memory	201700 kb
Host	smart-cbb126e7-504f-49fb-8eaa-4609144c1356
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280670579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4280670579
Directory	/workspace/18.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.4263135238
Short name	T47
Test name
Test status
Simulation time	497747239737 ps
CPU time	1182.71 seconds
Started	Feb 07 01:21:54 PM PST 24
Finished	Feb 07 01:41:37 PM PST 24
Peak memory	201612 kb
Host	smart-e3b913e0-0eb2-4c21-998f-cef53705a80c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263135238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix ed.4263135238
Directory	/workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_wakeup.887815051
Short name	T213
Test name
Test status
Simulation time	166736427566 ps
CPU time	95.53 seconds
Started	Feb 07 01:23:07 PM PST 24
Finished	Feb 07 01:24:43 PM PST 24
Peak memory	199256 kb
Host	smart-0ebe13a0-f0e1-4e81-9f56-f7ea12517e5c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887815051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_ wakeup.887815051
Directory	/workspace/18.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3471997743
Short name	T398
Test name
Test status
Simulation time	495100649288 ps
CPU time	1090.36 seconds
Started	Feb 07 01:23:07 PM PST 24
Finished	Feb 07 01:41:18 PM PST 24
Peak memory	199396 kb
Host	smart-54813a55-2782-475f-accf-98c78b58e0c5
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471997743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .adc_ctrl_filters_wakeup_fixed.3471997743
Directory	/workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_fsm_reset.3799254512
Short name	T679
Test name
Test status
Simulation time	138300956849 ps
CPU time	470.48 seconds
Started	Feb 07 01:22:27 PM PST 24
Finished	Feb 07 01:30:18 PM PST 24
Peak memory	201856 kb
Host	smart-38b18681-881c-4a43-9ee4-420e258e6e54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799254512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3799254512
Directory	/workspace/18.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/18.adc_ctrl_lowpower_counter.2623856477
Short name	T542
Test name
Test status
Simulation time	29091572047 ps
CPU time	18.27 seconds
Started	Feb 07 01:21:55 PM PST 24
Finished	Feb 07 01:22:13 PM PST 24
Peak memory	201284 kb
Host	smart-8f8777c8-0356-42f5-8de1-a0ca8664474d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623856477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2623856477
Directory	/workspace/18.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/18.adc_ctrl_poweron_counter.645340277
Short name	T569
Test name
Test status
Simulation time	4840728874 ps
CPU time	11.83 seconds
Started	Feb 07 01:21:54 PM PST 24
Finished	Feb 07 01:22:07 PM PST 24
Peak memory	201368 kb
Host	smart-d6669335-a8f2-4065-8631-47645fbc1330
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645340277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.645340277
Directory	/workspace/18.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/18.adc_ctrl_smoke.25607404
Short name	T138
Test name
Test status
Simulation time	5809963623 ps
CPU time	8.17 seconds
Started	Feb 07 01:21:52 PM PST 24
Finished	Feb 07 01:22:01 PM PST 24
Peak memory	201340 kb
Host	smart-f1053842-2d47-4b86-bd8b-a876ad52c507
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25607404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.25607404
Directory	/workspace/18.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.adc_ctrl_stress_all.3050493494
Short name	T771
Test name
Test status
Simulation time	123864497846 ps
CPU time	432.25 seconds
Started	Feb 07 01:22:28 PM PST 24
Finished	Feb 07 01:29:41 PM PST 24
Peak memory	211208 kb
Host	smart-1a7dbe1a-b4b5-42b0-8ff8-5f410a062822
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050493494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all .3050493494
Directory	/workspace/18.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2498219730
Short name	T778
Test name
Test status
Simulation time	165821593608 ps
CPU time	223.57 seconds
Started	Feb 07 01:22:28 PM PST 24
Finished	Feb 07 01:26:12 PM PST 24
Peak memory	217404 kb
Host	smart-546aedf7-86d3-4632-8ae5-5bb0243d13ee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498219730 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2498219730
Directory	/workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.adc_ctrl_alert_test.1856174857
Short name	T450
Test name
Test status
Simulation time	327628252 ps
CPU time	1.19 seconds
Started	Feb 07 01:22:34 PM PST 24
Finished	Feb 07 01:22:36 PM PST 24
Peak memory	201276 kb
Host	smart-23c3abef-3a7f-4c19-8f33-2fd2136d62b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856174857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1856174857
Directory	/workspace/19.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.adc_ctrl_clock_gating.3514149929
Short name	T298
Test name
Test status
Simulation time	336602397355 ps
CPU time	684.82 seconds
Started	Feb 07 01:22:24 PM PST 24
Finished	Feb 07 01:33:49 PM PST 24
Peak memory	201564 kb
Host	smart-b21d2b4b-6a9e-4382-9919-74852f145f23
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514149929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat ing.3514149929
Directory	/workspace/19.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_both.230166195
Short name	T664
Test name
Test status
Simulation time	163290217820 ps
CPU time	107.64 seconds
Started	Feb 07 01:22:26 PM PST 24
Finished	Feb 07 01:24:14 PM PST 24
Peak memory	201628 kb
Host	smart-cd7e9227-f7af-4d4d-b9d7-21152493c4e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230166195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.230166195
Directory	/workspace/19.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_interrupt.2030292303
Short name	T793
Test name
Test status
Simulation time	162587845186 ps
CPU time	407.41 seconds
Started	Feb 07 01:22:27 PM PST 24
Finished	Feb 07 01:29:15 PM PST 24
Peak memory	201592 kb
Host	smart-fa0140e9-5c93-4172-a084-d2d85827c046
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030292303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2030292303
Directory	/workspace/19.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3724899079
Short name	T406
Test name
Test status
Simulation time	169000693999 ps
CPU time	205.81 seconds
Started	Feb 07 01:22:27 PM PST 24
Finished	Feb 07 01:25:54 PM PST 24
Peak memory	201528 kb
Host	smart-183dabf5-bdf0-40a4-a80b-2b8c7bad169f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724899079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru pt_fixed.3724899079
Directory	/workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_polled.1468129435
Short name	T790
Test name
Test status
Simulation time	323221792065 ps
CPU time	200.34 seconds
Started	Feb 07 01:22:26 PM PST 24
Finished	Feb 07 01:25:47 PM PST 24
Peak memory	201564 kb
Host	smart-3464b853-e63b-4ca7-bbf1-b3360bc15f59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468129435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1468129435
Directory	/workspace/19.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3181395591
Short name	T810
Test name
Test status
Simulation time	327486905645 ps
CPU time	182.12 seconds
Started	Feb 07 01:22:27 PM PST 24
Finished	Feb 07 01:25:30 PM PST 24
Peak memory	201596 kb
Host	smart-19172f63-10d0-4d47-9c85-96eef044d24f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181395591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix ed.3181395591
Directory	/workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_wakeup.3785096310
Short name	T275
Test name
Test status
Simulation time	162664871244 ps
CPU time	234.06 seconds
Started	Feb 07 01:22:28 PM PST 24
Finished	Feb 07 01:26:22 PM PST 24
Peak memory	201616 kb
Host	smart-d894c1fa-77e8-4d9f-ae92-aedb63c8c7d7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785096310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters _wakeup.3785096310
Directory	/workspace/19.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1850594154
Short name	T530
Test name
Test status
Simulation time	494379187187 ps
CPU time	1209.69 seconds
Started	Feb 07 01:22:28 PM PST 24
Finished	Feb 07 01:42:38 PM PST 24
Peak memory	201564 kb
Host	smart-bf606a35-1204-471d-8172-859c60175be5
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850594154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .adc_ctrl_filters_wakeup_fixed.1850594154
Directory	/workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_lowpower_counter.1990879456
Short name	T662
Test name
Test status
Simulation time	42834057074 ps
CPU time	13.35 seconds
Started	Feb 07 01:22:26 PM PST 24
Finished	Feb 07 01:22:40 PM PST 24
Peak memory	201324 kb
Host	smart-b075d22d-10c8-453b-8a26-745be37d7a5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990879456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1990879456
Directory	/workspace/19.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/19.adc_ctrl_poweron_counter.2965807713
Short name	T412
Test name
Test status
Simulation time	5394557323 ps
CPU time	7.22 seconds
Started	Feb 07 01:22:28 PM PST 24
Finished	Feb 07 01:22:35 PM PST 24
Peak memory	201392 kb
Host	smart-5185869f-739c-4178-b8a8-4915936b9cb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965807713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2965807713
Directory	/workspace/19.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/19.adc_ctrl_smoke.943539332
Short name	T594
Test name
Test status
Simulation time	6107697642 ps
CPU time	4.36 seconds
Started	Feb 07 01:22:26 PM PST 24
Finished	Feb 07 01:22:31 PM PST 24
Peak memory	201364 kb
Host	smart-2e3eda4e-5529-4505-a93a-062402f52cf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943539332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.943539332
Directory	/workspace/19.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.adc_ctrl_stress_all.1971041958
Short name	T668
Test name
Test status
Simulation time	264629215236 ps
CPU time	855.67 seconds
Started	Feb 07 01:22:34 PM PST 24
Finished	Feb 07 01:36:51 PM PST 24
Peak memory	210144 kb
Host	smart-cc93ea89-0e55-429a-8260-bf5034b6854c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971041958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all .1971041958
Directory	/workspace/19.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.adc_ctrl_alert_test.406775887
Short name	T579
Test name
Test status
Simulation time	453180275 ps
CPU time	1.71 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:19:16 PM PST 24
Peak memory	201148 kb
Host	smart-b4d300ea-7d31-4f13-a43c-95ab44473430
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406775887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.406775887
Directory	/workspace/2.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_both.1073941394
Short name	T271
Test name
Test status
Simulation time	495879002409 ps
CPU time	1071.23 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:37:07 PM PST 24
Peak memory	201612 kb
Host	smart-dba4273f-dad5-4a31-af6d-efbc0b05a7aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073941394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1073941394
Directory	/workspace/2.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_interrupt.3793719442
Short name	T296
Test name
Test status
Simulation time	164046806141 ps
CPU time	384.58 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:25:40 PM PST 24
Peak memory	201576 kb
Host	smart-b0f0f3d1-e81a-415e-9a06-cabbd9fbfc10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3793719442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3793719442
Directory	/workspace/2.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1104152601
Short name	T428
Test name
Test status
Simulation time	164614169165 ps
CPU time	346.19 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:25:02 PM PST 24
Peak memory	201444 kb
Host	smart-f528acb0-0749-4cce-b5a7-ae64a8ed8d6b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104152601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup t_fixed.1104152601
Directory	/workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_polled.3998759883
Short name	T631
Test name
Test status
Simulation time	165710141709 ps
CPU time	103.36 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:20:59 PM PST 24
Peak memory	201616 kb
Host	smart-3bcdfdd9-28a1-4aa9-99bf-e14fa8144673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998759883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3998759883
Directory	/workspace/2.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1021423952
Short name	T427
Test name
Test status
Simulation time	328106677251 ps
CPU time	201.01 seconds
Started	Feb 07 01:19:16 PM PST 24
Finished	Feb 07 01:22:38 PM PST 24
Peak memory	201492 kb
Host	smart-e14b2f1e-871c-4456-a487-4a74f135cead
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021423952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe d.1021423952
Directory	/workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_wakeup.2791615868
Short name	T471
Test name
Test status
Simulation time	165477290731 ps
CPU time	196.67 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:22:32 PM PST 24
Peak memory	201640 kb
Host	smart-ce4174cd-37cf-45bb-9a6b-276326ff3677
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791615868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_ wakeup.2791615868
Directory	/workspace/2.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4284706900
Short name	T149
Test name
Test status
Simulation time	159887046603 ps
CPU time	88.54 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:20:43 PM PST 24
Peak memory	201516 kb
Host	smart-96687994-1d19-4d68-aa41-d997d7cd3592
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284706900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. adc_ctrl_filters_wakeup_fixed.4284706900
Directory	/workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_fsm_reset.1926555720
Short name	T422
Test name
Test status
Simulation time	88570415290 ps
CPU time	360.37 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:25:16 PM PST 24
Peak memory	201220 kb
Host	smart-3e087002-52c6-48e4-8d7a-5e42da549d62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926555720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1926555720
Directory	/workspace/2.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/2.adc_ctrl_lowpower_counter.1304388329
Short name	T600
Test name
Test status
Simulation time	27721357425 ps
CPU time	22.97 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:19:38 PM PST 24
Peak memory	201340 kb
Host	smart-44f4e1ac-09cf-48d6-aef4-b3f2b13414c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304388329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1304388329
Directory	/workspace/2.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/2.adc_ctrl_poweron_counter.2295120553
Short name	T718
Test name
Test status
Simulation time	4822044004 ps
CPU time	11.18 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:19:26 PM PST 24
Peak memory	201212 kb
Host	smart-a8a28f67-f677-4597-9ea1-849c84d49f7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295120553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2295120553
Directory	/workspace/2.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/2.adc_ctrl_sec_cm.3782548982
Short name	T43
Test name
Test status
Simulation time	4445784390 ps
CPU time	10.28 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:19:26 PM PST 24
Peak memory	216040 kb
Host	smart-513e21e1-e21f-4a3f-bdbe-8885fb966dab
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782548982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3782548982
Directory	/workspace/2.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.adc_ctrl_smoke.1674089926
Short name	T747
Test name
Test status
Simulation time	6135739531 ps
CPU time	2.24 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:19:17 PM PST 24
Peak memory	201384 kb
Host	smart-52398b64-3f98-4597-ac53-6b246312f86a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674089926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1674089926
Directory	/workspace/2.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1785311452
Short name	T580
Test name
Test status
Simulation time	17882492977 ps
CPU time	40.21 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:19:55 PM PST 24
Peak memory	201752 kb
Host	smart-22c50cb6-e0cf-430a-975d-17e6d6b0c0b5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785311452 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1785311452
Directory	/workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.adc_ctrl_alert_test.3744012646
Short name	T586
Test name
Test status
Simulation time	341890683 ps
CPU time	1.39 seconds
Started	Feb 07 01:22:54 PM PST 24
Finished	Feb 07 01:22:56 PM PST 24
Peak memory	201268 kb
Host	smart-f0e87faa-531c-48bc-bcc6-9b622ca28019
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744012646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3744012646
Directory	/workspace/20.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.adc_ctrl_clock_gating.1784177382
Short name	T690
Test name
Test status
Simulation time	159425546751 ps
CPU time	374.94 seconds
Started	Feb 07 01:22:35 PM PST 24
Finished	Feb 07 01:28:51 PM PST 24
Peak memory	201676 kb
Host	smart-a9abd344-87c9-432d-b016-1829938883da
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784177382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat ing.1784177382
Directory	/workspace/20.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_both.767808632
Short name	T254
Test name
Test status
Simulation time	337249967232 ps
CPU time	735.4 seconds
Started	Feb 07 01:22:35 PM PST 24
Finished	Feb 07 01:34:51 PM PST 24
Peak memory	201640 kb
Host	smart-d6b0c030-cac6-4b59-9320-8094b6f06e1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=767808632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.767808632
Directory	/workspace/20.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_interrupt.3857880297
Short name	T217
Test name
Test status
Simulation time	479527504695 ps
CPU time	1172 seconds
Started	Feb 07 01:22:34 PM PST 24
Finished	Feb 07 01:42:07 PM PST 24
Peak memory	201636 kb
Host	smart-7592ef46-cef4-4ac7-a982-6b7c439e03f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857880297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3857880297
Directory	/workspace/20.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.79588119
Short name	T447
Test name
Test status
Simulation time	168067629868 ps
CPU time	414.32 seconds
Started	Feb 07 01:22:34 PM PST 24
Finished	Feb 07 01:29:29 PM PST 24
Peak memory	201536 kb
Host	smart-b1049748-693e-4f69-bb3e-ae81f9898071
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=79588119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt _fixed.79588119
Directory	/workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_polled.912327999
Short name	T760
Test name
Test status
Simulation time	505637300221 ps
CPU time	1111.37 seconds
Started	Feb 07 01:22:39 PM PST 24
Finished	Feb 07 01:41:11 PM PST 24
Peak memory	201556 kb
Host	smart-9676a715-072a-4ce6-b9d0-79cbbdca8ffd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912327999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.912327999
Directory	/workspace/20.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.282921825
Short name	T646
Test name
Test status
Simulation time	499098381801 ps
CPU time	611.43 seconds
Started	Feb 07 01:22:37 PM PST 24
Finished	Feb 07 01:32:49 PM PST 24
Peak memory	201536 kb
Host	smart-d5fe8764-9acc-412a-b79f-aade24835cb7
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=282921825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe d.282921825
Directory	/workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_wakeup.3380170991
Short name	T687
Test name
Test status
Simulation time	161334208357 ps
CPU time	40.94 seconds
Started	Feb 07 01:22:35 PM PST 24
Finished	Feb 07 01:23:17 PM PST 24
Peak memory	201672 kb
Host	smart-55c45f11-6dd9-4c3d-ba83-509001694e51
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380170991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters _wakeup.3380170991
Directory	/workspace/20.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2231715786
Short name	T762
Test name
Test status
Simulation time	163592345099 ps
CPU time	45.47 seconds
Started	Feb 07 01:22:33 PM PST 24
Finished	Feb 07 01:23:19 PM PST 24
Peak memory	201668 kb
Host	smart-bb63d017-6cdb-4588-ba3f-b5d1e5ed6060
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231715786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20 .adc_ctrl_filters_wakeup_fixed.2231715786
Directory	/workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_fsm_reset.2132082469
Short name	T165
Test name
Test status
Simulation time	86851853138 ps
CPU time	440.59 seconds
Started	Feb 07 01:22:54 PM PST 24
Finished	Feb 07 01:30:16 PM PST 24
Peak memory	201876 kb
Host	smart-9aad3c7c-5e32-43a9-b593-33b273d4ef96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132082469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2132082469
Directory	/workspace/20.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/20.adc_ctrl_lowpower_counter.2732692930
Short name	T849
Test name
Test status
Simulation time	26313064673 ps
CPU time	15.04 seconds
Started	Feb 07 01:22:34 PM PST 24
Finished	Feb 07 01:22:50 PM PST 24
Peak memory	201400 kb
Host	smart-584ba04f-5e21-448d-a970-848c5e0a80d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732692930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2732692930
Directory	/workspace/20.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/20.adc_ctrl_poweron_counter.1130357847
Short name	T835
Test name
Test status
Simulation time	2835032708 ps
CPU time	7.31 seconds
Started	Feb 07 01:22:37 PM PST 24
Finished	Feb 07 01:22:45 PM PST 24
Peak memory	201372 kb
Host	smart-7d722d05-754c-4a04-8e82-903aaeb38e29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130357847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1130357847
Directory	/workspace/20.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/20.adc_ctrl_smoke.2033585269
Short name	T802
Test name
Test status
Simulation time	6060621380 ps
CPU time	4.26 seconds
Started	Feb 07 01:22:36 PM PST 24
Finished	Feb 07 01:22:40 PM PST 24
Peak memory	201416 kb
Host	smart-51f285a9-2382-4a9b-bf33-834d320b3a04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033585269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2033585269
Directory	/workspace/20.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.adc_ctrl_stress_all.3540926170
Short name	T591
Test name
Test status
Simulation time	176682657472 ps
CPU time	197.62 seconds
Started	Feb 07 01:22:52 PM PST 24
Finished	Feb 07 01:26:10 PM PST 24
Peak memory	201536 kb
Host	smart-d7fe473c-5a25-4d29-9218-00e320f8b961
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540926170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all .3540926170
Directory	/workspace/20.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4008890078
Short name	T822
Test name
Test status
Simulation time	55370915317 ps
CPU time	32.16 seconds
Started	Feb 07 01:22:58 PM PST 24
Finished	Feb 07 01:23:30 PM PST 24
Peak memory	209916 kb
Host	smart-bc3ee147-de1d-4187-9900-258d8b3de86f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008890078 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4008890078
Directory	/workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.adc_ctrl_alert_test.3672417793
Short name	T746
Test name
Test status
Simulation time	438804383 ps
CPU time	0.76 seconds
Started	Feb 07 01:23:10 PM PST 24
Finished	Feb 07 01:23:12 PM PST 24
Peak memory	201252 kb
Host	smart-1253ef54-ae07-41c6-8ee8-9adebf850daa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672417793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3672417793
Directory	/workspace/21.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1361650893
Short name	T829
Test name
Test status
Simulation time	166729979283 ps
CPU time	196.29 seconds
Started	Feb 07 01:22:54 PM PST 24
Finished	Feb 07 01:26:11 PM PST 24
Peak memory	201428 kb
Host	smart-da4ec03e-086d-42d2-868a-73038737e1cb
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361650893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru pt_fixed.1361650893
Directory	/workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_polled.80645591
Short name	T824
Test name
Test status
Simulation time	498798265661 ps
CPU time	297.83 seconds
Started	Feb 07 01:22:58 PM PST 24
Finished	Feb 07 01:27:57 PM PST 24
Peak memory	201648 kb
Host	smart-ee06cd6b-2652-411d-8bc0-39463df3ba8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80645591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.80645591
Directory	/workspace/21.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1711573561
Short name	T808
Test name
Test status
Simulation time	328479926533 ps
CPU time	104.06 seconds
Started	Feb 07 01:22:59 PM PST 24
Finished	Feb 07 01:24:43 PM PST 24
Peak memory	201624 kb
Host	smart-c08b00ef-c478-4b5d-a4d8-c4c69c3baa97
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711573561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix ed.1711573561
Directory	/workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_wakeup.1314625413
Short name	T100
Test name
Test status
Simulation time	163970556132 ps
CPU time	187.62 seconds
Started	Feb 07 01:22:56 PM PST 24
Finished	Feb 07 01:26:04 PM PST 24
Peak memory	201636 kb
Host	smart-8fdd1017-c1a9-4c1f-bdcf-eb8cb87c24d8
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314625413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters _wakeup.1314625413
Directory	/workspace/21.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1524367948
Short name	T548
Test name
Test status
Simulation time	163429522842 ps
CPU time	34.89 seconds
Started	Feb 07 01:23:02 PM PST 24
Finished	Feb 07 01:23:38 PM PST 24
Peak memory	201560 kb
Host	smart-933638f1-5805-47a8-83e7-ec726b97ebb2
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524367948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .adc_ctrl_filters_wakeup_fixed.1524367948
Directory	/workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_fsm_reset.3609564551
Short name	T11
Test name
Test status
Simulation time	105372865226 ps
CPU time	507.59 seconds
Started	Feb 07 01:23:09 PM PST 24
Finished	Feb 07 01:31:38 PM PST 24
Peak memory	201860 kb
Host	smart-e2e9d3bf-fb50-40f9-a8f6-a9c1d37db1f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3609564551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3609564551
Directory	/workspace/21.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/21.adc_ctrl_lowpower_counter.3348048486
Short name	T433
Test name
Test status
Simulation time	35970923823 ps
CPU time	87.24 seconds
Started	Feb 07 01:22:52 PM PST 24
Finished	Feb 07 01:24:20 PM PST 24
Peak memory	201376 kb
Host	smart-26b7add2-8bef-47e1-9e69-ff143c51cb6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348048486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3348048486
Directory	/workspace/21.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/21.adc_ctrl_poweron_counter.4121171539
Short name	T409
Test name
Test status
Simulation time	4121873246 ps
CPU time	10.66 seconds
Started	Feb 07 01:22:54 PM PST 24
Finished	Feb 07 01:23:05 PM PST 24
Peak memory	201356 kb
Host	smart-53e8e924-2a3f-46bf-8ebd-d3b515124718
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121171539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4121171539
Directory	/workspace/21.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/21.adc_ctrl_smoke.2132761563
Short name	T514
Test name
Test status
Simulation time	5531879264 ps
CPU time	13.06 seconds
Started	Feb 07 01:22:54 PM PST 24
Finished	Feb 07 01:23:08 PM PST 24
Peak memory	201368 kb
Host	smart-ac7e6dbb-a16e-44b1-8392-73c64e64104f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132761563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2132761563
Directory	/workspace/21.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.adc_ctrl_stress_all.3630698332
Short name	T712
Test name
Test status
Simulation time	41579741250 ps
CPU time	98.33 seconds
Started	Feb 07 01:23:09 PM PST 24
Finished	Feb 07 01:24:48 PM PST 24
Peak memory	201420 kb
Host	smart-88265d32-e198-4ffe-a591-efa8b6e28d7f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630698332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all .3630698332
Directory	/workspace/21.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1447100483
Short name	T170
Test name
Test status
Simulation time	313770575979 ps
CPU time	471.41 seconds
Started	Feb 07 01:23:08 PM PST 24
Finished	Feb 07 01:31:00 PM PST 24
Peak memory	217680 kb
Host	smart-ebc9b966-8b61-408d-9a12-ef9214de8785
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447100483 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1447100483
Directory	/workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.adc_ctrl_alert_test.2740981895
Short name	T752
Test name
Test status
Simulation time	516834532 ps
CPU time	1.88 seconds
Started	Feb 07 01:23:20 PM PST 24
Finished	Feb 07 01:23:22 PM PST 24
Peak memory	201240 kb
Host	smart-223cc1dd-e7b9-4c68-96a7-040f6da29509
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740981895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2740981895
Directory	/workspace/22.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.adc_ctrl_clock_gating.3741048439
Short name	T316
Test name
Test status
Simulation time	327275932575 ps
CPU time	162.77 seconds
Started	Feb 07 01:23:19 PM PST 24
Finished	Feb 07 01:26:02 PM PST 24
Peak memory	201668 kb
Host	smart-48f91771-69d6-4e37-a71a-5d243e91cf76
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741048439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat ing.3741048439
Directory	/workspace/22.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_polled.137913081
Short name	T143
Test name
Test status
Simulation time	333241856343 ps
CPU time	79.16 seconds
Started	Feb 07 01:23:09 PM PST 24
Finished	Feb 07 01:24:28 PM PST 24
Peak memory	201712 kb
Host	smart-282ebb86-f2bf-4dc4-ad73-ef74c491c44b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137913081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.137913081
Directory	/workspace/22.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2901505035
Short name	T552
Test name
Test status
Simulation time	165690918799 ps
CPU time	411.7 seconds
Started	Feb 07 01:23:09 PM PST 24
Finished	Feb 07 01:30:01 PM PST 24
Peak memory	201572 kb
Host	smart-e40c9523-6a91-4e6a-a2ad-9d907eb06ba6
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901505035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix ed.2901505035
Directory	/workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1999886942
Short name	T540
Test name
Test status
Simulation time	487311904207 ps
CPU time	498.68 seconds
Started	Feb 07 01:23:20 PM PST 24
Finished	Feb 07 01:31:39 PM PST 24
Peak memory	201556 kb
Host	smart-e9711ef3-8dc8-4d33-8d6b-9fe6e297a5e3
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999886942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .adc_ctrl_filters_wakeup_fixed.1999886942
Directory	/workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/22.adc_ctrl_fsm_reset.3327173090
Short name	T673
Test name
Test status
Simulation time	102966981252 ps
CPU time	374.52 seconds
Started	Feb 07 01:23:18 PM PST 24
Finished	Feb 07 01:29:33 PM PST 24
Peak memory	201876 kb
Host	smart-9d181652-99a2-4d61-abe9-72f300552905
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3327173090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3327173090
Directory	/workspace/22.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/22.adc_ctrl_lowpower_counter.1064971682
Short name	T429
Test name
Test status
Simulation time	38991600603 ps
CPU time	17.23 seconds
Started	Feb 07 01:23:16 PM PST 24
Finished	Feb 07 01:23:34 PM PST 24
Peak memory	201320 kb
Host	smart-b5aebbe7-55d7-460f-8d0b-07b38c6a29ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064971682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1064971682
Directory	/workspace/22.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/22.adc_ctrl_poweron_counter.4181591729
Short name	T669
Test name
Test status
Simulation time	4502797839 ps
CPU time	3.42 seconds
Started	Feb 07 01:23:20 PM PST 24
Finished	Feb 07 01:23:24 PM PST 24
Peak memory	201376 kb
Host	smart-98fe1b7b-8210-42dd-ad70-5240ce63c38b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181591729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.4181591729
Directory	/workspace/22.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/22.adc_ctrl_smoke.1899078267
Short name	T828
Test name
Test status
Simulation time	5697194652 ps
CPU time	13.88 seconds
Started	Feb 07 01:23:09 PM PST 24
Finished	Feb 07 01:23:24 PM PST 24
Peak memory	201336 kb
Host	smart-0403b2b0-dfd8-4ab4-b2fe-c3452a513073
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899078267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1899078267
Directory	/workspace/22.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.adc_ctrl_stress_all.3030299665
Short name	T625
Test name
Test status
Simulation time	114404698768 ps
CPU time	243.18 seconds
Started	Feb 07 01:23:18 PM PST 24
Finished	Feb 07 01:27:22 PM PST 24
Peak memory	201872 kb
Host	smart-407f5ad4-4921-406d-a39e-749919a18637
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030299665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all .3030299665
Directory	/workspace/22.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.adc_ctrl_alert_test.3035946168
Short name	T541
Test name
Test status
Simulation time	429017915 ps
CPU time	1.52 seconds
Started	Feb 07 01:23:39 PM PST 24
Finished	Feb 07 01:23:41 PM PST 24
Peak memory	200820 kb
Host	smart-df987745-aedf-4bf3-9ed0-1b05db3425e9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035946168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3035946168
Directory	/workspace/23.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.adc_ctrl_clock_gating.762606983
Short name	T500
Test name
Test status
Simulation time	166556172927 ps
CPU time	98.01 seconds
Started	Feb 07 01:23:30 PM PST 24
Finished	Feb 07 01:25:09 PM PST 24
Peak memory	201552 kb
Host	smart-d5cc95b0-6794-4682-989e-67c95ebec604
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762606983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati ng.762606983
Directory	/workspace/23.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_interrupt.3812385187
Short name	T558
Test name
Test status
Simulation time	164786953952 ps
CPU time	98.37 seconds
Started	Feb 07 01:23:17 PM PST 24
Finished	Feb 07 01:24:56 PM PST 24
Peak memory	201588 kb
Host	smart-91b21a21-8e19-445e-93ea-c247d6b7c643
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812385187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3812385187
Directory	/workspace/23.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2154018775
Short name	T478
Test name
Test status
Simulation time	161765950704 ps
CPU time	88.85 seconds
Started	Feb 07 01:23:16 PM PST 24
Finished	Feb 07 01:24:46 PM PST 24
Peak memory	201624 kb
Host	smart-b2b450e8-3ce2-4a89-9b5b-bfbeacbe7b7f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154018775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru pt_fixed.2154018775
Directory	/workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_polled.2153032839
Short name	T103
Test name
Test status
Simulation time	330569410529 ps
CPU time	204.46 seconds
Started	Feb 07 01:23:20 PM PST 24
Finished	Feb 07 01:26:45 PM PST 24
Peak memory	201596 kb
Host	smart-80aa988f-21cd-4e40-a520-0730675ae648
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153032839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2153032839
Directory	/workspace/23.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2702241290
Short name	T619
Test name
Test status
Simulation time	491303648142 ps
CPU time	1161.37 seconds
Started	Feb 07 01:23:19 PM PST 24
Finished	Feb 07 01:42:41 PM PST 24
Peak memory	201588 kb
Host	smart-57495338-fec0-4229-b4fd-116ecc9d7ba8
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702241290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix ed.2702241290
Directory	/workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/23.adc_ctrl_lowpower_counter.682196449
Short name	T135
Test name
Test status
Simulation time	31030037254 ps
CPU time	18 seconds
Started	Feb 07 01:23:33 PM PST 24
Finished	Feb 07 01:23:52 PM PST 24
Peak memory	201396 kb
Host	smart-26da5bd0-1347-41e0-9fd2-d7299d05f11c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682196449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.682196449
Directory	/workspace/23.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/23.adc_ctrl_poweron_counter.2003953295
Short name	T754
Test name
Test status
Simulation time	4427647415 ps
CPU time	3.27 seconds
Started	Feb 07 01:23:38 PM PST 24
Finished	Feb 07 01:23:42 PM PST 24
Peak memory	200964 kb
Host	smart-78f4f0b0-4fbf-44e7-a023-40ce69f6b781
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003953295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2003953295
Directory	/workspace/23.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/23.adc_ctrl_smoke.172753689
Short name	T44
Test name
Test status
Simulation time	5522692595 ps
CPU time	13.47 seconds
Started	Feb 07 01:23:19 PM PST 24
Finished	Feb 07 01:23:33 PM PST 24
Peak memory	201352 kb
Host	smart-ca101fc8-e5fe-45c0-b476-01b243634a51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172753689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.172753689
Directory	/workspace/23.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1920049409
Short name	T78
Test name
Test status
Simulation time	178354856533 ps
CPU time	514.25 seconds
Started	Feb 07 01:23:31 PM PST 24
Finished	Feb 07 01:32:06 PM PST 24
Peak memory	210276 kb
Host	smart-d424f1e2-49c7-4a21-9d8b-fbf353660ddd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920049409 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1920049409
Directory	/workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.adc_ctrl_alert_test.438829800
Short name	T655
Test name
Test status
Simulation time	346109166 ps
CPU time	0.97 seconds
Started	Feb 07 01:25:33 PM PST 24
Finished	Feb 07 01:25:35 PM PST 24
Peak memory	201248 kb
Host	smart-3e67b2a4-6737-48e8-b832-3e7b61f98df9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438829800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.438829800
Directory	/workspace/24.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_both.727679733
Short name	T667
Test name
Test status
Simulation time	325552030191 ps
CPU time	186.42 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:28:41 PM PST 24
Peak memory	201608 kb
Host	smart-eb96cb86-db3f-4144-bba2-7c2b6894998b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727679733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.727679733
Directory	/workspace/24.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_interrupt.1663338234
Short name	T120
Test name
Test status
Simulation time	165283117505 ps
CPU time	98.6 seconds
Started	Feb 07 01:23:38 PM PST 24
Finished	Feb 07 01:25:18 PM PST 24
Peak memory	201212 kb
Host	smart-5071d4d8-7da0-40f1-a736-a732c67a27dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663338234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1663338234
Directory	/workspace/24.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2856706142
Short name	T505
Test name
Test status
Simulation time	326436737666 ps
CPU time	207.85 seconds
Started	Feb 07 01:25:35 PM PST 24
Finished	Feb 07 01:29:04 PM PST 24
Peak memory	201596 kb
Host	smart-ba343337-bb82-408f-83ec-a372a16a28ae
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856706142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru pt_fixed.2856706142
Directory	/workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_polled.1384881268
Short name	T463
Test name
Test status
Simulation time	158263827437 ps
CPU time	28.25 seconds
Started	Feb 07 01:23:29 PM PST 24
Finished	Feb 07 01:23:58 PM PST 24
Peak memory	201592 kb
Host	smart-b4a7684c-6fe5-4405-8799-2fe4cde3f7f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384881268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1384881268
Directory	/workspace/24.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1956098340
Short name	T556
Test name
Test status
Simulation time	161312955875 ps
CPU time	135.04 seconds
Started	Feb 07 01:23:39 PM PST 24
Finished	Feb 07 01:25:54 PM PST 24
Peak memory	201204 kb
Host	smart-e16f7d29-8975-4c52-9e44-6635c1da4632
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956098340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix ed.1956098340
Directory	/workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_wakeup.1344508300
Short name	T720
Test name
Test status
Simulation time	343060722067 ps
CPU time	410.14 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:32:25 PM PST 24
Peak memory	201528 kb
Host	smart-e9fa30d8-14ad-4f28-9cdd-1174a77c9d79
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344508300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters _wakeup.1344508300
Directory	/workspace/24.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3888625955
Short name	T576
Test name
Test status
Simulation time	165391061050 ps
CPU time	368.23 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:31:44 PM PST 24
Peak memory	201688 kb
Host	smart-52e15bbf-a574-48eb-9c44-78d82f30b022
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888625955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .adc_ctrl_filters_wakeup_fixed.3888625955
Directory	/workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_fsm_reset.461324069
Short name	T184
Test name
Test status
Simulation time	118851527458 ps
CPU time	623.21 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:35:58 PM PST 24
Peak memory	201920 kb
Host	smart-8c2347c2-6287-4128-a923-6d62c6caa4b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461324069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.461324069
Directory	/workspace/24.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/24.adc_ctrl_lowpower_counter.3280601983
Short name	T423
Test name
Test status
Simulation time	30842053855 ps
CPU time	19.09 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:25:54 PM PST 24
Peak memory	201392 kb
Host	smart-93e4f14d-9a24-45a3-a73c-796e7f9b9e2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280601983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3280601983
Directory	/workspace/24.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/24.adc_ctrl_poweron_counter.1349807732
Short name	T414
Test name
Test status
Simulation time	3114751390 ps
CPU time	5.88 seconds
Started	Feb 07 01:25:38 PM PST 24
Finished	Feb 07 01:25:46 PM PST 24
Peak memory	201424 kb
Host	smart-22aa4d8e-90af-4d39-9b9e-88a552fe557b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349807732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1349807732
Directory	/workspace/24.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/24.adc_ctrl_smoke.1284407020
Short name	T472
Test name
Test status
Simulation time	6102451676 ps
CPU time	6.27 seconds
Started	Feb 07 01:23:31 PM PST 24
Finished	Feb 07 01:23:38 PM PST 24
Peak memory	201392 kb
Host	smart-0ca25fce-9b2f-4eb7-a528-532a909fda0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284407020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1284407020
Directory	/workspace/24.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.adc_ctrl_stress_all.3991555931
Short name	T488
Test name
Test status
Simulation time	360758819152 ps
CPU time	829.26 seconds
Started	Feb 07 01:25:32 PM PST 24
Finished	Feb 07 01:39:22 PM PST 24
Peak memory	201676 kb
Host	smart-0a65f0b8-3349-4e99-9435-a8b908eb20e5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991555931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all .3991555931
Directory	/workspace/24.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3129082977
Short name	T704
Test name
Test status
Simulation time	5789433162 ps
CPU time	17.29 seconds
Started	Feb 07 01:25:38 PM PST 24
Finished	Feb 07 01:25:57 PM PST 24
Peak memory	218156 kb
Host	smart-155ed586-4d4d-4fc7-a1f6-47ac983564c4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129082977 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3129082977
Directory	/workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.adc_ctrl_alert_test.2918141859
Short name	T658
Test name
Test status
Simulation time	419133726 ps
CPU time	0.86 seconds
Started	Feb 07 01:25:54 PM PST 24
Finished	Feb 07 01:25:56 PM PST 24
Peak memory	201132 kb
Host	smart-d034598f-e52f-4b9d-b753-095855b44b59
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918141859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2918141859
Directory	/workspace/25.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.adc_ctrl_clock_gating.2728129900
Short name	T846
Test name
Test status
Simulation time	162407471389 ps
CPU time	183.37 seconds
Started	Feb 07 01:25:52 PM PST 24
Finished	Feb 07 01:28:57 PM PST 24
Peak memory	201612 kb
Host	smart-8bc7595e-1989-4eb2-96c5-27f7e50fb11b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728129900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat ing.2728129900
Directory	/workspace/25.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_interrupt.3736579076
Short name	T21
Test name
Test status
Simulation time	166873446210 ps
CPU time	386.91 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:32:01 PM PST 24
Peak memory	201560 kb
Host	smart-61dcafaf-269f-4bf5-8ab8-0ae0a7b39147
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736579076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3736579076
Directory	/workspace/25.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.436768019
Short name	T493
Test name
Test status
Simulation time	163471117771 ps
CPU time	192.07 seconds
Started	Feb 07 01:25:33 PM PST 24
Finished	Feb 07 01:28:45 PM PST 24
Peak memory	201592 kb
Host	smart-8d98df42-3013-4cd5-91d0-8af064f3c57b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=436768019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup t_fixed.436768019
Directory	/workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4259859868
Short name	T636
Test name
Test status
Simulation time	168993161326 ps
CPU time	397.35 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:32:13 PM PST 24
Peak memory	201556 kb
Host	smart-31f4e048-f05e-4881-ab2f-ad742e3f9b63
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259859868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix ed.4259859868
Directory	/workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_wakeup.3301446704
Short name	T549
Test name
Test status
Simulation time	168069111673 ps
CPU time	396.84 seconds
Started	Feb 07 01:25:34 PM PST 24
Finished	Feb 07 01:32:12 PM PST 24
Peak memory	201520 kb
Host	smart-851c7467-4d2f-46a3-9598-33c8f175c38a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301446704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters _wakeup.3301446704
Directory	/workspace/25.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.559484594
Short name	T575
Test name
Test status
Simulation time	329882810194 ps
CPU time	167.49 seconds
Started	Feb 07 01:25:37 PM PST 24
Finished	Feb 07 01:28:26 PM PST 24
Peak memory	201580 kb
Host	smart-4c8884d4-155b-46f7-ab4c-39d36c5d7ccc
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559484594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. adc_ctrl_filters_wakeup_fixed.559484594
Directory	/workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_fsm_reset.281625990
Short name	T733
Test name
Test status
Simulation time	139964173119 ps
CPU time	463.98 seconds
Started	Feb 07 01:25:52 PM PST 24
Finished	Feb 07 01:33:38 PM PST 24
Peak memory	201900 kb
Host	smart-ec710ab9-988f-4fb5-b15e-b4cc75b9c689
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281625990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.281625990
Directory	/workspace/25.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/25.adc_ctrl_lowpower_counter.755936733
Short name	T767
Test name
Test status
Simulation time	41119563244 ps
CPU time	90.02 seconds
Started	Feb 07 01:25:54 PM PST 24
Finished	Feb 07 01:27:26 PM PST 24
Peak memory	201452 kb
Host	smart-5b77b8c6-78ee-4827-b7c1-fda8d0e21991
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755936733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.755936733
Directory	/workspace/25.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/25.adc_ctrl_poweron_counter.1878447154
Short name	T670
Test name
Test status
Simulation time	4255514621 ps
CPU time	3.01 seconds
Started	Feb 07 01:25:48 PM PST 24
Finished	Feb 07 01:25:53 PM PST 24
Peak memory	201360 kb
Host	smart-d1c5551a-82db-4973-9314-4d66d8a6611e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878447154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1878447154
Directory	/workspace/25.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/25.adc_ctrl_smoke.2436212576
Short name	T476
Test name
Test status
Simulation time	5768119193 ps
CPU time	4.55 seconds
Started	Feb 07 01:25:33 PM PST 24
Finished	Feb 07 01:25:39 PM PST 24
Peak memory	201388 kb
Host	smart-6e543b3b-c905-498f-bf34-ddbb686b17f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436212576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2436212576
Directory	/workspace/25.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.444170813
Short name	T30
Test name
Test status
Simulation time	331704833469 ps
CPU time	199.61 seconds
Started	Feb 07 01:25:53 PM PST 24
Finished	Feb 07 01:29:14 PM PST 24
Peak memory	210276 kb
Host	smart-d5ded3e1-d753-474e-9238-35db91d3951b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444170813 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.444170813
Directory	/workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.adc_ctrl_alert_test.3336788906
Short name	T721
Test name
Test status
Simulation time	416821528 ps
CPU time	1.62 seconds
Started	Feb 07 01:26:02 PM PST 24
Finished	Feb 07 01:26:05 PM PST 24
Peak memory	201208 kb
Host	smart-bd850c5f-9f7b-480b-be5e-95676c681634
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336788906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3336788906
Directory	/workspace/26.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.adc_ctrl_clock_gating.2773865857
Short name	T253
Test name
Test status
Simulation time	495277588839 ps
CPU time	584.47 seconds
Started	Feb 07 01:25:51 PM PST 24
Finished	Feb 07 01:35:38 PM PST 24
Peak memory	201504 kb
Host	smart-2a3d8a60-3fcc-47dc-92c2-3372284bdbc5
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773865857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat ing.2773865857
Directory	/workspace/26.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_both.2088581988
Short name	T86
Test name
Test status
Simulation time	335042944957 ps
CPU time	197.06 seconds
Started	Feb 07 01:25:51 PM PST 24
Finished	Feb 07 01:29:11 PM PST 24
Peak memory	201564 kb
Host	smart-3d4cf378-7f72-48ba-bef3-ce3e553a2afb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088581988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2088581988
Directory	/workspace/26.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_interrupt.2148305446
Short name	T842
Test name
Test status
Simulation time	163715923100 ps
CPU time	159.38 seconds
Started	Feb 07 01:25:57 PM PST 24
Finished	Feb 07 01:28:37 PM PST 24
Peak memory	201652 kb
Host	smart-e52c765d-b810-451c-a252-152e29d5af77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148305446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2148305446
Directory	/workspace/26.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2643424763
Short name	T489
Test name
Test status
Simulation time	334239947818 ps
CPU time	178.51 seconds
Started	Feb 07 01:25:56 PM PST 24
Finished	Feb 07 01:28:56 PM PST 24
Peak memory	201608 kb
Host	smart-d4eea8bc-a70d-43e9-98d5-d0a86487bb83
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643424763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru pt_fixed.2643424763
Directory	/workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_polled.1221997848
Short name	T838
Test name
Test status
Simulation time	332507823045 ps
CPU time	384.9 seconds
Started	Feb 07 01:25:47 PM PST 24
Finished	Feb 07 01:32:14 PM PST 24
Peak memory	201644 kb
Host	smart-a6038527-557a-40e7-bbd7-c0b77379b107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221997848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1221997848
Directory	/workspace/26.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.45272967
Short name	T407
Test name
Test status
Simulation time	489583309905 ps
CPU time	1091.11 seconds
Started	Feb 07 01:25:52 PM PST 24
Finished	Feb 07 01:44:05 PM PST 24
Peak memory	201612 kb
Host	smart-3b30667e-dce4-4482-ab17-121438ddd144
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=45272967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed .45272967
Directory	/workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_wakeup.311691157
Short name	T719
Test name
Test status
Simulation time	499917380496 ps
CPU time	295.1 seconds
Started	Feb 07 01:25:57 PM PST 24
Finished	Feb 07 01:30:53 PM PST 24
Peak memory	201588 kb
Host	smart-8208dcc9-472c-4b56-8a19-d854ccda3cda
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311691157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_ wakeup.311691157
Directory	/workspace/26.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.866474973
Short name	T811
Test name
Test status
Simulation time	160743282017 ps
CPU time	338.15 seconds
Started	Feb 07 01:25:55 PM PST 24
Finished	Feb 07 01:31:35 PM PST 24
Peak memory	201628 kb
Host	smart-6a0bf2c8-3161-4263-97f2-33b250980419
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866474973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. adc_ctrl_filters_wakeup_fixed.866474973
Directory	/workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_fsm_reset.3908660546
Short name	T743
Test name
Test status
Simulation time	82323141142 ps
CPU time	338.18 seconds
Started	Feb 07 01:26:12 PM PST 24
Finished	Feb 07 01:31:52 PM PST 24
Peak memory	201852 kb
Host	smart-f3449939-0d01-487d-80c3-76fb9caf2512
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908660546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3908660546
Directory	/workspace/26.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/26.adc_ctrl_lowpower_counter.2969020442
Short name	T417
Test name
Test status
Simulation time	22388042462 ps
CPU time	6.72 seconds
Started	Feb 07 01:25:54 PM PST 24
Finished	Feb 07 01:26:02 PM PST 24
Peak memory	201356 kb
Host	smart-ba6aac96-390c-4777-9fd0-1d3da5639dd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969020442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2969020442
Directory	/workspace/26.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/26.adc_ctrl_poweron_counter.955807732
Short name	T819
Test name
Test status
Simulation time	3027857542 ps
CPU time	8.38 seconds
Started	Feb 07 01:25:53 PM PST 24
Finished	Feb 07 01:26:03 PM PST 24
Peak memory	201368 kb
Host	smart-4664a141-1407-4607-8510-e40e22b7ade5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955807732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.955807732
Directory	/workspace/26.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/26.adc_ctrl_smoke.2433884242
Short name	T458
Test name
Test status
Simulation time	5860792044 ps
CPU time	15.51 seconds
Started	Feb 07 01:25:52 PM PST 24
Finished	Feb 07 01:26:09 PM PST 24
Peak memory	201304 kb
Host	smart-9ef1012d-09ef-4cd6-9e7a-f9865e8a57f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433884242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2433884242
Directory	/workspace/26.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.adc_ctrl_stress_all.1329763614
Short name	T33
Test name
Test status
Simulation time	355607895785 ps
CPU time	1368.88 seconds
Started	Feb 07 01:26:07 PM PST 24
Finished	Feb 07 01:48:58 PM PST 24
Peak memory	201896 kb
Host	smart-fb284085-0170-443f-adb2-b6ab32f4924e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329763614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all .1329763614
Directory	/workspace/26.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4200593812
Short name	T737
Test name
Test status
Simulation time	93771520704 ps
CPU time	182 seconds
Started	Feb 07 01:26:13 PM PST 24
Finished	Feb 07 01:29:16 PM PST 24
Peak memory	210236 kb
Host	smart-e2e9316f-0d90-48d0-9707-0eab4cd54108
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200593812 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4200593812
Directory	/workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.adc_ctrl_alert_test.3554212365
Short name	T513
Test name
Test status
Simulation time	469893201 ps
CPU time	1.73 seconds
Started	Feb 07 01:26:07 PM PST 24
Finished	Feb 07 01:26:10 PM PST 24
Peak memory	201256 kb
Host	smart-248575a8-feab-40cf-8510-1b0f1039ed66
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554212365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3554212365
Directory	/workspace/27.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.adc_ctrl_clock_gating.560504557
Short name	T770
Test name
Test status
Simulation time	511004550725 ps
CPU time	102.64 seconds
Started	Feb 07 01:26:06 PM PST 24
Finished	Feb 07 01:27:51 PM PST 24
Peak memory	201556 kb
Host	smart-f5d6ec08-4e20-455c-bd29-eb3c528cace6
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560504557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati ng.560504557
Directory	/workspace/27.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_interrupt.1630549009
Short name	T294
Test name
Test status
Simulation time	331896164854 ps
CPU time	725.35 seconds
Started	Feb 07 01:26:12 PM PST 24
Finished	Feb 07 01:38:19 PM PST 24
Peak memory	201612 kb
Host	smart-557378ae-8929-4330-9427-095d745fac06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630549009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1630549009
Directory	/workspace/27.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3981196317
Short name	T809
Test name
Test status
Simulation time	492124316031 ps
CPU time	1209.17 seconds
Started	Feb 07 01:26:10 PM PST 24
Finished	Feb 07 01:46:23 PM PST 24
Peak memory	201600 kb
Host	smart-3c49fabf-bc47-4875-9cf8-30db77e0b5e3
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981196317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru pt_fixed.3981196317
Directory	/workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2973236954
Short name	T618
Test name
Test status
Simulation time	333781231928 ps
CPU time	192.85 seconds
Started	Feb 07 01:26:12 PM PST 24
Finished	Feb 07 01:29:27 PM PST 24
Peak memory	201516 kb
Host	smart-1dbefec9-83ff-4e67-a59b-712848bc836b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973236954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix ed.2973236954
Directory	/workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_wakeup.1074655896
Short name	T209
Test name
Test status
Simulation time	167110451495 ps
CPU time	83.7 seconds
Started	Feb 07 01:26:04 PM PST 24
Finished	Feb 07 01:27:29 PM PST 24
Peak memory	201576 kb
Host	smart-265ccc0d-0332-4ec7-800c-a5338f18c9ed
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074655896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters _wakeup.1074655896
Directory	/workspace/27.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1400350776
Short name	T741
Test name
Test status
Simulation time	316097953644 ps
CPU time	61.91 seconds
Started	Feb 07 01:26:04 PM PST 24
Finished	Feb 07 01:27:07 PM PST 24
Peak memory	201548 kb
Host	smart-081896bc-0529-4448-8d92-178ea7086e4e
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400350776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .adc_ctrl_filters_wakeup_fixed.1400350776
Directory	/workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_fsm_reset.3085578655
Short name	T177
Test name
Test status
Simulation time	102743076269 ps
CPU time	523.51 seconds
Started	Feb 07 01:26:10 PM PST 24
Finished	Feb 07 01:34:57 PM PST 24
Peak memory	201904 kb
Host	smart-82be8446-1249-4820-b2e4-b3edb095e00c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085578655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3085578655
Directory	/workspace/27.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/27.adc_ctrl_lowpower_counter.2372657880
Short name	T444
Test name
Test status
Simulation time	45823284175 ps
CPU time	28.09 seconds
Started	Feb 07 01:26:03 PM PST 24
Finished	Feb 07 01:26:32 PM PST 24
Peak memory	201364 kb
Host	smart-2caedcaf-2695-44f6-9350-57d105928458
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372657880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2372657880
Directory	/workspace/27.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/27.adc_ctrl_poweron_counter.1433087615
Short name	T555
Test name
Test status
Simulation time	3513293112 ps
CPU time	8.41 seconds
Started	Feb 07 01:26:04 PM PST 24
Finished	Feb 07 01:26:13 PM PST 24
Peak memory	201392 kb
Host	smart-72d291d7-fcd4-4952-a515-5de31b516808
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433087615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1433087615
Directory	/workspace/27.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/27.adc_ctrl_smoke.2318023763
Short name	T755
Test name
Test status
Simulation time	6046435296 ps
CPU time	3.9 seconds
Started	Feb 07 01:26:04 PM PST 24
Finished	Feb 07 01:26:09 PM PST 24
Peak memory	201352 kb
Host	smart-3fee3c7b-46c9-4bf6-be5d-e0e8f34c414c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318023763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2318023763
Directory	/workspace/27.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.adc_ctrl_stress_all.2569420282
Short name	T766
Test name
Test status
Simulation time	169583762034 ps
CPU time	103.55 seconds
Started	Feb 07 01:26:02 PM PST 24
Finished	Feb 07 01:27:47 PM PST 24
Peak memory	201692 kb
Host	smart-876dd153-f8b7-4fb6-ac14-2d0e8ba0e376
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569420282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all .2569420282
Directory	/workspace/27.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2763081706
Short name	T255
Test name
Test status
Simulation time	8043419653 ps
CPU time	18.41 seconds
Started	Feb 07 01:26:08 PM PST 24
Finished	Feb 07 01:26:31 PM PST 24
Peak memory	201788 kb
Host	smart-3cc2dddd-4e87-4583-bf22-bf26436937f7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763081706 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2763081706
Directory	/workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.adc_ctrl_alert_test.4209057551
Short name	T779
Test name
Test status
Simulation time	292598510 ps
CPU time	1.24 seconds
Started	Feb 07 01:26:15 PM PST 24
Finished	Feb 07 01:26:18 PM PST 24
Peak memory	201276 kb
Host	smart-afaa8049-e063-443a-8985-0247aed0ccd6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209057551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.4209057551
Directory	/workspace/28.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_both.3720749589
Short name	T561
Test name
Test status
Simulation time	489069481718 ps
CPU time	286.1 seconds
Started	Feb 07 01:26:03 PM PST 24
Finished	Feb 07 01:30:50 PM PST 24
Peak memory	201532 kb
Host	smart-2b1e9e2c-0d91-4780-9e8b-82fd5cd57b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720749589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3720749589
Directory	/workspace/28.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_interrupt.130718261
Short name	T190
Test name
Test status
Simulation time	162128716093 ps
CPU time	91.62 seconds
Started	Feb 07 01:26:04 PM PST 24
Finished	Feb 07 01:27:36 PM PST 24
Peak memory	201624 kb
Host	smart-b6097dcb-9ce9-4661-a575-cb1d150b98e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130718261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.130718261
Directory	/workspace/28.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1115082197
Short name	T568
Test name
Test status
Simulation time	488194654160 ps
CPU time	1115.58 seconds
Started	Feb 07 01:26:09 PM PST 24
Finished	Feb 07 01:44:49 PM PST 24
Peak memory	201648 kb
Host	smart-bc748799-0fb4-4bff-a22e-21770480afde
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115082197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru pt_fixed.1115082197
Directory	/workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_polled.2995623766
Short name	T560
Test name
Test status
Simulation time	162537445358 ps
CPU time	373.57 seconds
Started	Feb 07 01:26:05 PM PST 24
Finished	Feb 07 01:32:20 PM PST 24
Peak memory	201500 kb
Host	smart-b766f8a7-aec8-4bfc-ac23-76f7e11cbed4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995623766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2995623766
Directory	/workspace/28.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.72428635
Short name	T826
Test name
Test status
Simulation time	165869944385 ps
CPU time	395.4 seconds
Started	Feb 07 01:26:08 PM PST 24
Finished	Feb 07 01:32:48 PM PST 24
Peak memory	201640 kb
Host	smart-3aef78f6-b6e4-46bc-bce7-d0abecd23a71
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=72428635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed .72428635
Directory	/workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3069077760
Short name	T462
Test name
Test status
Simulation time	499794269789 ps
CPU time	1088.52 seconds
Started	Feb 07 01:26:12 PM PST 24
Finished	Feb 07 01:44:22 PM PST 24
Peak memory	201632 kb
Host	smart-2fd36e48-49e0-4a9c-8beb-bc6fc36c4b87
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069077760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .adc_ctrl_filters_wakeup_fixed.3069077760
Directory	/workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_fsm_reset.2700133299
Short name	T677
Test name
Test status
Simulation time	87190504011 ps
CPU time	351.11 seconds
Started	Feb 07 01:26:14 PM PST 24
Finished	Feb 07 01:32:08 PM PST 24
Peak memory	201936 kb
Host	smart-71e1fe99-a0d0-4249-82b0-18f7f629c2aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700133299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2700133299
Directory	/workspace/28.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/28.adc_ctrl_lowpower_counter.3945818707
Short name	T587
Test name
Test status
Simulation time	27938976105 ps
CPU time	71.08 seconds
Started	Feb 07 01:26:02 PM PST 24
Finished	Feb 07 01:27:15 PM PST 24
Peak memory	201396 kb
Host	smart-d090e007-14b2-4279-896f-aac2d37364d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945818707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3945818707
Directory	/workspace/28.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/28.adc_ctrl_poweron_counter.986936041
Short name	T529
Test name
Test status
Simulation time	3564369828 ps
CPU time	2.79 seconds
Started	Feb 07 01:26:09 PM PST 24
Finished	Feb 07 01:26:16 PM PST 24
Peak memory	201304 kb
Host	smart-217e1efd-45cf-469c-9e12-93bcb471f401
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986936041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.986936041
Directory	/workspace/28.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/28.adc_ctrl_smoke.789142612
Short name	T425
Test name
Test status
Simulation time	5820629357 ps
CPU time	13.59 seconds
Started	Feb 07 01:26:07 PM PST 24
Finished	Feb 07 01:26:22 PM PST 24
Peak memory	201348 kb
Host	smart-b34d5e97-1a42-4ea1-8160-87cfcbaebcee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789142612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.789142612
Directory	/workspace/28.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4175179533
Short name	T700
Test name
Test status
Simulation time	90106023103 ps
CPU time	55.72 seconds
Started	Feb 07 01:26:17 PM PST 24
Finished	Feb 07 01:27:13 PM PST 24
Peak memory	210260 kb
Host	smart-5495c804-8794-45a9-a54b-918a40f686e5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175179533 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4175179533
Directory	/workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.adc_ctrl_alert_test.3068882587
Short name	T416
Test name
Test status
Simulation time	481173345 ps
CPU time	1.62 seconds
Started	Feb 07 01:26:29 PM PST 24
Finished	Feb 07 01:26:31 PM PST 24
Peak memory	201236 kb
Host	smart-d0cbfc77-a2d9-468a-b940-ee2f29f0dbdd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068882587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3068882587
Directory	/workspace/29.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_both.1919163627
Short name	T250
Test name
Test status
Simulation time	494880969633 ps
CPU time	575.26 seconds
Started	Feb 07 01:26:19 PM PST 24
Finished	Feb 07 01:35:55 PM PST 24
Peak memory	201584 kb
Host	smart-51d4a021-be1b-40c3-bf2c-9098158af5fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919163627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1919163627
Directory	/workspace/29.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_interrupt.1141648600
Short name	T264
Test name
Test status
Simulation time	328985064582 ps
CPU time	418.2 seconds
Started	Feb 07 01:26:19 PM PST 24
Finished	Feb 07 01:33:18 PM PST 24
Peak memory	201524 kb
Host	smart-7796637a-4f2e-4323-bb1e-71fde1fd9790
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141648600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1141648600
Directory	/workspace/29.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1165152156
Short name	T133
Test name
Test status
Simulation time	332826186161 ps
CPU time	433.88 seconds
Started	Feb 07 01:26:14 PM PST 24
Finished	Feb 07 01:33:29 PM PST 24
Peak memory	201540 kb
Host	smart-c5cac6a5-f02c-483f-a6bb-e7d5790632e0
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165152156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru pt_fixed.1165152156
Directory	/workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_polled.1034677600
Short name	T504
Test name
Test status
Simulation time	162747840477 ps
CPU time	390.33 seconds
Started	Feb 07 01:26:15 PM PST 24
Finished	Feb 07 01:32:47 PM PST 24
Peak memory	201580 kb
Host	smart-f1ae449b-2793-4ccb-ab14-8df3bacfab3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034677600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1034677600
Directory	/workspace/29.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.380056271
Short name	T660
Test name
Test status
Simulation time	498243359766 ps
CPU time	303.07 seconds
Started	Feb 07 01:26:13 PM PST 24
Finished	Feb 07 01:31:18 PM PST 24
Peak memory	201528 kb
Host	smart-693debc6-852f-4354-a1d4-e258ad5ffc3f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=380056271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe d.380056271
Directory	/workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_wakeup.3772790953
Short name	T122
Test name
Test status
Simulation time	330739424390 ps
CPU time	186.19 seconds
Started	Feb 07 01:26:19 PM PST 24
Finished	Feb 07 01:29:26 PM PST 24
Peak memory	201604 kb
Host	smart-345ed0e4-317a-4083-9c57-5006d2991ad8
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772790953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters _wakeup.3772790953
Directory	/workspace/29.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.141644776
Short name	T693
Test name
Test status
Simulation time	496939752174 ps
CPU time	152.84 seconds
Started	Feb 07 01:26:14 PM PST 24
Finished	Feb 07 01:28:48 PM PST 24
Peak memory	201564 kb
Host	smart-12d751f7-bb47-4709-8a05-f7685e98e487
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141644776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. adc_ctrl_filters_wakeup_fixed.141644776
Directory	/workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_fsm_reset.3445118967
Short name	T852
Test name
Test status
Simulation time	113824434831 ps
CPU time	385.19 seconds
Started	Feb 07 01:26:29 PM PST 24
Finished	Feb 07 01:32:55 PM PST 24
Peak memory	201908 kb
Host	smart-37804f7a-06ec-4c8a-a93a-bed1f774f18d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445118967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3445118967
Directory	/workspace/29.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/29.adc_ctrl_lowpower_counter.3139945362
Short name	T528
Test name
Test status
Simulation time	22689862334 ps
CPU time	24.44 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:26:52 PM PST 24
Peak memory	201356 kb
Host	smart-f1dc4372-3dac-4e08-8507-a388b24af27d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139945362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3139945362
Directory	/workspace/29.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/29.adc_ctrl_poweron_counter.704534561
Short name	T535
Test name
Test status
Simulation time	4490882989 ps
CPU time	9.15 seconds
Started	Feb 07 01:26:19 PM PST 24
Finished	Feb 07 01:26:29 PM PST 24
Peak memory	201308 kb
Host	smart-cd2783f9-89de-497b-8f31-d22685f7dbc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=704534561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.704534561
Directory	/workspace/29.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/29.adc_ctrl_smoke.759241575
Short name	T439
Test name
Test status
Simulation time	6024317409 ps
CPU time	14.99 seconds
Started	Feb 07 01:26:19 PM PST 24
Finished	Feb 07 01:26:35 PM PST 24
Peak memory	201396 kb
Host	smart-804e664f-9628-400a-9d4d-dfdc04d2ffb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759241575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.759241575
Directory	/workspace/29.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.adc_ctrl_stress_all.2068208698
Short name	T821
Test name
Test status
Simulation time	237453146609 ps
CPU time	136.08 seconds
Started	Feb 07 01:26:29 PM PST 24
Finished	Feb 07 01:28:45 PM PST 24
Peak memory	201580 kb
Host	smart-6330a5a1-c33e-466c-adec-175bfddd3b4b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068208698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all .2068208698
Directory	/workspace/29.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3102014262
Short name	T642
Test name
Test status
Simulation time	200615200627 ps
CPU time	68.36 seconds
Started	Feb 07 01:26:26 PM PST 24
Finished	Feb 07 01:27:35 PM PST 24
Peak memory	209948 kb
Host	smart-c51a5e74-ec89-4689-be94-7c4bb9923428
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102014262 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3102014262
Directory	/workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.adc_ctrl_alert_test.2513765133
Short name	T706
Test name
Test status
Simulation time	462574683 ps
CPU time	1.09 seconds
Started	Feb 07 01:19:16 PM PST 24
Finished	Feb 07 01:19:18 PM PST 24
Peak memory	201160 kb
Host	smart-1c5d5fd0-6067-4c56-b47e-31ba74e98cfa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513765133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2513765133
Directory	/workspace/3.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.adc_ctrl_clock_gating.1277070711
Short name	T252
Test name
Test status
Simulation time	322811342127 ps
CPU time	199.8 seconds
Started	Feb 07 01:19:06 PM PST 24
Finished	Feb 07 01:22:26 PM PST 24
Peak memory	201496 kb
Host	smart-e147b1a9-f7bd-4b9c-998c-83ecb2d7832b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277070711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati ng.1277070711
Directory	/workspace/3.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_both.537065427
Short name	T263
Test name
Test status
Simulation time	500484440889 ps
CPU time	1136.57 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:38:13 PM PST 24
Peak memory	201696 kb
Host	smart-2b80234d-f38a-4c99-a1e5-4b220a439c03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537065427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.537065427
Directory	/workspace/3.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2737566939
Short name	T637
Test name
Test status
Simulation time	165661157422 ps
CPU time	399.81 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:25:56 PM PST 24
Peak memory	201592 kb
Host	smart-a8b4db2c-e432-4791-b9f5-0c5013a6048a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737566939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup t_fixed.2737566939
Directory	/workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_polled.964840994
Short name	T581
Test name
Test status
Simulation time	329262118734 ps
CPU time	699.03 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:30:53 PM PST 24
Peak memory	201460 kb
Host	smart-cca17dde-7a5e-4aa0-a561-a9f4c1b83a09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964840994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.964840994
Directory	/workspace/3.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3010530475
Short name	T606
Test name
Test status
Simulation time	493987874238 ps
CPU time	280.56 seconds
Started	Feb 07 01:19:06 PM PST 24
Finished	Feb 07 01:23:47 PM PST 24
Peak memory	201508 kb
Host	smart-d3ab81f6-9720-4e16-ab18-0e0688dbf6fe
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010530475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe d.3010530475
Directory	/workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_wakeup.1325949633
Short name	T848
Test name
Test status
Simulation time	326326912029 ps
CPU time	748.23 seconds
Started	Feb 07 01:19:05 PM PST 24
Finished	Feb 07 01:31:34 PM PST 24
Peak memory	201516 kb
Host	smart-9d49a1a0-a92a-45e4-bd84-0febee4ad24a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325949633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_ wakeup.1325949633
Directory	/workspace/3.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1198333213
Short name	T814
Test name
Test status
Simulation time	495961450688 ps
CPU time	1182.59 seconds
Started	Feb 07 01:19:04 PM PST 24
Finished	Feb 07 01:38:47 PM PST 24
Peak memory	201636 kb
Host	smart-bc263890-b90c-452c-8318-f5151ce73531
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198333213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. adc_ctrl_filters_wakeup_fixed.1198333213
Directory	/workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_fsm_reset.1611566265
Short name	T774
Test name
Test status
Simulation time	128073084056 ps
CPU time	673.36 seconds
Started	Feb 07 01:19:09 PM PST 24
Finished	Feb 07 01:30:23 PM PST 24
Peak memory	201912 kb
Host	smart-1f460b28-f19b-424c-9ecb-97fb058f498d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611566265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1611566265
Directory	/workspace/3.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/3.adc_ctrl_lowpower_counter.2489292883
Short name	T649
Test name
Test status
Simulation time	33687570546 ps
CPU time	38.2 seconds
Started	Feb 07 01:19:09 PM PST 24
Finished	Feb 07 01:19:48 PM PST 24
Peak memory	201436 kb
Host	smart-16b1c4e0-df16-4957-bbeb-1fff8892dc97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489292883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2489292883
Directory	/workspace/3.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/3.adc_ctrl_poweron_counter.1003270895
Short name	T509
Test name
Test status
Simulation time	3993106509 ps
CPU time	10.71 seconds
Started	Feb 07 01:19:11 PM PST 24
Finished	Feb 07 01:19:23 PM PST 24
Peak memory	201452 kb
Host	smart-ca3ee08b-83d5-4a7d-aa43-9ac04e340a35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003270895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1003270895
Directory	/workspace/3.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/3.adc_ctrl_sec_cm.1345794667
Short name	T42
Test name
Test status
Simulation time	4246978484 ps
CPU time	9.69 seconds
Started	Feb 07 01:19:14 PM PST 24
Finished	Feb 07 01:19:25 PM PST 24
Peak memory	216744 kb
Host	smart-d32b4127-afa8-4e89-a669-dc77817a6737
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345794667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1345794667
Directory	/workspace/3.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.adc_ctrl_smoke.2067328373
Short name	T757
Test name
Test status
Simulation time	5951155317 ps
CPU time	14.68 seconds
Started	Feb 07 01:19:15 PM PST 24
Finished	Feb 07 01:19:30 PM PST 24
Peak memory	201188 kb
Host	smart-adefa430-3ed1-428b-9379-c852a63227d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067328373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2067328373
Directory	/workspace/3.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3286250094
Short name	T88
Test name
Test status
Simulation time	125404056426 ps
CPU time	184.1 seconds
Started	Feb 07 01:19:07 PM PST 24
Finished	Feb 07 01:22:12 PM PST 24
Peak memory	218468 kb
Host	smart-d84edfb9-5306-4e77-adf4-0b336d9e95c8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286250094 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3286250094
Directory	/workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.adc_ctrl_alert_test.268228635
Short name	T501
Test name
Test status
Simulation time	390363625 ps
CPU time	1.49 seconds
Started	Feb 07 01:26:26 PM PST 24
Finished	Feb 07 01:26:29 PM PST 24
Peak memory	201252 kb
Host	smart-5b49b85f-05b7-482f-afd6-663f3e6d1521
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268228635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.268228635
Directory	/workspace/30.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.adc_ctrl_clock_gating.2186693226
Short name	T280
Test name
Test status
Simulation time	317763085231 ps
CPU time	349.09 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:32:17 PM PST 24
Peak memory	201700 kb
Host	smart-a74721d8-fcce-4868-9b97-d97ca875e9b0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186693226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat ing.2186693226
Directory	/workspace/30.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_both.2457039583
Short name	T295
Test name
Test status
Simulation time	167062979083 ps
CPU time	98.84 seconds
Started	Feb 07 01:26:26 PM PST 24
Finished	Feb 07 01:28:05 PM PST 24
Peak memory	201692 kb
Host	smart-6d4f3b35-ba5f-46d9-be80-936a2e6b9733
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2457039583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2457039583
Directory	/workspace/30.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_interrupt.2993061918
Short name	T304
Test name
Test status
Simulation time	335028085544 ps
CPU time	89.04 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:27:57 PM PST 24
Peak memory	201632 kb
Host	smart-02d1be7e-c9b0-4645-ad97-0afc7e05491c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993061918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2993061918
Directory	/workspace/30.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1303255538
Short name	T722
Test name
Test status
Simulation time	488063380637 ps
CPU time	220.27 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:30:08 PM PST 24
Peak memory	201624 kb
Host	smart-b3e9d84b-7061-4441-ba19-f35a59aa3e59
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303255538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru pt_fixed.1303255538
Directory	/workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_polled.672454276
Short name	T110
Test name
Test status
Simulation time	326195553988 ps
CPU time	158.93 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:29:06 PM PST 24
Peak memory	201652 kb
Host	smart-30caa18d-2aa7-405e-8e54-978cc49fb026
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672454276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.672454276
Directory	/workspace/30.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1636344698
Short name	T134
Test name
Test status
Simulation time	160631081093 ps
CPU time	109.17 seconds
Started	Feb 07 01:26:26 PM PST 24
Finished	Feb 07 01:28:16 PM PST 24
Peak memory	201572 kb
Host	smart-3611ef97-6c71-45e8-ae79-5a02a88fbcf4
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636344698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix ed.1636344698
Directory	/workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_wakeup.3000055939
Short name	T13
Test name
Test status
Simulation time	163838279579 ps
CPU time	380.36 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:32:48 PM PST 24
Peak memory	201608 kb
Host	smart-dd4ed587-2f6a-434d-9e59-1850e2df092b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000055939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters _wakeup.3000055939
Directory	/workspace/30.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3417976971
Short name	T589
Test name
Test status
Simulation time	493521387728 ps
CPU time	1146.63 seconds
Started	Feb 07 01:26:26 PM PST 24
Finished	Feb 07 01:45:34 PM PST 24
Peak memory	201452 kb
Host	smart-f1701cd2-1a8b-4343-89bb-f5c509d21d66
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417976971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .adc_ctrl_filters_wakeup_fixed.3417976971
Directory	/workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_fsm_reset.2580857781
Short name	T665
Test name
Test status
Simulation time	85719017079 ps
CPU time	343.34 seconds
Started	Feb 07 01:26:30 PM PST 24
Finished	Feb 07 01:32:14 PM PST 24
Peak memory	201968 kb
Host	smart-9ec4f941-e231-465a-bd3a-d5a709bdf427
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580857781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2580857781
Directory	/workspace/30.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/30.adc_ctrl_lowpower_counter.2582414669
Short name	T49
Test name
Test status
Simulation time	20917121375 ps
CPU time	49.02 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:27:17 PM PST 24
Peak memory	201428 kb
Host	smart-1e707ff3-28cf-4bea-9fc9-6c265fef9c1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582414669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2582414669
Directory	/workspace/30.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/30.adc_ctrl_poweron_counter.246498029
Short name	T815
Test name
Test status
Simulation time	4824871612 ps
CPU time	8.39 seconds
Started	Feb 07 01:26:28 PM PST 24
Finished	Feb 07 01:26:37 PM PST 24
Peak memory	201400 kb
Host	smart-118588e8-63a8-48f7-af5c-8835ed36c053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246498029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.246498029
Directory	/workspace/30.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/30.adc_ctrl_smoke.608662231
Short name	T405
Test name
Test status
Simulation time	6135685375 ps
CPU time	15.49 seconds
Started	Feb 07 01:26:30 PM PST 24
Finished	Feb 07 01:26:46 PM PST 24
Peak memory	201420 kb
Host	smart-06ecdea1-8376-4f33-803b-4b24aaba4145
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608662231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.608662231
Directory	/workspace/30.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.adc_ctrl_stress_all.3950159976
Short name	T859
Test name
Test status
Simulation time	690866619935 ps
CPU time	1512.76 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:51:40 PM PST 24
Peak memory	201592 kb
Host	smart-d871c294-96ea-4d85-aa44-e5965c7692a1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950159976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all .3950159976
Directory	/workspace/30.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3014148790
Short name	T117
Test name
Test status
Simulation time	85073065405 ps
CPU time	71.46 seconds
Started	Feb 07 01:26:25 PM PST 24
Finished	Feb 07 01:27:38 PM PST 24
Peak memory	209948 kb
Host	smart-dcdcb131-83af-4fe0-aba3-6720499cb976
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014148790 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3014148790
Directory	/workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.adc_ctrl_alert_test.2996991326
Short name	T584
Test name
Test status
Simulation time	521726120 ps
CPU time	1.9 seconds
Started	Feb 07 01:26:55 PM PST 24
Finished	Feb 07 01:26:58 PM PST 24
Peak memory	201264 kb
Host	smart-be213e7c-61a4-4537-bb0f-886954005ab9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996991326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2996991326
Directory	/workspace/31.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.adc_ctrl_clock_gating.2155960578
Short name	T850
Test name
Test status
Simulation time	165823876002 ps
CPU time	380.19 seconds
Started	Feb 07 01:26:54 PM PST 24
Finished	Feb 07 01:33:15 PM PST 24
Peak memory	201600 kb
Host	smart-c2e0801d-b100-4d2c-8e44-b98ba07838c4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155960578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat ing.2155960578
Directory	/workspace/31.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_both.1489102666
Short name	T750
Test name
Test status
Simulation time	496667478491 ps
CPU time	1187.87 seconds
Started	Feb 07 01:26:56 PM PST 24
Finished	Feb 07 01:46:44 PM PST 24
Peak memory	201592 kb
Host	smart-35017991-f3c0-4049-9432-735161daa44f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489102666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1489102666
Directory	/workspace/31.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_interrupt.1632028849
Short name	T274
Test name
Test status
Simulation time	166116374887 ps
CPU time	411.38 seconds
Started	Feb 07 01:26:58 PM PST 24
Finished	Feb 07 01:33:50 PM PST 24
Peak memory	201112 kb
Host	smart-0a45a7e6-769d-4f63-a3ad-85eb58f9873a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632028849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1632028849
Directory	/workspace/31.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3100767192
Short name	T483
Test name
Test status
Simulation time	480951890610 ps
CPU time	558.3 seconds
Started	Feb 07 01:26:53 PM PST 24
Finished	Feb 07 01:36:12 PM PST 24
Peak memory	201564 kb
Host	smart-56b8024c-a5f2-4e22-bf0c-cd25c0fab3a2
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100767192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru pt_fixed.3100767192
Directory	/workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_polled.2612398375
Short name	T204
Test name
Test status
Simulation time	329675567406 ps
CPU time	716.76 seconds
Started	Feb 07 01:26:33 PM PST 24
Finished	Feb 07 01:38:31 PM PST 24
Peak memory	201672 kb
Host	smart-75756c00-f9c1-4b99-bff7-ca8971856d17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612398375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2612398375
Directory	/workspace/31.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.176864618
Short name	T452
Test name
Test status
Simulation time	163225943459 ps
CPU time	347.71 seconds
Started	Feb 07 01:26:55 PM PST 24
Finished	Feb 07 01:32:44 PM PST 24
Peak memory	201588 kb
Host	smart-c3fbcce5-d9f1-4f47-ac10-839e2adde13e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=176864618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe d.176864618
Directory	/workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_wakeup.2157980195
Short name	T647
Test name
Test status
Simulation time	490019958205 ps
CPU time	302.15 seconds
Started	Feb 07 01:26:54 PM PST 24
Finished	Feb 07 01:31:56 PM PST 24
Peak memory	201604 kb
Host	smart-c546d283-1134-4157-bcb9-e038f83f862e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157980195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters _wakeup.2157980195
Directory	/workspace/31.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3270200394
Short name	T751
Test name
Test status
Simulation time	330056924806 ps
CPU time	810.68 seconds
Started	Feb 07 01:26:54 PM PST 24
Finished	Feb 07 01:40:25 PM PST 24
Peak memory	201624 kb
Host	smart-783ee0f2-d291-46e8-94f3-f928f2e616ca
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270200394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .adc_ctrl_filters_wakeup_fixed.3270200394
Directory	/workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_lowpower_counter.2822710768
Short name	T459
Test name
Test status
Simulation time	24514125794 ps
CPU time	54.91 seconds
Started	Feb 07 01:26:54 PM PST 24
Finished	Feb 07 01:27:50 PM PST 24
Peak memory	201392 kb
Host	smart-f5d2967e-c47c-4b76-b355-c30366748aaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822710768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2822710768
Directory	/workspace/31.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/31.adc_ctrl_poweron_counter.2156234993
Short name	T800
Test name
Test status
Simulation time	4358788486 ps
CPU time	1.52 seconds
Started	Feb 07 01:26:58 PM PST 24
Finished	Feb 07 01:27:00 PM PST 24
Peak memory	200896 kb
Host	smart-036be556-3a94-4c25-a5dc-dc6bc7fad159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156234993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2156234993
Directory	/workspace/31.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/31.adc_ctrl_smoke.1787112148
Short name	T545
Test name
Test status
Simulation time	5931746799 ps
CPU time	4.08 seconds
Started	Feb 07 01:26:27 PM PST 24
Finished	Feb 07 01:26:31 PM PST 24
Peak memory	201340 kb
Host	smart-f14a6765-1495-4eab-83dd-019ae14615f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787112148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1787112148
Directory	/workspace/31.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.adc_ctrl_stress_all.3463698990
Short name	T613
Test name
Test status
Simulation time	12159676164 ps
CPU time	7.28 seconds
Started	Feb 07 01:26:54 PM PST 24
Finished	Feb 07 01:27:02 PM PST 24
Peak memory	201372 kb
Host	smart-6fcd0703-9f22-4777-b412-2d4385bf4866
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463698990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all .3463698990
Directory	/workspace/31.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1397779711
Short name	T675
Test name
Test status
Simulation time	215555884441 ps
CPU time	362.51 seconds
Started	Feb 07 01:26:56 PM PST 24
Finished	Feb 07 01:32:59 PM PST 24
Peak memory	210344 kb
Host	smart-e4cd956b-dbd4-4f60-a64e-ee85fa7dca71
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397779711 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1397779711
Directory	/workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.adc_ctrl_alert_test.2981191513
Short name	T454
Test name
Test status
Simulation time	476275522 ps
CPU time	1.72 seconds
Started	Feb 07 01:26:59 PM PST 24
Finished	Feb 07 01:27:02 PM PST 24
Peak memory	201132 kb
Host	smart-df18da21-7128-4e45-967f-04ec174fa0f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981191513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2981191513
Directory	/workspace/32.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_both.2909908669
Short name	T224
Test name
Test status
Simulation time	164788977332 ps
CPU time	83.54 seconds
Started	Feb 07 01:26:56 PM PST 24
Finished	Feb 07 01:28:21 PM PST 24
Peak memory	201636 kb
Host	smart-ae3afb4f-613d-4923-84b4-53328860770c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909908669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2909908669
Directory	/workspace/32.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_interrupt.1564598089
Short name	T573
Test name
Test status
Simulation time	487180046786 ps
CPU time	1151.47 seconds
Started	Feb 07 01:26:56 PM PST 24
Finished	Feb 07 01:46:08 PM PST 24
Peak memory	201624 kb
Host	smart-80c5850a-567b-4ed9-b5dd-e2e81cc130f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564598089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1564598089
Directory	/workspace/32.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3747132121
Short name	T783
Test name
Test status
Simulation time	170463845632 ps
CPU time	410.59 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:33:49 PM PST 24
Peak memory	201616 kb
Host	smart-55408ddc-923a-449b-8a3c-d61d1160d4a6
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747132121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru pt_fixed.3747132121
Directory	/workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_polled.32195253
Short name	T108
Test name
Test status
Simulation time	491194289814 ps
CPU time	252.54 seconds
Started	Feb 07 01:26:54 PM PST 24
Finished	Feb 07 01:31:07 PM PST 24
Peak memory	201588 kb
Host	smart-5cc83ea7-b841-4bbb-abbc-3ecf4e631d02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32195253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.32195253
Directory	/workspace/32.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3001836265
Short name	T663
Test name
Test status
Simulation time	324268549009 ps
CPU time	124.72 seconds
Started	Feb 07 01:26:54 PM PST 24
Finished	Feb 07 01:29:00 PM PST 24
Peak memory	201560 kb
Host	smart-e7235938-c748-4546-a718-873c47de55c2
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001836265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix ed.3001836265
Directory	/workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_wakeup.4016611625
Short name	T276
Test name
Test status
Simulation time	516101689697 ps
CPU time	660.33 seconds
Started	Feb 07 01:26:56 PM PST 24
Finished	Feb 07 01:37:57 PM PST 24
Peak memory	201608 kb
Host	smart-2ff7ea30-52f3-4c00-a00a-62fc579c6190
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016611625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters _wakeup.4016611625
Directory	/workspace/32.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1706572231
Short name	T546
Test name
Test status
Simulation time	494959103324 ps
CPU time	547.07 seconds
Started	Feb 07 01:26:58 PM PST 24
Finished	Feb 07 01:36:06 PM PST 24
Peak memory	201628 kb
Host	smart-da493073-b3ce-44f5-8ece-3e3a19f5c2ef
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706572231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .adc_ctrl_filters_wakeup_fixed.1706572231
Directory	/workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_fsm_reset.997992261
Short name	T839
Test name
Test status
Simulation time	124577917224 ps
CPU time	431.12 seconds
Started	Feb 07 01:27:00 PM PST 24
Finished	Feb 07 01:34:11 PM PST 24
Peak memory	201756 kb
Host	smart-326e80c4-906b-4f4a-9c4e-4a70720aea0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997992261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.997992261
Directory	/workspace/32.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/32.adc_ctrl_lowpower_counter.2533575747
Short name	T866
Test name
Test status
Simulation time	27572929533 ps
CPU time	57.99 seconds
Started	Feb 07 01:26:59 PM PST 24
Finished	Feb 07 01:27:58 PM PST 24
Peak memory	201384 kb
Host	smart-d2605786-a601-455c-a987-57530c14cfb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533575747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2533575747
Directory	/workspace/32.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/32.adc_ctrl_poweron_counter.1676259742
Short name	T469
Test name
Test status
Simulation time	4691456827 ps
CPU time	3.45 seconds
Started	Feb 07 01:26:59 PM PST 24
Finished	Feb 07 01:27:03 PM PST 24
Peak memory	201392 kb
Host	smart-48ce5b4c-f06e-49c4-8562-b3160f1ef1b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676259742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1676259742
Directory	/workspace/32.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/32.adc_ctrl_smoke.4049520633
Short name	T544
Test name
Test status
Simulation time	5857529445 ps
CPU time	13.32 seconds
Started	Feb 07 01:26:53 PM PST 24
Finished	Feb 07 01:27:07 PM PST 24
Peak memory	201388 kb
Host	smart-75b0523f-fbdf-4c93-af88-420d33d20fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049520633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.4049520633
Directory	/workspace/32.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.adc_ctrl_stress_all.3775523064
Short name	T81
Test name
Test status
Simulation time	166695438621 ps
CPU time	374.07 seconds
Started	Feb 07 01:27:02 PM PST 24
Finished	Feb 07 01:33:18 PM PST 24
Peak memory	201608 kb
Host	smart-b93e2201-32e8-46dd-888e-2432c9c52527
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775523064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all .3775523064
Directory	/workspace/32.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.adc_ctrl_alert_test.32662624
Short name	T413
Test name
Test status
Simulation time	417838466 ps
CPU time	1.49 seconds
Started	Feb 07 01:26:59 PM PST 24
Finished	Feb 07 01:27:01 PM PST 24
Peak memory	201156 kb
Host	smart-1c0df565-8737-42c2-a194-7efa0e73f628
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.32662624
Directory	/workspace/33.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.adc_ctrl_clock_gating.720927670
Short name	T621
Test name
Test status
Simulation time	491986716979 ps
CPU time	104.74 seconds
Started	Feb 07 01:27:00 PM PST 24
Finished	Feb 07 01:28:46 PM PST 24
Peak memory	201584 kb
Host	smart-45d69ebb-876e-4ddc-b1b4-ad4c9b60afd2
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720927670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati ng.720927670
Directory	/workspace/33.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_interrupt.2908437209
Short name	T266
Test name
Test status
Simulation time	167007164731 ps
CPU time	98.23 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:28:36 PM PST 24
Peak memory	201584 kb
Host	smart-2ca2ea11-bc02-4ac7-b3f1-88f48f343282
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908437209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2908437209
Directory	/workspace/33.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4256731938
Short name	T744
Test name
Test status
Simulation time	493027179816 ps
CPU time	1114.83 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:45:32 PM PST 24
Peak memory	201616 kb
Host	smart-a7e9214b-1de4-4001-8424-5133b3ef265f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256731938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru pt_fixed.4256731938
Directory	/workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_polled.1177973390
Short name	T855
Test name
Test status
Simulation time	327900147250 ps
CPU time	384.31 seconds
Started	Feb 07 01:26:59 PM PST 24
Finished	Feb 07 01:33:24 PM PST 24
Peak memory	201616 kb
Host	smart-ca534214-fc36-4aca-8e3f-1024215d01a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177973390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1177973390
Directory	/workspace/33.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2180565050
Short name	T653
Test name
Test status
Simulation time	496666685567 ps
CPU time	290.7 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:31:49 PM PST 24
Peak memory	201548 kb
Host	smart-d9c0f69e-73ad-4d2d-b517-c02b729667fb
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180565050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix ed.2180565050
Directory	/workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_wakeup.479679600
Short name	T678
Test name
Test status
Simulation time	159895844065 ps
CPU time	87.07 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:28:25 PM PST 24
Peak memory	201532 kb
Host	smart-86675368-97db-4b7e-a816-d3ed8f75487a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479679600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_ wakeup.479679600
Directory	/workspace/33.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2458041721
Short name	T626
Test name
Test status
Simulation time	161803697706 ps
CPU time	85.99 seconds
Started	Feb 07 01:26:58 PM PST 24
Finished	Feb 07 01:28:25 PM PST 24
Peak memory	201620 kb
Host	smart-0f842825-2628-4130-98fc-2a50dfaa4ebe
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458041721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .adc_ctrl_filters_wakeup_fixed.2458041721
Directory	/workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_fsm_reset.3523233261
Short name	T136
Test name
Test status
Simulation time	105736331756 ps
CPU time	527.4 seconds
Started	Feb 07 01:27:00 PM PST 24
Finished	Feb 07 01:35:48 PM PST 24
Peak memory	201864 kb
Host	smart-b3af62ef-b5b9-474f-abc2-003d0280e395
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523233261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3523233261
Directory	/workspace/33.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/33.adc_ctrl_lowpower_counter.1416738909
Short name	T449
Test name
Test status
Simulation time	33590159324 ps
CPU time	10.98 seconds
Started	Feb 07 01:26:56 PM PST 24
Finished	Feb 07 01:27:07 PM PST 24
Peak memory	201352 kb
Host	smart-509d5e07-37fa-4d75-9f8a-75008c35c0c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416738909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1416738909
Directory	/workspace/33.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/33.adc_ctrl_poweron_counter.2182607785
Short name	T392
Test name
Test status
Simulation time	4369985743 ps
CPU time	5.92 seconds
Started	Feb 07 01:27:00 PM PST 24
Finished	Feb 07 01:27:07 PM PST 24
Peak memory	201408 kb
Host	smart-3b1cc0ec-bee3-4df6-bd2e-8daaf1e4fd97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182607785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2182607785
Directory	/workspace/33.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/33.adc_ctrl_smoke.1117679053
Short name	T481
Test name
Test status
Simulation time	5745273447 ps
CPU time	3.13 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:27:01 PM PST 24
Peak memory	201344 kb
Host	smart-ce55ddc4-4562-4f67-a934-509b91aa7252
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117679053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1117679053
Directory	/workspace/33.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.adc_ctrl_stress_all.1359886965
Short name	T609
Test name
Test status
Simulation time	15891306075 ps
CPU time	3.22 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:27:01 PM PST 24
Peak memory	201672 kb
Host	smart-3f81951f-729d-4376-ae12-cc7ddb66d56b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359886965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all .1359886965
Directory	/workspace/33.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2260399955
Short name	T709
Test name
Test status
Simulation time	85984768701 ps
CPU time	206.27 seconds
Started	Feb 07 01:26:57 PM PST 24
Finished	Feb 07 01:30:24 PM PST 24
Peak memory	210364 kb
Host	smart-5d35fa1e-708d-463b-afe9-12b259a385c6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260399955 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2260399955
Directory	/workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.adc_ctrl_alert_test.3261601400
Short name	T532
Test name
Test status
Simulation time	315067156 ps
CPU time	1.39 seconds
Started	Feb 07 01:27:11 PM PST 24
Finished	Feb 07 01:27:13 PM PST 24
Peak memory	201216 kb
Host	smart-34d28bd6-cfff-4212-9c33-1b93e75a48a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261601400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3261601400
Directory	/workspace/34.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.adc_ctrl_clock_gating.3270811898
Short name	T197
Test name
Test status
Simulation time	497106357861 ps
CPU time	264.38 seconds
Started	Feb 07 01:27:13 PM PST 24
Finished	Feb 07 01:31:38 PM PST 24
Peak memory	201584 kb
Host	smart-aafd99c1-ef74-4c71-85e2-dec8d0903483
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270811898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat ing.3270811898
Directory	/workspace/34.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_both.4142730041
Short name	T159
Test name
Test status
Simulation time	346196545308 ps
CPU time	205.09 seconds
Started	Feb 07 01:27:09 PM PST 24
Finished	Feb 07 01:30:35 PM PST 24
Peak memory	201676 kb
Host	smart-4d78d4ba-295b-40db-ad05-62dab2e8c34b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142730041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4142730041
Directory	/workspace/34.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_interrupt.137136636
Short name	T297
Test name
Test status
Simulation time	489289823976 ps
CPU time	1261.64 seconds
Started	Feb 07 01:26:59 PM PST 24
Finished	Feb 07 01:48:01 PM PST 24
Peak memory	201568 kb
Host	smart-4bc74ae8-13b6-4488-a6aa-dd65c424a3ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137136636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.137136636
Directory	/workspace/34.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2507821198
Short name	T605
Test name
Test status
Simulation time	327458261804 ps
CPU time	523.38 seconds
Started	Feb 07 01:27:09 PM PST 24
Finished	Feb 07 01:35:53 PM PST 24
Peak memory	201540 kb
Host	smart-1eec50b6-317a-4fa0-afea-c51831979784
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507821198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru pt_fixed.2507821198
Directory	/workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_polled.4126177614
Short name	T157
Test name
Test status
Simulation time	323977592730 ps
CPU time	78.58 seconds
Started	Feb 07 01:27:02 PM PST 24
Finished	Feb 07 01:28:22 PM PST 24
Peak memory	201720 kb
Host	smart-a6676fa6-9d2e-4c9b-8ad7-18d6d3f5ebbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126177614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4126177614
Directory	/workspace/34.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.145525833
Short name	T776
Test name
Test status
Simulation time	326299586737 ps
CPU time	193.65 seconds
Started	Feb 07 01:27:00 PM PST 24
Finished	Feb 07 01:30:15 PM PST 24
Peak memory	201636 kb
Host	smart-b44fae71-7262-4e8d-8739-e16c16d3da68
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=145525833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe d.145525833
Directory	/workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.290260602
Short name	T787
Test name
Test status
Simulation time	158736966888 ps
CPU time	357.15 seconds
Started	Feb 07 01:27:09 PM PST 24
Finished	Feb 07 01:33:07 PM PST 24
Peak memory	201648 kb
Host	smart-02bbad9a-7310-464b-95df-c921e5165d21
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290260602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. adc_ctrl_filters_wakeup_fixed.290260602
Directory	/workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_fsm_reset.292238770
Short name	T174
Test name
Test status
Simulation time	85943930323 ps
CPU time	334.59 seconds
Started	Feb 07 01:27:10 PM PST 24
Finished	Feb 07 01:32:46 PM PST 24
Peak memory	201820 kb
Host	smart-e2cd7ae8-fb9f-4ef2-ba36-3f551f480fe1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292238770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.292238770
Directory	/workspace/34.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/34.adc_ctrl_lowpower_counter.768715335
Short name	T461
Test name
Test status
Simulation time	43155646756 ps
CPU time	24.96 seconds
Started	Feb 07 01:27:12 PM PST 24
Finished	Feb 07 01:27:37 PM PST 24
Peak memory	201392 kb
Host	smart-dcb6d528-0e5f-461c-8ded-5171de353fc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768715335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.768715335
Directory	/workspace/34.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/34.adc_ctrl_poweron_counter.1499273425
Short name	T404
Test name
Test status
Simulation time	3808347633 ps
CPU time	8.84 seconds
Started	Feb 07 01:27:08 PM PST 24
Finished	Feb 07 01:27:17 PM PST 24
Peak memory	201392 kb
Host	smart-676d946a-3e46-4507-88b9-d25f11205643
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499273425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1499273425
Directory	/workspace/34.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/34.adc_ctrl_smoke.1418878055
Short name	T431
Test name
Test status
Simulation time	5676595117 ps
CPU time	13.56 seconds
Started	Feb 07 01:27:02 PM PST 24
Finished	Feb 07 01:27:17 PM PST 24
Peak memory	201428 kb
Host	smart-d3cd73f5-99c9-4640-bfef-df29461f8d2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418878055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1418878055
Directory	/workspace/34.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.adc_ctrl_stress_all.3587465496
Short name	T215
Test name
Test status
Simulation time	339552277819 ps
CPU time	92.74 seconds
Started	Feb 07 01:27:12 PM PST 24
Finished	Feb 07 01:28:45 PM PST 24
Peak memory	201648 kb
Host	smart-68ad36d9-2975-4193-8acb-b9c384f95c29
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587465496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all .3587465496
Directory	/workspace/34.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.adc_ctrl_alert_test.629903403
Short name	T736
Test name
Test status
Simulation time	373524630 ps
CPU time	0.91 seconds
Started	Feb 07 01:27:20 PM PST 24
Finished	Feb 07 01:27:22 PM PST 24
Peak memory	201256 kb
Host	smart-e3f17f26-f476-433f-9ea1-8dff6db0ac08
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629903403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.629903403
Directory	/workspace/35.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.adc_ctrl_clock_gating.863485925
Short name	T118
Test name
Test status
Simulation time	327785803680 ps
CPU time	690.74 seconds
Started	Feb 07 01:27:27 PM PST 24
Finished	Feb 07 01:38:58 PM PST 24
Peak memory	201464 kb
Host	smart-88258e07-328b-4483-9f63-83af5cfec10a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863485925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati ng.863485925
Directory	/workspace/35.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_both.2500785197
Short name	T623
Test name
Test status
Simulation time	491846335061 ps
CPU time	1062.6 seconds
Started	Feb 07 01:27:24 PM PST 24
Finished	Feb 07 01:45:07 PM PST 24
Peak memory	201648 kb
Host	smart-bf5cc505-09bf-4be0-8253-e4d7ecccb3f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500785197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2500785197
Directory	/workspace/35.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_interrupt.2697767023
Short name	T46
Test name
Test status
Simulation time	328010195720 ps
CPU time	389.66 seconds
Started	Feb 07 01:27:09 PM PST 24
Finished	Feb 07 01:33:39 PM PST 24
Peak memory	201660 kb
Host	smart-f596c9b5-972f-44c7-bca1-6e2ddcd64de0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697767023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2697767023
Directory	/workspace/35.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3916955158
Short name	T525
Test name
Test status
Simulation time	482394541021 ps
CPU time	357 seconds
Started	Feb 07 01:27:27 PM PST 24
Finished	Feb 07 01:33:25 PM PST 24
Peak memory	201444 kb
Host	smart-4e68923a-94f9-4d6b-8143-fe80cb1d2c62
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916955158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru pt_fixed.3916955158
Directory	/workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_polled.2193720788
Short name	T603
Test name
Test status
Simulation time	338224314124 ps
CPU time	325.78 seconds
Started	Feb 07 01:27:11 PM PST 24
Finished	Feb 07 01:32:37 PM PST 24
Peak memory	201668 kb
Host	smart-805751e8-c7eb-4880-8168-bb4de19bbe2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193720788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2193720788
Directory	/workspace/35.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3663111873
Short name	T395
Test name
Test status
Simulation time	325973762757 ps
CPU time	476.89 seconds
Started	Feb 07 01:27:09 PM PST 24
Finished	Feb 07 01:35:07 PM PST 24
Peak memory	201492 kb
Host	smart-7098998d-a43d-4478-801e-b66e8d6bad49
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663111873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix ed.3663111873
Directory	/workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_wakeup.701920434
Short name	T577
Test name
Test status
Simulation time	164578492896 ps
CPU time	146.8 seconds
Started	Feb 07 01:27:24 PM PST 24
Finished	Feb 07 01:29:51 PM PST 24
Peak memory	201640 kb
Host	smart-a74a3bde-e495-4c15-b751-0e148100faf0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701920434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_ wakeup.701920434
Directory	/workspace/35.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3986239441
Short name	T748
Test name
Test status
Simulation time	333994257922 ps
CPU time	199.22 seconds
Started	Feb 07 01:27:22 PM PST 24
Finished	Feb 07 01:30:41 PM PST 24
Peak memory	201628 kb
Host	smart-8b712c0a-dde5-4f8f-b352-8c1c7e032f8f
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986239441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .adc_ctrl_filters_wakeup_fixed.3986239441
Directory	/workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/35.adc_ctrl_fsm_reset.2384735633
Short name	T633
Test name
Test status
Simulation time	76932120290 ps
CPU time	268.92 seconds
Started	Feb 07 01:27:21 PM PST 24
Finished	Feb 07 01:31:50 PM PST 24
Peak memory	201852 kb
Host	smart-4c350e6d-ffad-4524-8814-920436e19d88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384735633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2384735633
Directory	/workspace/35.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/35.adc_ctrl_lowpower_counter.700656541
Short name	T803
Test name
Test status
Simulation time	23703901897 ps
CPU time	12.43 seconds
Started	Feb 07 01:27:25 PM PST 24
Finished	Feb 07 01:27:38 PM PST 24
Peak memory	201404 kb
Host	smart-b95ee3e3-2eb0-4e64-a1b1-f6998f35ad3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700656541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.700656541
Directory	/workspace/35.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/35.adc_ctrl_poweron_counter.3758579800
Short name	T83
Test name
Test status
Simulation time	3726529861 ps
CPU time	3.02 seconds
Started	Feb 07 01:27:23 PM PST 24
Finished	Feb 07 01:27:26 PM PST 24
Peak memory	201436 kb
Host	smart-064f5130-7b41-42bd-9ed2-c99a008e4b46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3758579800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3758579800
Directory	/workspace/35.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/35.adc_ctrl_smoke.1308108498
Short name	T773
Test name
Test status
Simulation time	6000450533 ps
CPU time	6.23 seconds
Started	Feb 07 01:27:11 PM PST 24
Finished	Feb 07 01:27:17 PM PST 24
Peak memory	201260 kb
Host	smart-2951b5a1-1dfe-4db7-8ef6-95fbccabd805
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308108498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1308108498
Directory	/workspace/35.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.adc_ctrl_stress_all.3120313135
Short name	T142
Test name
Test status
Simulation time	335300976626 ps
CPU time	66.81 seconds
Started	Feb 07 01:27:21 PM PST 24
Finished	Feb 07 01:28:28 PM PST 24
Peak memory	201616 kb
Host	smart-8a93e4f4-17f8-469e-ad32-9d54c9975209
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120313135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all .3120313135
Directory	/workspace/35.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.adc_ctrl_alert_test.493689536
Short name	T441
Test name
Test status
Simulation time	285087522 ps
CPU time	0.99 seconds
Started	Feb 07 01:27:41 PM PST 24
Finished	Feb 07 01:27:42 PM PST 24
Peak memory	201332 kb
Host	smart-92db019f-f5e8-44b5-81c4-aa0e0b945522
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493689536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.493689536
Directory	/workspace/36.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_both.3445532559
Short name	T306
Test name
Test status
Simulation time	473816424703 ps
CPU time	279.83 seconds
Started	Feb 07 01:27:39 PM PST 24
Finished	Feb 07 01:32:20 PM PST 24
Peak memory	201708 kb
Host	smart-c4d8c4c3-3004-49a2-b7d9-6c118838e98d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445532559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3445532559
Directory	/workspace/36.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_interrupt.3053631422
Short name	T628
Test name
Test status
Simulation time	325074561690 ps
CPU time	386.38 seconds
Started	Feb 07 01:27:38 PM PST 24
Finished	Feb 07 01:34:05 PM PST 24
Peak memory	201564 kb
Host	smart-b87e1d1e-d2b8-4654-a23c-43101b5654d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053631422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3053631422
Directory	/workspace/36.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4027094522
Short name	T836
Test name
Test status
Simulation time	484553021298 ps
CPU time	298.68 seconds
Started	Feb 07 01:27:38 PM PST 24
Finished	Feb 07 01:32:37 PM PST 24
Peak memory	201584 kb
Host	smart-79b1e276-aba4-45f4-a952-74b6e57a052c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027094522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru pt_fixed.4027094522
Directory	/workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_polled.2110534521
Short name	T777
Test name
Test status
Simulation time	327368250851 ps
CPU time	735.29 seconds
Started	Feb 07 01:27:19 PM PST 24
Finished	Feb 07 01:39:35 PM PST 24
Peak memory	201644 kb
Host	smart-a4ec8397-01cf-467c-9857-069f0e0ac247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110534521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2110534521
Directory	/workspace/36.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2043669173
Short name	T612
Test name
Test status
Simulation time	166702409098 ps
CPU time	389.23 seconds
Started	Feb 07 01:27:24 PM PST 24
Finished	Feb 07 01:33:53 PM PST 24
Peak memory	201640 kb
Host	smart-d6890d12-9bea-40d1-9c31-c95603511d5a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043669173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix ed.2043669173
Directory	/workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_wakeup.1652507339
Short name	T791
Test name
Test status
Simulation time	168964034644 ps
CPU time	72.38 seconds
Started	Feb 07 01:27:37 PM PST 24
Finished	Feb 07 01:28:50 PM PST 24
Peak memory	201696 kb
Host	smart-8d859c69-85c6-41c4-98c1-427fb147de30
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652507339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters _wakeup.1652507339
Directory	/workspace/36.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1935989060
Short name	T681
Test name
Test status
Simulation time	167765906421 ps
CPU time	101.68 seconds
Started	Feb 07 01:27:40 PM PST 24
Finished	Feb 07 01:29:22 PM PST 24
Peak memory	201568 kb
Host	smart-a83080b8-5050-403d-b2f6-91d14068bb29
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935989060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .adc_ctrl_filters_wakeup_fixed.1935989060
Directory	/workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_fsm_reset.4100351679
Short name	T827
Test name
Test status
Simulation time	126481897991 ps
CPU time	656.54 seconds
Started	Feb 07 01:27:38 PM PST 24
Finished	Feb 07 01:38:35 PM PST 24
Peak memory	201936 kb
Host	smart-66fd1f4c-0f43-4ddf-a445-66b660dd015d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100351679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.4100351679
Directory	/workspace/36.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/36.adc_ctrl_lowpower_counter.2050410535
Short name	T521
Test name
Test status
Simulation time	35035113726 ps
CPU time	23.64 seconds
Started	Feb 07 01:27:37 PM PST 24
Finished	Feb 07 01:28:01 PM PST 24
Peak memory	201396 kb
Host	smart-b1481e7e-648f-42af-ad19-0061e59ce500
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050410535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2050410535
Directory	/workspace/36.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/36.adc_ctrl_poweron_counter.181548934
Short name	T792
Test name
Test status
Simulation time	3457675682 ps
CPU time	2.57 seconds
Started	Feb 07 01:27:35 PM PST 24
Finished	Feb 07 01:27:38 PM PST 24
Peak memory	201356 kb
Host	smart-235293e8-91e7-42ba-b763-a74e14206a23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=181548934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.181548934
Directory	/workspace/36.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/36.adc_ctrl_smoke.2595774620
Short name	T825
Test name
Test status
Simulation time	5926517975 ps
CPU time	3.67 seconds
Started	Feb 07 01:27:22 PM PST 24
Finished	Feb 07 01:27:26 PM PST 24
Peak memory	201416 kb
Host	smart-e0a293b9-cc80-41e1-ad65-cf33fdb351cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595774620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2595774620
Directory	/workspace/36.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.adc_ctrl_stress_all.2359375399
Short name	T148
Test name
Test status
Simulation time	366959102564 ps
CPU time	886.68 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:42:30 PM PST 24
Peak memory	201604 kb
Host	smart-41a14e20-561f-41e3-a7b2-f5a53f5584d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359375399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all .2359375399
Directory	/workspace/36.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.adc_ctrl_alert_test.2341441368
Short name	T861
Test name
Test status
Simulation time	420844514 ps
CPU time	0.83 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:27:43 PM PST 24
Peak memory	201236 kb
Host	smart-36e99979-fa38-4223-87e5-11ac9235d3dd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341441368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2341441368
Directory	/workspace/37.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.adc_ctrl_clock_gating.2069974188
Short name	T258
Test name
Test status
Simulation time	164243544271 ps
CPU time	378.4 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:34:01 PM PST 24
Peak memory	201584 kb
Host	smart-d465d150-3e34-448d-be4a-37845089d475
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069974188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat ing.2069974188
Directory	/workspace/37.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_both.617475886
Short name	T225
Test name
Test status
Simulation time	165847112093 ps
CPU time	105.52 seconds
Started	Feb 07 01:27:43 PM PST 24
Finished	Feb 07 01:29:29 PM PST 24
Peak memory	201476 kb
Host	smart-19994d27-b4a9-4f43-8c40-f72afed2d0e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617475886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.617475886
Directory	/workspace/37.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_interrupt.3132409855
Short name	T445
Test name
Test status
Simulation time	162193307965 ps
CPU time	23.44 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:28:06 PM PST 24
Peak memory	201616 kb
Host	smart-3473af2a-2412-4251-bcc3-84bca5938e02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132409855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3132409855
Directory	/workspace/37.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3802942006
Short name	T851
Test name
Test status
Simulation time	482775412612 ps
CPU time	1064.29 seconds
Started	Feb 07 01:27:55 PM PST 24
Finished	Feb 07 01:45:45 PM PST 24
Peak memory	201496 kb
Host	smart-a37daacf-50d6-4145-9a87-d77dc8011837
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802942006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru pt_fixed.3802942006
Directory	/workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_polled.2199792338
Short name	T551
Test name
Test status
Simulation time	168095971499 ps
CPU time	212.13 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:31:15 PM PST 24
Peak memory	201592 kb
Host	smart-3fe5eb9f-3a54-4d6f-a232-ea5c4cd1e52d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199792338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2199792338
Directory	/workspace/37.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3151689355
Short name	T14
Test name
Test status
Simulation time	488658507156 ps
CPU time	277.24 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:32:20 PM PST 24
Peak memory	201544 kb
Host	smart-5a038e2f-b2bf-41c0-b72a-b47e0a366dc4
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151689355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix ed.3151689355
Directory	/workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_wakeup.3112848655
Short name	T242
Test name
Test status
Simulation time	168507480231 ps
CPU time	396.76 seconds
Started	Feb 07 01:27:41 PM PST 24
Finished	Feb 07 01:34:18 PM PST 24
Peak memory	201604 kb
Host	smart-c0c86758-2d0e-4ad1-811b-ad8fa5b7823e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112848655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters _wakeup.3112848655
Directory	/workspace/37.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3058765110
Short name	T519
Test name
Test status
Simulation time	165124375101 ps
CPU time	412.86 seconds
Started	Feb 07 01:27:41 PM PST 24
Finished	Feb 07 01:34:35 PM PST 24
Peak memory	201532 kb
Host	smart-e4c2b793-9b71-4255-83a1-b387ee731f99
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058765110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .adc_ctrl_filters_wakeup_fixed.3058765110
Directory	/workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_lowpower_counter.3414332976
Short name	T734
Test name
Test status
Simulation time	26830747866 ps
CPU time	9.5 seconds
Started	Feb 07 01:27:41 PM PST 24
Finished	Feb 07 01:27:51 PM PST 24
Peak memory	201396 kb
Host	smart-bc93273a-d424-4c99-9482-661b6f93ac98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414332976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3414332976
Directory	/workspace/37.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/37.adc_ctrl_poweron_counter.2663768691
Short name	T833
Test name
Test status
Simulation time	4024480141 ps
CPU time	2.94 seconds
Started	Feb 07 01:27:43 PM PST 24
Finished	Feb 07 01:27:46 PM PST 24
Peak memory	201412 kb
Host	smart-2f59dbb8-5888-4107-8856-a0422dcb3dbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663768691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2663768691
Directory	/workspace/37.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/37.adc_ctrl_smoke.1073931080
Short name	T436
Test name
Test status
Simulation time	5860835184 ps
CPU time	4.04 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:27:46 PM PST 24
Peak memory	201392 kb
Host	smart-8c9cd742-76aa-4316-a9eb-8fe88af3dfec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073931080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1073931080
Directory	/workspace/37.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.adc_ctrl_stress_all.2548341835
Short name	T234
Test name
Test status
Simulation time	204778670839 ps
CPU time	243.55 seconds
Started	Feb 07 01:27:42 PM PST 24
Finished	Feb 07 01:31:46 PM PST 24
Peak memory	201556 kb
Host	smart-5aa21f31-2eeb-42eb-b11b-4abdbcf0f051
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548341835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all .2548341835
Directory	/workspace/37.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.724813757
Short name	T315
Test name
Test status
Simulation time	195534659036 ps
CPU time	228.38 seconds
Started	Feb 07 01:27:41 PM PST 24
Finished	Feb 07 01:31:30 PM PST 24
Peak memory	210288 kb
Host	smart-5165e71e-303f-40bc-bb4b-942321f6cf93
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724813757 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.724813757
Directory	/workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.adc_ctrl_alert_test.4263087678
Short name	T602
Test name
Test status
Simulation time	354195131 ps
CPU time	0.71 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:28:22 PM PST 24
Peak memory	200956 kb
Host	smart-a3d3c3b6-edbc-4eee-baa9-dc519b8aa98e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263087678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4263087678
Directory	/workspace/38.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_both.2550333714
Short name	T640
Test name
Test status
Simulation time	485055094107 ps
CPU time	187.6 seconds
Started	Feb 07 01:27:57 PM PST 24
Finished	Feb 07 01:31:09 PM PST 24
Peak memory	201636 kb
Host	smart-abca6021-46f3-4d07-ac49-466da4646ba9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550333714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2550333714
Directory	/workspace/38.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_interrupt.2334898446
Short name	T659
Test name
Test status
Simulation time	494099203475 ps
CPU time	1202.11 seconds
Started	Feb 07 01:27:53 PM PST 24
Finished	Feb 07 01:47:57 PM PST 24
Peak memory	201628 kb
Host	smart-bd6c7959-d631-42f4-9b36-cec38e50a799
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334898446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2334898446
Directory	/workspace/38.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1166923419
Short name	T775
Test name
Test status
Simulation time	489670105126 ps
CPU time	1171.77 seconds
Started	Feb 07 01:27:54 PM PST 24
Finished	Feb 07 01:47:32 PM PST 24
Peak memory	201572 kb
Host	smart-ece746a1-61aa-4fe7-9a5b-07d7a13b81b4
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166923419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru pt_fixed.1166923419
Directory	/workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2121230696
Short name	T507
Test name
Test status
Simulation time	333590155397 ps
CPU time	133.37 seconds
Started	Feb 07 01:27:55 PM PST 24
Finished	Feb 07 01:30:14 PM PST 24
Peak memory	201544 kb
Host	smart-06137dc8-6266-47b3-ac69-58d82492822c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121230696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix ed.2121230696
Directory	/workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_wakeup.196670974
Short name	T610
Test name
Test status
Simulation time	159982407840 ps
CPU time	188.34 seconds
Started	Feb 07 01:27:54 PM PST 24
Finished	Feb 07 01:31:09 PM PST 24
Peak memory	201664 kb
Host	smart-47ab5524-1f13-46df-bb36-8fa47a214107
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196670974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_ wakeup.196670974
Directory	/workspace/38.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.851270501
Short name	T394
Test name
Test status
Simulation time	164328471329 ps
CPU time	98.21 seconds
Started	Feb 07 01:27:57 PM PST 24
Finished	Feb 07 01:29:39 PM PST 24
Peak memory	201520 kb
Host	smart-2d935081-2d53-4c15-86f9-e9533c4841ad
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851270501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. adc_ctrl_filters_wakeup_fixed.851270501
Directory	/workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_fsm_reset.2253956103
Short name	T715
Test name
Test status
Simulation time	116673701648 ps
CPU time	545.28 seconds
Started	Feb 07 01:27:54 PM PST 24
Finished	Feb 07 01:37:05 PM PST 24
Peak memory	201936 kb
Host	smart-5b21a3c1-9d4f-4fc2-8bd2-8e64ad0d8650
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253956103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2253956103
Directory	/workspace/38.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/38.adc_ctrl_lowpower_counter.2884321554
Short name	T435
Test name
Test status
Simulation time	46446459709 ps
CPU time	13.62 seconds
Started	Feb 07 01:27:53 PM PST 24
Finished	Feb 07 01:28:09 PM PST 24
Peak memory	201380 kb
Host	smart-f673476f-2815-4692-aa80-63dfeaf4ae08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2884321554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2884321554
Directory	/workspace/38.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/38.adc_ctrl_poweron_counter.2512990697
Short name	T491
Test name
Test status
Simulation time	4888755193 ps
CPU time	1.48 seconds
Started	Feb 07 01:27:53 PM PST 24
Finished	Feb 07 01:27:57 PM PST 24
Peak memory	201360 kb
Host	smart-feed7722-d74e-43b0-9865-adf8becfb665
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512990697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2512990697
Directory	/workspace/38.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/38.adc_ctrl_smoke.61236984
Short name	T582
Test name
Test status
Simulation time	5850961247 ps
CPU time	7.47 seconds
Started	Feb 07 01:27:54 PM PST 24
Finished	Feb 07 01:28:08 PM PST 24
Peak memory	201428 kb
Host	smart-c5da904e-77ab-4c0a-9e95-cd3d2d0b40ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61236984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.61236984
Directory	/workspace/38.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.adc_ctrl_stress_all.3921529109
Short name	T241
Test name
Test status
Simulation time	356330344797 ps
CPU time	708.69 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:40:10 PM PST 24
Peak memory	201224 kb
Host	smart-63d31b3d-9b3f-4d6a-8763-26565b4c0bd3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921529109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all .3921529109
Directory	/workspace/38.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.adc_ctrl_alert_test.2180437051
Short name	T408
Test name
Test status
Simulation time	339515600 ps
CPU time	1.03 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:28:22 PM PST 24
Peak memory	201220 kb
Host	smart-29d4b753-8696-49cc-b878-e05d9519da84
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180437051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2180437051
Directory	/workspace/39.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.adc_ctrl_clock_gating.1062238337
Short name	T314
Test name
Test status
Simulation time	494131959472 ps
CPU time	523.99 seconds
Started	Feb 07 01:28:15 PM PST 24
Finished	Feb 07 01:37:00 PM PST 24
Peak memory	201624 kb
Host	smart-6b4cb6d2-8ea2-4343-a081-097efa9297a1
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062238337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat ing.1062238337
Directory	/workspace/39.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_both.871987743
Short name	T305
Test name
Test status
Simulation time	495969351108 ps
CPU time	307.77 seconds
Started	Feb 07 01:28:19 PM PST 24
Finished	Feb 07 01:33:29 PM PST 24
Peak memory	201592 kb
Host	smart-0bb28f21-5105-4699-bea3-4df9fd94d305
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=871987743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.871987743
Directory	/workspace/39.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_interrupt.1864581021
Short name	T220
Test name
Test status
Simulation time	168771840746 ps
CPU time	290.09 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:33:11 PM PST 24
Peak memory	201664 kb
Host	smart-c808e553-6ac8-4842-85ab-6023030d7c63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864581021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1864581021
Directory	/workspace/39.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.726433808
Short name	T759
Test name
Test status
Simulation time	159227888735 ps
CPU time	24.88 seconds
Started	Feb 07 01:28:15 PM PST 24
Finished	Feb 07 01:28:41 PM PST 24
Peak memory	201500 kb
Host	smart-f3346551-e28b-47c7-937e-e18a64e450ab
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=726433808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup t_fixed.726433808
Directory	/workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_polled.1976082429
Short name	T565
Test name
Test status
Simulation time	477713882893 ps
CPU time	193.15 seconds
Started	Feb 07 01:28:16 PM PST 24
Finished	Feb 07 01:31:33 PM PST 24
Peak memory	201620 kb
Host	smart-440c1c96-d7ef-4b5f-a815-d27d09f62efa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976082429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1976082429
Directory	/workspace/39.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1670101415
Short name	T410
Test name
Test status
Simulation time	162642317908 ps
CPU time	34.25 seconds
Started	Feb 07 01:28:16 PM PST 24
Finished	Feb 07 01:28:55 PM PST 24
Peak memory	201612 kb
Host	smart-3824a385-5516-442b-a88f-6208059be0a3
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670101415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix ed.1670101415
Directory	/workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_wakeup.2092022372
Short name	T857
Test name
Test status
Simulation time	162920616320 ps
CPU time	23.17 seconds
Started	Feb 07 01:28:16 PM PST 24
Finished	Feb 07 01:28:44 PM PST 24
Peak memory	201580 kb
Host	smart-b85b3914-2235-4c00-b43e-f198016cc074
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092022372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters _wakeup.2092022372
Directory	/workspace/39.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1963960499
Short name	T460
Test name
Test status
Simulation time	160384743851 ps
CPU time	103.43 seconds
Started	Feb 07 01:28:15 PM PST 24
Finished	Feb 07 01:30:03 PM PST 24
Peak memory	201596 kb
Host	smart-7ebe3947-64e9-414b-b7aa-1a027a64cf18
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963960499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .adc_ctrl_filters_wakeup_fixed.1963960499
Directory	/workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_fsm_reset.3242144593
Short name	T185
Test name
Test status
Simulation time	76826475243 ps
CPU time	303.29 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:33:24 PM PST 24
Peak memory	201936 kb
Host	smart-cb5dd5cb-f4d0-48fd-befc-ee99e9dbb2b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3242144593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3242144593
Directory	/workspace/39.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/39.adc_ctrl_lowpower_counter.3189898797
Short name	T536
Test name
Test status
Simulation time	24140307756 ps
CPU time	50.18 seconds
Started	Feb 07 01:28:17 PM PST 24
Finished	Feb 07 01:29:11 PM PST 24
Peak memory	201260 kb
Host	smart-25659287-7bb2-40b9-8222-e5e87e23b03a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189898797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3189898797
Directory	/workspace/39.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/39.adc_ctrl_poweron_counter.1262011637
Short name	T550
Test name
Test status
Simulation time	2859984038 ps
CPU time	6.66 seconds
Started	Feb 07 01:28:15 PM PST 24
Finished	Feb 07 01:28:22 PM PST 24
Peak memory	201396 kb
Host	smart-a0e2ac2f-cc02-4528-85c3-d95f2922cd05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262011637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1262011637
Directory	/workspace/39.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/39.adc_ctrl_smoke.4019402477
Short name	T781
Test name
Test status
Simulation time	6150853745 ps
CPU time	2.92 seconds
Started	Feb 07 01:28:16 PM PST 24
Finished	Feb 07 01:28:24 PM PST 24
Peak memory	201400 kb
Host	smart-778bc2b8-5f7a-4872-a5a4-d7c661effce4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019402477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4019402477
Directory	/workspace/39.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.adc_ctrl_stress_all.4056330290
Short name	T303
Test name
Test status
Simulation time	171477801743 ps
CPU time	392.84 seconds
Started	Feb 07 01:28:17 PM PST 24
Finished	Feb 07 01:34:54 PM PST 24
Peak memory	201552 kb
Host	smart-ddd387ec-2f9b-4622-bb4c-7baf1c33ee0c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056330290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all .4056330290
Directory	/workspace/39.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.582867035
Short name	T717
Test name
Test status
Simulation time	59985624851 ps
CPU time	110.95 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:30:12 PM PST 24
Peak memory	210288 kb
Host	smart-8be07191-dcdf-44f9-b5ac-a04d7e7bdbc6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582867035 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.582867035
Directory	/workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.adc_ctrl_alert_test.1001466136
Short name	T858
Test name
Test status
Simulation time	536936402 ps
CPU time	0.97 seconds
Started	Feb 07 01:19:30 PM PST 24
Finished	Feb 07 01:19:34 PM PST 24
Peak memory	201292 kb
Host	smart-c7a6c0c0-61e1-4d21-a83d-fc6d8d697434
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001466136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1001466136
Directory	/workspace/4.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_interrupt.2471982601
Short name	T854
Test name
Test status
Simulation time	158566609328 ps
CPU time	89.86 seconds
Started	Feb 07 01:19:28 PM PST 24
Finished	Feb 07 01:21:00 PM PST 24
Peak memory	201624 kb
Host	smart-167248d2-0b26-4ef9-8c92-c8c5d86b7342
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471982601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2471982601
Directory	/workspace/4.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.293096532
Short name	T847
Test name
Test status
Simulation time	324695818833 ps
CPU time	214.71 seconds
Started	Feb 07 01:19:28 PM PST 24
Finished	Feb 07 01:23:06 PM PST 24
Peak memory	201536 kb
Host	smart-f37b040a-ad7c-4e7f-b7c4-2e64f454c6e5
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=293096532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt _fixed.293096532
Directory	/workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_polled.1299046899
Short name	T728
Test name
Test status
Simulation time	324424983362 ps
CPU time	189.94 seconds
Started	Feb 07 01:19:35 PM PST 24
Finished	Feb 07 01:22:46 PM PST 24
Peak memory	201664 kb
Host	smart-5b332a9e-9e59-4287-af05-ea5fe7c10909
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299046899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1299046899
Directory	/workspace/4.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.840161561
Short name	T132
Test name
Test status
Simulation time	331402804230 ps
CPU time	203.66 seconds
Started	Feb 07 01:19:30 PM PST 24
Finished	Feb 07 01:22:56 PM PST 24
Peak memory	201648 kb
Host	smart-d8716440-16f2-4bf4-b4aa-731f6c737493
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=840161561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed .840161561
Directory	/workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_wakeup.892585727
Short name	T804
Test name
Test status
Simulation time	333069447604 ps
CPU time	201.99 seconds
Started	Feb 07 01:19:31 PM PST 24
Finished	Feb 07 01:22:55 PM PST 24
Peak memory	201636 kb
Host	smart-3e955022-d83b-4877-8513-0fd28158067b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892585727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w akeup.892585727
Directory	/workspace/4.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.129559761
Short name	T388
Test name
Test status
Simulation time	320950793999 ps
CPU time	732.07 seconds
Started	Feb 07 01:19:29 PM PST 24
Finished	Feb 07 01:31:43 PM PST 24
Peak memory	201720 kb
Host	smart-ee5b0cb9-48af-482b-82bd-9319c386793c
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129559761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a dc_ctrl_filters_wakeup_fixed.129559761
Directory	/workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/4.adc_ctrl_fsm_reset.1548428114
Short name	T772
Test name
Test status
Simulation time	123500697335 ps
CPU time	441.93 seconds
Started	Feb 07 01:19:29 PM PST 24
Finished	Feb 07 01:26:53 PM PST 24
Peak memory	201932 kb
Host	smart-8ccede47-1940-471f-b435-6f07f8523030
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548428114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1548428114
Directory	/workspace/4.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/4.adc_ctrl_lowpower_counter.2385179910
Short name	T588
Test name
Test status
Simulation time	46317390459 ps
CPU time	17.14 seconds
Started	Feb 07 01:19:30 PM PST 24
Finished	Feb 07 01:19:50 PM PST 24
Peak memory	201384 kb
Host	smart-e2f749bc-e717-4994-8e45-9cc8211b8636
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385179910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2385179910
Directory	/workspace/4.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/4.adc_ctrl_poweron_counter.2313153964
Short name	T538
Test name
Test status
Simulation time	4247505143 ps
CPU time	10.82 seconds
Started	Feb 07 01:19:32 PM PST 24
Finished	Feb 07 01:19:44 PM PST 24
Peak memory	201396 kb
Host	smart-a10e3991-0413-443a-a802-fbb6d15006df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313153964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2313153964
Directory	/workspace/4.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/4.adc_ctrl_sec_cm.1283200183
Short name	T40
Test name
Test status
Simulation time	4111789902 ps
CPU time	3.31 seconds
Started	Feb 07 01:19:31 PM PST 24
Finished	Feb 07 01:19:36 PM PST 24
Peak memory	216720 kb
Host	smart-93c82dfc-dcab-4ee3-94f7-d87ec4d52f28
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283200183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1283200183
Directory	/workspace/4.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.adc_ctrl_smoke.2702808277
Short name	T82
Test name
Test status
Simulation time	6077207271 ps
CPU time	14.28 seconds
Started	Feb 07 01:19:28 PM PST 24
Finished	Feb 07 01:19:45 PM PST 24
Peak memory	201300 kb
Host	smart-7c234314-e937-44a3-a6c8-93a66b49e12d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702808277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2702808277
Directory	/workspace/4.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.adc_ctrl_stress_all.3862694299
Short name	T615
Test name
Test status
Simulation time	168971714234 ps
CPU time	189.28 seconds
Started	Feb 07 01:19:29 PM PST 24
Finished	Feb 07 01:22:40 PM PST 24
Peak memory	201624 kb
Host	smart-87adba18-8a92-4616-847c-92f37520d7b7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862694299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all. 3862694299
Directory	/workspace/4.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2389954186
Short name	T12
Test name
Test status
Simulation time	31049758533 ps
CPU time	51.94 seconds
Started	Feb 07 01:19:29 PM PST 24
Finished	Feb 07 01:20:25 PM PST 24
Peak memory	209952 kb
Host	smart-68244da6-fa2b-4284-b8f1-afb882086be4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389954186 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2389954186
Directory	/workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.adc_ctrl_alert_test.3776851768
Short name	T769
Test name
Test status
Simulation time	499019427 ps
CPU time	1.17 seconds
Started	Feb 07 01:28:20 PM PST 24
Finished	Feb 07 01:28:28 PM PST 24
Peak memory	201264 kb
Host	smart-ca8bf9e6-aaed-4203-99ea-d69b7e317406
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776851768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3776851768
Directory	/workspace/40.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_both.3812136146
Short name	T146
Test name
Test status
Simulation time	499872292908 ps
CPU time	273.63 seconds
Started	Feb 07 01:28:20 PM PST 24
Finished	Feb 07 01:33:00 PM PST 24
Peak memory	201644 kb
Host	smart-8f816e3d-ed00-4357-be27-b0fa86628c2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812136146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3812136146
Directory	/workspace/40.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_interrupt.4241882975
Short name	T249
Test name
Test status
Simulation time	168996422841 ps
CPU time	126.04 seconds
Started	Feb 07 01:28:19 PM PST 24
Finished	Feb 07 01:30:27 PM PST 24
Peak memory	201640 kb
Host	smart-29d40139-a85e-4de0-ba74-c5811715fd91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241882975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.4241882975
Directory	/workspace/40.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1880399017
Short name	T465
Test name
Test status
Simulation time	497376921696 ps
CPU time	1125.44 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:47:07 PM PST 24
Peak memory	201564 kb
Host	smart-36caca51-d610-4dee-a29d-c2685d221b2c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880399017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru pt_fixed.1880399017
Directory	/workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_polled.3404611044
Short name	T806
Test name
Test status
Simulation time	490152110315 ps
CPU time	536.53 seconds
Started	Feb 07 01:28:21 PM PST 24
Finished	Feb 07 01:37:24 PM PST 24
Peak memory	201448 kb
Host	smart-29c74384-f79a-4528-95b4-cb8b284c9c02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404611044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3404611044
Directory	/workspace/40.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3131621800
Short name	T830
Test name
Test status
Simulation time	162194135992 ps
CPU time	86.66 seconds
Started	Feb 07 01:28:21 PM PST 24
Finished	Feb 07 01:29:54 PM PST 24
Peak memory	201392 kb
Host	smart-9c091f45-eabc-47c6-a60b-8f0c975d1d0b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131621800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix ed.3131621800
Directory	/workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2207760519
Short name	T473
Test name
Test status
Simulation time	329707928242 ps
CPU time	755.46 seconds
Started	Feb 07 01:28:20 PM PST 24
Finished	Feb 07 01:40:58 PM PST 24
Peak memory	201664 kb
Host	smart-db054172-cbdd-4fc6-be14-33b045cd3c41
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207760519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .adc_ctrl_filters_wakeup_fixed.2207760519
Directory	/workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_fsm_reset.185570703
Short name	T171
Test name
Test status
Simulation time	97124463643 ps
CPU time	325.73 seconds
Started	Feb 07 01:28:19 PM PST 24
Finished	Feb 07 01:33:47 PM PST 24
Peak memory	201928 kb
Host	smart-b52e5f04-7cad-426e-8f76-17159101735a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185570703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.185570703
Directory	/workspace/40.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/40.adc_ctrl_lowpower_counter.3395072797
Short name	T801
Test name
Test status
Simulation time	41257584015 ps
CPU time	42.64 seconds
Started	Feb 07 01:28:17 PM PST 24
Finished	Feb 07 01:29:04 PM PST 24
Peak memory	201460 kb
Host	smart-40ccfaa6-0421-4f7e-9495-bfc484f1b983
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395072797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3395072797
Directory	/workspace/40.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/40.adc_ctrl_poweron_counter.2847722979
Short name	T695
Test name
Test status
Simulation time	3469520630 ps
CPU time	2.62 seconds
Started	Feb 07 01:28:16 PM PST 24
Finished	Feb 07 01:28:23 PM PST 24
Peak memory	201392 kb
Host	smart-c1984343-51aa-4a44-b3fd-14edd3e3fef4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847722979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2847722979
Directory	/workspace/40.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/40.adc_ctrl_smoke.3707029876
Short name	T590
Test name
Test status
Simulation time	5630320744 ps
CPU time	15.21 seconds
Started	Feb 07 01:28:18 PM PST 24
Finished	Feb 07 01:28:36 PM PST 24
Peak memory	201316 kb
Host	smart-480e2a48-ce93-4a50-9893-4113f21d69aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707029876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3707029876
Directory	/workspace/40.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.adc_ctrl_stress_all.3355615285
Short name	T322
Test name
Test status
Simulation time	144873285417 ps
CPU time	538.64 seconds
Started	Feb 07 01:28:17 PM PST 24
Finished	Feb 07 01:37:20 PM PST 24
Peak memory	218140 kb
Host	smart-1bd69259-f6e0-467c-ae6c-a722ef57f274
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355615285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all .3355615285
Directory	/workspace/40.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.adc_ctrl_alert_test.2476834560
Short name	T534
Test name
Test status
Simulation time	479812701 ps
CPU time	0.83 seconds
Started	Feb 07 01:28:52 PM PST 24
Finished	Feb 07 01:28:53 PM PST 24
Peak memory	201228 kb
Host	smart-d93c5934-1759-4ccf-b62d-00576bd8b392
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476834560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2476834560
Directory	/workspace/41.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.adc_ctrl_clock_gating.3899189427
Short name	T85
Test name
Test status
Simulation time	489969477286 ps
CPU time	113.65 seconds
Started	Feb 07 01:28:30 PM PST 24
Finished	Feb 07 01:30:24 PM PST 24
Peak memory	201620 kb
Host	smart-0e7694bd-ae0b-4925-a759-8707b8bbe8d7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899189427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat ing.3899189427
Directory	/workspace/41.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_both.1097438224
Short name	T10
Test name
Test status
Simulation time	326874831617 ps
CPU time	838.51 seconds
Started	Feb 07 01:28:30 PM PST 24
Finished	Feb 07 01:42:30 PM PST 24
Peak memory	201624 kb
Host	smart-6f43e57f-b62d-4ea0-a4da-99981cc6d032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097438224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1097438224
Directory	/workspace/41.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_interrupt.1733042329
Short name	T656
Test name
Test status
Simulation time	164655741472 ps
CPU time	352.88 seconds
Started	Feb 07 01:28:29 PM PST 24
Finished	Feb 07 01:34:23 PM PST 24
Peak memory	201556 kb
Host	smart-c11c4838-b32d-4c8b-84b9-6ac7e01a24a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733042329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1733042329
Directory	/workspace/41.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4080206553
Short name	T661
Test name
Test status
Simulation time	484926472693 ps
CPU time	383.11 seconds
Started	Feb 07 01:28:32 PM PST 24
Finished	Feb 07 01:34:56 PM PST 24
Peak memory	201556 kb
Host	smart-c7201f25-32e3-4b58-900d-1e60421ca36d
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080206553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru pt_fixed.4080206553
Directory	/workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_polled.1101362823
Short name	T246
Test name
Test status
Simulation time	333160639613 ps
CPU time	397.4 seconds
Started	Feb 07 01:28:19 PM PST 24
Finished	Feb 07 01:34:59 PM PST 24
Peak memory	201572 kb
Host	smart-976495e9-37ae-44af-ba50-3cf6a116d466
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101362823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1101362823
Directory	/workspace/41.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2551010490
Short name	T495
Test name
Test status
Simulation time	159490030556 ps
CPU time	38.05 seconds
Started	Feb 07 01:28:21 PM PST 24
Finished	Feb 07 01:29:05 PM PST 24
Peak memory	201664 kb
Host	smart-4c6d3efe-97ce-4275-80f2-5982c1c5a5ea
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551010490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix ed.2551010490
Directory	/workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_wakeup.4110046888
Short name	T251
Test name
Test status
Simulation time	493703652283 ps
CPU time	158.19 seconds
Started	Feb 07 01:28:32 PM PST 24
Finished	Feb 07 01:31:11 PM PST 24
Peak memory	201556 kb
Host	smart-0a3fa20c-ef46-4b43-829c-f3cad5214f23
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110046888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters _wakeup.4110046888
Directory	/workspace/41.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.950999394
Short name	T697
Test name
Test status
Simulation time	162434988332 ps
CPU time	97.89 seconds
Started	Feb 07 01:28:30 PM PST 24
Finished	Feb 07 01:30:09 PM PST 24
Peak memory	201612 kb
Host	smart-dd619f2e-3936-4edd-806c-ea0104daa36a
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950999394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. adc_ctrl_filters_wakeup_fixed.950999394
Directory	/workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_fsm_reset.2788454822
Short name	T497
Test name
Test status
Simulation time	90623578537 ps
CPU time	324.87 seconds
Started	Feb 07 01:28:31 PM PST 24
Finished	Feb 07 01:33:56 PM PST 24
Peak memory	201872 kb
Host	smart-f885973b-a54d-49f3-a100-11b2d2f7bc77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2788454822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2788454822
Directory	/workspace/41.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/41.adc_ctrl_lowpower_counter.1934788423
Short name	T517
Test name
Test status
Simulation time	28735814401 ps
CPU time	44.69 seconds
Started	Feb 07 01:28:29 PM PST 24
Finished	Feb 07 01:29:15 PM PST 24
Peak memory	201324 kb
Host	smart-dfe706e5-4295-4fc8-89a2-b5ab6145ade0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934788423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1934788423
Directory	/workspace/41.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/41.adc_ctrl_poweron_counter.3823144929
Short name	T784
Test name
Test status
Simulation time	3921746429 ps
CPU time	2.85 seconds
Started	Feb 07 01:28:32 PM PST 24
Finished	Feb 07 01:28:35 PM PST 24
Peak memory	201380 kb
Host	smart-f0beb4b9-e280-48be-9013-5f9df0b20e61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823144929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3823144929
Directory	/workspace/41.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/41.adc_ctrl_smoke.3687379985
Short name	T567
Test name
Test status
Simulation time	5727975150 ps
CPU time	1.51 seconds
Started	Feb 07 01:28:20 PM PST 24
Finished	Feb 07 01:28:28 PM PST 24
Peak memory	201356 kb
Host	smart-8a026a83-a0d1-4951-ae3a-63b8f7f4e9ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687379985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3687379985
Directory	/workspace/41.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.adc_ctrl_stress_all.2104679340
Short name	T290
Test name
Test status
Simulation time	280634226262 ps
CPU time	536.77 seconds
Started	Feb 07 01:28:29 PM PST 24
Finished	Feb 07 01:37:26 PM PST 24
Peak memory	218148 kb
Host	smart-f84314ce-8cc1-4805-91e1-184e02e8e4e2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104679340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all .2104679340
Directory	/workspace/41.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1210104779
Short name	T666
Test name
Test status
Simulation time	12683909301 ps
CPU time	33.39 seconds
Started	Feb 07 01:28:33 PM PST 24
Finished	Feb 07 01:29:07 PM PST 24
Peak memory	209948 kb
Host	smart-5ecccc66-a9af-403c-b2c0-835cbd5c4807
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210104779 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1210104779
Directory	/workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.adc_ctrl_alert_test.3864954502
Short name	T714
Test name
Test status
Simulation time	349158744 ps
CPU time	1.44 seconds
Started	Feb 07 01:29:04 PM PST 24
Finished	Feb 07 01:29:06 PM PST 24
Peak memory	201252 kb
Host	smart-4fee0e2f-cbe9-4758-a724-e1ca623a5a54
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864954502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3864954502
Directory	/workspace/42.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.adc_ctrl_clock_gating.164531045
Short name	T228
Test name
Test status
Simulation time	169794540928 ps
CPU time	106.83 seconds
Started	Feb 07 01:28:54 PM PST 24
Finished	Feb 07 01:30:41 PM PST 24
Peak memory	201580 kb
Host	smart-11f9b5c5-6beb-4d09-a6bd-88d430eef71b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164531045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati ng.164531045
Directory	/workspace/42.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_both.2420831337
Short name	T753
Test name
Test status
Simulation time	170872589231 ps
CPU time	424.7 seconds
Started	Feb 07 01:28:51 PM PST 24
Finished	Feb 07 01:35:56 PM PST 24
Peak memory	201628 kb
Host	smart-5a3be3c6-0e1e-4ca7-94ea-ea0f3cf08375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2420831337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2420831337
Directory	/workspace/42.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_interrupt.1589966311
Short name	T490
Test name
Test status
Simulation time	163356214601 ps
CPU time	191.49 seconds
Started	Feb 07 01:28:58 PM PST 24
Finished	Feb 07 01:32:10 PM PST 24
Peak memory	201548 kb
Host	smart-a9f91af4-c268-42a0-9cdb-07f0d392acab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589966311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1589966311
Directory	/workspace/42.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3011254294
Short name	T563
Test name
Test status
Simulation time	328244882385 ps
CPU time	688.5 seconds
Started	Feb 07 01:28:51 PM PST 24
Finished	Feb 07 01:40:20 PM PST 24
Peak memory	201504 kb
Host	smart-9b410e3a-321f-437d-8157-5d2f12d4bb41
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011254294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru pt_fixed.3011254294
Directory	/workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_polled.3284108888
Short name	T864
Test name
Test status
Simulation time	165017996003 ps
CPU time	364.12 seconds
Started	Feb 07 01:28:53 PM PST 24
Finished	Feb 07 01:34:58 PM PST 24
Peak memory	201608 kb
Host	smart-9aaa9d01-9d36-44ff-9783-8060209c4745
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3284108888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3284108888
Directory	/workspace/42.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3989586887
Short name	T52
Test name
Test status
Simulation time	492196365933 ps
CPU time	488.08 seconds
Started	Feb 07 01:28:59 PM PST 24
Finished	Feb 07 01:37:08 PM PST 24
Peak memory	201544 kb
Host	smart-c6d60854-cc58-4a38-a3f0-e78dce195dee
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989586887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix ed.3989586887
Directory	/workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_wakeup.480084702
Short name	T208
Test name
Test status
Simulation time	165588111793 ps
CPU time	101.47 seconds
Started	Feb 07 01:28:54 PM PST 24
Finished	Feb 07 01:30:36 PM PST 24
Peak memory	201560 kb
Host	smart-21457dfa-bf4e-4aa4-89af-d618dc36ce16
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480084702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_ wakeup.480084702
Directory	/workspace/42.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1734250024
Short name	T537
Test name
Test status
Simulation time	503184614119 ps
CPU time	319.09 seconds
Started	Feb 07 01:28:54 PM PST 24
Finished	Feb 07 01:34:13 PM PST 24
Peak memory	201548 kb
Host	smart-9ded107b-b013-46c3-8693-1e6afdeb62a9
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734250024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .adc_ctrl_filters_wakeup_fixed.1734250024
Directory	/workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_fsm_reset.3617741473
Short name	T524
Test name
Test status
Simulation time	68627744534 ps
CPU time	385.05 seconds
Started	Feb 07 01:28:59 PM PST 24
Finished	Feb 07 01:35:25 PM PST 24
Peak memory	201988 kb
Host	smart-8457d5e0-8f9f-49a3-990c-d2e4e9cbc8ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617741473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3617741473
Directory	/workspace/42.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/42.adc_ctrl_lowpower_counter.1760252567
Short name	T391
Test name
Test status
Simulation time	35866093254 ps
CPU time	37.6 seconds
Started	Feb 07 01:29:02 PM PST 24
Finished	Feb 07 01:29:41 PM PST 24
Peak memory	201456 kb
Host	smart-3e3b5c67-8f1e-40ed-b979-e7d2ecf14369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760252567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1760252567
Directory	/workspace/42.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/42.adc_ctrl_poweron_counter.1570568985
Short name	T711
Test name
Test status
Simulation time	3100390511 ps
CPU time	1.65 seconds
Started	Feb 07 01:28:54 PM PST 24
Finished	Feb 07 01:28:57 PM PST 24
Peak memory	201424 kb
Host	smart-5e3952fa-2e63-4011-9d98-72dd4d973e05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570568985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1570568985
Directory	/workspace/42.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/42.adc_ctrl_smoke.1360550302
Short name	T79
Test name
Test status
Simulation time	5840114941 ps
CPU time	4.34 seconds
Started	Feb 07 01:29:03 PM PST 24
Finished	Feb 07 01:29:08 PM PST 24
Peak memory	201388 kb
Host	smart-5dbe3be6-c735-41a9-9acb-d8e3d0bab06e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360550302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1360550302
Directory	/workspace/42.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2396908886
Short name	T710
Test name
Test status
Simulation time	66346849059 ps
CPU time	242.89 seconds
Started	Feb 07 01:29:01 PM PST 24
Finished	Feb 07 01:33:04 PM PST 24
Peak memory	211316 kb
Host	smart-f5e5def5-3f46-4620-a696-fc7e4493c806
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396908886 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2396908886
Directory	/workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.adc_ctrl_alert_test.2801057928
Short name	T789
Test name
Test status
Simulation time	504994548 ps
CPU time	0.9 seconds
Started	Feb 07 01:29:15 PM PST 24
Finished	Feb 07 01:29:16 PM PST 24
Peak memory	201192 kb
Host	smart-4fa42c40-86b4-4f36-a95b-e89c5d094b26
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801057928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2801057928
Directory	/workspace/43.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.adc_ctrl_clock_gating.2964229073
Short name	T279
Test name
Test status
Simulation time	162970219144 ps
CPU time	62.39 seconds
Started	Feb 07 01:29:13 PM PST 24
Finished	Feb 07 01:30:16 PM PST 24
Peak memory	201508 kb
Host	smart-7dda932e-d998-4e77-b8c6-5fb5cb1cbbf0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964229073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat ing.2964229073
Directory	/workspace/43.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_both.3638036953
Short name	T90
Test name
Test status
Simulation time	163759826597 ps
CPU time	159.89 seconds
Started	Feb 07 01:29:15 PM PST 24
Finished	Feb 07 01:31:56 PM PST 24
Peak memory	201620 kb
Host	smart-9a6d65dc-9bb6-46f4-8c7c-c0e25e0a7aa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638036953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3638036953
Directory	/workspace/43.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2400000382
Short name	T763
Test name
Test status
Simulation time	326621686396 ps
CPU time	329.28 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:34:44 PM PST 24
Peak memory	201608 kb
Host	smart-c013e223-0a3d-4ac9-bc7d-cc11020e5031
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400000382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru pt_fixed.2400000382
Directory	/workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_polled.2841200842
Short name	T749
Test name
Test status
Simulation time	330563466511 ps
CPU time	771.45 seconds
Started	Feb 07 01:29:03 PM PST 24
Finished	Feb 07 01:41:55 PM PST 24
Peak memory	201668 kb
Host	smart-68a16e9f-7261-42c2-b2d5-1936ec9f5b4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841200842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2841200842
Directory	/workspace/43.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1868286856
Short name	T841
Test name
Test status
Simulation time	332692341970 ps
CPU time	76.89 seconds
Started	Feb 07 01:29:03 PM PST 24
Finished	Feb 07 01:30:20 PM PST 24
Peak memory	201608 kb
Host	smart-edc03605-c4a0-4533-89af-50279f6dc007
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868286856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix ed.1868286856
Directory	/workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_wakeup.22239941
Short name	T764
Test name
Test status
Simulation time	330601193877 ps
CPU time	85.89 seconds
Started	Feb 07 01:28:59 PM PST 24
Finished	Feb 07 01:30:25 PM PST 24
Peak memory	201572 kb
Host	smart-886c94f5-0011-41d9-80d6-4dc812077a89
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_ wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_w akeup.22239941
Directory	/workspace/43.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3461430942
Short name	T54
Test name
Test status
Simulation time	170064030860 ps
CPU time	416.94 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:36:11 PM PST 24
Peak memory	201588 kb
Host	smart-3ae6c2fb-b937-4e70-a1aa-e24b108e8c02
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461430942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43 .adc_ctrl_filters_wakeup_fixed.3461430942
Directory	/workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/43.adc_ctrl_fsm_reset.4070074119
Short name	T183
Test name
Test status
Simulation time	79758996571 ps
CPU time	352.15 seconds
Started	Feb 07 01:29:13 PM PST 24
Finished	Feb 07 01:35:06 PM PST 24
Peak memory	201892 kb
Host	smart-0b6df5a5-46e8-46d6-8a0a-5313e75fa097
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070074119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.4070074119
Directory	/workspace/43.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/43.adc_ctrl_lowpower_counter.2835889325
Short name	T498
Test name
Test status
Simulation time	43454264533 ps
CPU time	102.26 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:30:57 PM PST 24
Peak memory	201380 kb
Host	smart-4b55ae8d-26ff-4d9f-9606-12f9b61a0161
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2835889325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2835889325
Directory	/workspace/43.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/43.adc_ctrl_poweron_counter.353585629
Short name	T807
Test name
Test status
Simulation time	4467207196 ps
CPU time	10.19 seconds
Started	Feb 07 01:29:11 PM PST 24
Finished	Feb 07 01:29:22 PM PST 24
Peak memory	201280 kb
Host	smart-c6f7c16e-e0fe-4b25-adfd-372551190e12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353585629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.353585629
Directory	/workspace/43.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/43.adc_ctrl_smoke.871260220
Short name	T554
Test name
Test status
Simulation time	5585992010 ps
CPU time	12.71 seconds
Started	Feb 07 01:29:13 PM PST 24
Finished	Feb 07 01:29:27 PM PST 24
Peak memory	201388 kb
Host	smart-b53babf4-f5c1-4577-a0e0-17de723933a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=871260220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.871260220
Directory	/workspace/43.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.adc_ctrl_stress_all.3227857857
Short name	T620
Test name
Test status
Simulation time	362184680398 ps
CPU time	418.06 seconds
Started	Feb 07 01:29:17 PM PST 24
Finished	Feb 07 01:36:16 PM PST 24
Peak memory	201644 kb
Host	smart-4dd55e4c-1449-478e-99fd-891ce6407e22
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227857857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all .3227857857
Directory	/workspace/43.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1178101537
Short name	T816
Test name
Test status
Simulation time	48414754484 ps
CPU time	93.7 seconds
Started	Feb 07 01:29:15 PM PST 24
Finished	Feb 07 01:30:49 PM PST 24
Peak memory	209956 kb
Host	smart-423a2077-2a58-4639-b548-d296dfb2f0b8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178101537 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1178101537
Directory	/workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.adc_ctrl_alert_test.3969560311
Short name	T765
Test name
Test status
Simulation time	380286605 ps
CPU time	1.4 seconds
Started	Feb 07 01:29:15 PM PST 24
Finished	Feb 07 01:29:17 PM PST 24
Peak memory	201248 kb
Host	smart-4cd0ae13-19e6-4c6a-9179-cb99522a792c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969560311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3969560311
Directory	/workspace/44.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3152218188
Short name	T798
Test name
Test status
Simulation time	166634560118 ps
CPU time	335.68 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:34:50 PM PST 24
Peak memory	201424 kb
Host	smart-ddbb561c-d9ee-4b89-b679-33eed694616a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152218188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru pt_fixed.3152218188
Directory	/workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_polled.2402734646
Short name	T511
Test name
Test status
Simulation time	163276311234 ps
CPU time	381.55 seconds
Started	Feb 07 01:29:16 PM PST 24
Finished	Feb 07 01:35:38 PM PST 24
Peak memory	201552 kb
Host	smart-81cb4ed9-ddcb-42bc-9e5c-16b3a4c7fa7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402734646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2402734646
Directory	/workspace/44.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3636405005
Short name	T698
Test name
Test status
Simulation time	493249983273 ps
CPU time	271.86 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:33:47 PM PST 24
Peak memory	201576 kb
Host	smart-a4a87a7a-4878-425b-b47a-b570c9324b1e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636405005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix ed.3636405005
Directory	/workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_wakeup.1569917059
Short name	T597
Test name
Test status
Simulation time	167435322447 ps
CPU time	396.83 seconds
Started	Feb 07 01:29:11 PM PST 24
Finished	Feb 07 01:35:49 PM PST 24
Peak memory	201668 kb
Host	smart-420ca2bc-9123-459b-b4a9-2a18f73a7677
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569917059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters _wakeup.1569917059
Directory	/workspace/44.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1005214161
Short name	T796
Test name
Test status
Simulation time	332847734362 ps
CPU time	809.82 seconds
Started	Feb 07 01:29:16 PM PST 24
Finished	Feb 07 01:42:46 PM PST 24
Peak memory	201524 kb
Host	smart-77661555-7d4b-46c6-8a3e-e76b2a313400
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005214161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .adc_ctrl_filters_wakeup_fixed.1005214161
Directory	/workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_fsm_reset.3730193741
Short name	T167
Test name
Test status
Simulation time	75489645878 ps
CPU time	237.48 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:33:12 PM PST 24
Peak memory	201952 kb
Host	smart-2c9da1d4-5eba-43bd-947a-dd52213e2036
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730193741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3730193741
Directory	/workspace/44.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/44.adc_ctrl_lowpower_counter.1516975717
Short name	T641
Test name
Test status
Simulation time	39609313618 ps
CPU time	87.21 seconds
Started	Feb 07 01:29:18 PM PST 24
Finished	Feb 07 01:30:46 PM PST 24
Peak memory	201376 kb
Host	smart-ea8cf58f-d50d-42fc-a433-bc2c07be690f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516975717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1516975717
Directory	/workspace/44.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/44.adc_ctrl_poweron_counter.3398076344
Short name	T817
Test name
Test status
Simulation time	3663687303 ps
CPU time	5.04 seconds
Started	Feb 07 01:29:13 PM PST 24
Finished	Feb 07 01:29:19 PM PST 24
Peak memory	201368 kb
Host	smart-a7208848-94bc-40c0-bba1-e23340a83496
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398076344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3398076344
Directory	/workspace/44.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/44.adc_ctrl_smoke.2058912214
Short name	T694
Test name
Test status
Simulation time	5973086868 ps
CPU time	8.76 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:29:24 PM PST 24
Peak memory	201372 kb
Host	smart-db5c1ce9-d7d1-471e-ad0a-31ccf9432bed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058912214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2058912214
Directory	/workspace/44.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.adc_ctrl_stress_all.194626078
Short name	T141
Test name
Test status
Simulation time	623218436006 ps
CPU time	758.09 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:41:53 PM PST 24
Peak memory	210048 kb
Host	smart-76e6a54e-d29c-45be-b559-a2437195e355
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194626078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all. 194626078
Directory	/workspace/44.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1805183434
Short name	T307
Test name
Test status
Simulation time	867836561466 ps
CPU time	778.91 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:42:14 PM PST 24
Peak memory	210216 kb
Host	smart-bb217c45-d5da-4387-a444-d5cf78e11045
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805183434 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1805183434
Directory	/workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.adc_ctrl_alert_test.1679672679
Short name	T443
Test name
Test status
Simulation time	377582198 ps
CPU time	1.44 seconds
Started	Feb 07 01:29:25 PM PST 24
Finished	Feb 07 01:29:27 PM PST 24
Peak memory	201224 kb
Host	smart-133c48e6-6412-4509-be3c-adedd2e81dfb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679672679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1679672679
Directory	/workspace/45.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_both.1626442973
Short name	T152
Test name
Test status
Simulation time	323454424997 ps
CPU time	114.47 seconds
Started	Feb 07 01:29:18 PM PST 24
Finished	Feb 07 01:31:13 PM PST 24
Peak memory	201656 kb
Host	smart-fb2a55ef-d73a-4ea9-b691-e4bc28fed768
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626442973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1626442973
Directory	/workspace/45.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_interrupt.1184866672
Short name	T261
Test name
Test status
Simulation time	166264616235 ps
CPU time	186.81 seconds
Started	Feb 07 01:29:17 PM PST 24
Finished	Feb 07 01:32:24 PM PST 24
Peak memory	201600 kb
Host	smart-f8c6d4c0-ef41-45bb-912c-bf3d206e7c8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184866672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1184866672
Directory	/workspace/45.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.223922368
Short name	T400
Test name
Test status
Simulation time	325627180371 ps
CPU time	786.3 seconds
Started	Feb 07 01:29:16 PM PST 24
Finished	Feb 07 01:42:23 PM PST 24
Peak memory	201544 kb
Host	smart-967cb6a1-878b-45e1-bc67-01bec8ff3338
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=223922368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup t_fixed.223922368
Directory	/workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_polled.3765998190
Short name	T128
Test name
Test status
Simulation time	332608484581 ps
CPU time	115.43 seconds
Started	Feb 07 01:29:18 PM PST 24
Finished	Feb 07 01:31:13 PM PST 24
Peak memory	201616 kb
Host	smart-f4336307-9626-4de2-a2f1-513b4a885b1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765998190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3765998190
Directory	/workspace/45.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.933305366
Short name	T614
Test name
Test status
Simulation time	160842366019 ps
CPU time	69.38 seconds
Started	Feb 07 01:29:17 PM PST 24
Finished	Feb 07 01:30:27 PM PST 24
Peak memory	201608 kb
Host	smart-160870ad-ae0a-43da-9eb0-a1fffd97269e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=933305366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe d.933305366
Directory	/workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_wakeup.1311488763
Short name	T278
Test name
Test status
Simulation time	504534062030 ps
CPU time	242.34 seconds
Started	Feb 07 01:29:14 PM PST 24
Finished	Feb 07 01:33:17 PM PST 24
Peak memory	201616 kb
Host	smart-8dbabbbf-358b-4a14-b5a0-1b0aada7d74f
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311488763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters _wakeup.1311488763
Directory	/workspace/45.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1347433206
Short name	T19
Test name
Test status
Simulation time	162787106764 ps
CPU time	185.76 seconds
Started	Feb 07 01:29:19 PM PST 24
Finished	Feb 07 01:32:25 PM PST 24
Peak memory	201572 kb
Host	smart-9acf6aa2-d4f5-46a9-94d9-eb9b10cfa055
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347433206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .adc_ctrl_filters_wakeup_fixed.1347433206
Directory	/workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_lowpower_counter.1854686800
Short name	T724
Test name
Test status
Simulation time	26689935621 ps
CPU time	60.93 seconds
Started	Feb 07 01:29:26 PM PST 24
Finished	Feb 07 01:30:27 PM PST 24
Peak memory	201420 kb
Host	smart-5fd1d98c-d385-42fd-b625-d4a637011d7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854686800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1854686800
Directory	/workspace/45.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/45.adc_ctrl_poweron_counter.3511681899
Short name	T418
Test name
Test status
Simulation time	3601564998 ps
CPU time	3.34 seconds
Started	Feb 07 01:29:17 PM PST 24
Finished	Feb 07 01:29:21 PM PST 24
Peak memory	201388 kb
Host	smart-7ba3599c-4269-4a67-b0b0-ce6b3a0cb898
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3511681899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3511681899
Directory	/workspace/45.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/45.adc_ctrl_smoke.4262745505
Short name	T516
Test name
Test status
Simulation time	5843264262 ps
CPU time	7.94 seconds
Started	Feb 07 01:29:15 PM PST 24
Finished	Feb 07 01:29:23 PM PST 24
Peak memory	201376 kb
Host	smart-208adda6-3530-43af-929d-5c3b37f6ee2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262745505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4262745505
Directory	/workspace/45.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.adc_ctrl_stress_all.2167153394
Short name	T97
Test name
Test status
Simulation time	436949933461 ps
CPU time	1288.49 seconds
Started	Feb 07 01:29:26 PM PST 24
Finished	Feb 07 01:50:56 PM PST 24
Peak memory	210104 kb
Host	smart-e386e8b3-419f-4b7a-aeb9-643fb3b148ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167153394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all .2167153394
Directory	/workspace/45.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.adc_ctrl_alert_test.2051465967
Short name	T36
Test name
Test status
Simulation time	481717877 ps
CPU time	0.82 seconds
Started	Feb 07 01:29:37 PM PST 24
Finished	Feb 07 01:29:38 PM PST 24
Peak memory	201292 kb
Host	smart-e147e122-d8d3-40eb-9444-46cc90466169
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051465967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2051465967
Directory	/workspace/46.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.adc_ctrl_clock_gating.138754565
Short name	T313
Test name
Test status
Simulation time	488537600788 ps
CPU time	528.55 seconds
Started	Feb 07 01:29:36 PM PST 24
Finished	Feb 07 01:38:25 PM PST 24
Peak memory	201596 kb
Host	smart-4a37ab2e-3114-44b1-9527-4d092b370c26
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138754565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati ng.138754565
Directory	/workspace/46.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_both.3764943710
Short name	T312
Test name
Test status
Simulation time	325216229382 ps
CPU time	276.81 seconds
Started	Feb 07 01:29:39 PM PST 24
Finished	Feb 07 01:34:16 PM PST 24
Peak memory	201588 kb
Host	smart-8476747a-eba3-4364-8a1e-bb850e71b820
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764943710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3764943710
Directory	/workspace/46.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_interrupt.4148574663
Short name	T311
Test name
Test status
Simulation time	161047893985 ps
CPU time	389.08 seconds
Started	Feb 07 01:29:36 PM PST 24
Finished	Feb 07 01:36:06 PM PST 24
Peak memory	201636 kb
Host	smart-d2316f04-f6cf-44e0-ba4d-94f368ca1191
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148574663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4148574663
Directory	/workspace/46.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.315574487
Short name	T686
Test name
Test status
Simulation time	322720983547 ps
CPU time	820.95 seconds
Started	Feb 07 01:29:36 PM PST 24
Finished	Feb 07 01:43:18 PM PST 24
Peak memory	201568 kb
Host	smart-b1965fe2-a0db-4acd-9d46-934549a0d020
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=315574487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup t_fixed.315574487
Directory	/workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_polled.2005945803
Short name	T654
Test name
Test status
Simulation time	502207702515 ps
CPU time	1222.96 seconds
Started	Feb 07 01:29:36 PM PST 24
Finished	Feb 07 01:50:00 PM PST 24
Peak memory	201580 kb
Host	smart-14f4dff9-e328-4265-a22f-50eb3c4abf38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005945803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2005945803
Directory	/workspace/46.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2606831808
Short name	T585
Test name
Test status
Simulation time	496769164384 ps
CPU time	194.25 seconds
Started	Feb 07 01:29:37 PM PST 24
Finished	Feb 07 01:32:51 PM PST 24
Peak memory	201576 kb
Host	smart-c6edc387-cb58-44c7-826a-7dd1b5e1886d
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606831808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix ed.2606831808
Directory	/workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_wakeup.3459311017
Short name	T688
Test name
Test status
Simulation time	164142930510 ps
CPU time	363.78 seconds
Started	Feb 07 01:29:35 PM PST 24
Finished	Feb 07 01:35:39 PM PST 24
Peak memory	201652 kb
Host	smart-100e52f7-2aa2-4660-b5b2-eb4ad9d02fb4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459311017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters _wakeup.3459311017
Directory	/workspace/46.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.48025633
Short name	T639
Test name
Test status
Simulation time	501115270052 ps
CPU time	570.17 seconds
Started	Feb 07 01:29:37 PM PST 24
Finished	Feb 07 01:39:07 PM PST 24
Peak memory	201544 kb
Host	smart-364fe0a3-f2ce-41d6-9e1b-7e3cd684632d
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48025633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ= adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.a dc_ctrl_filters_wakeup_fixed.48025633
Directory	/workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_fsm_reset.1324442108
Short name	T840
Test name
Test status
Simulation time	95617141607 ps
CPU time	399.49 seconds
Started	Feb 07 01:29:39 PM PST 24
Finished	Feb 07 01:36:19 PM PST 24
Peak memory	201888 kb
Host	smart-5c3453f3-b3e2-4521-b850-1cb975b52c40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324442108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1324442108
Directory	/workspace/46.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/46.adc_ctrl_lowpower_counter.2041093150
Short name	T477
Test name
Test status
Simulation time	42323273255 ps
CPU time	68.66 seconds
Started	Feb 07 01:29:35 PM PST 24
Finished	Feb 07 01:30:44 PM PST 24
Peak memory	201432 kb
Host	smart-fabb487f-87f8-4171-8f4c-ccf515bce0ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041093150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2041093150
Directory	/workspace/46.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/46.adc_ctrl_poweron_counter.1294077866
Short name	T616
Test name
Test status
Simulation time	4057807880 ps
CPU time	9.85 seconds
Started	Feb 07 01:29:35 PM PST 24
Finished	Feb 07 01:29:46 PM PST 24
Peak memory	201420 kb
Host	smart-92cca4c4-0ae0-4bf6-9ce2-3a8e93f3278f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294077866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1294077866
Directory	/workspace/46.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/46.adc_ctrl_smoke.3878520777
Short name	T788
Test name
Test status
Simulation time	5705107816 ps
CPU time	2.64 seconds
Started	Feb 07 01:29:36 PM PST 24
Finished	Feb 07 01:29:39 PM PST 24
Peak memory	201344 kb
Host	smart-16532c5a-f77e-4191-9d90-4d00c53bc191
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3878520777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3878520777
Directory	/workspace/46.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.adc_ctrl_stress_all.152776419
Short name	T187
Test name
Test status
Simulation time	662882707172 ps
CPU time	385.73 seconds
Started	Feb 07 01:29:36 PM PST 24
Finished	Feb 07 01:36:02 PM PST 24
Peak memory	201640 kb
Host	smart-87906622-d40f-47b0-96a1-c8216f450884
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152776419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all. 152776419
Directory	/workspace/46.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.23054419
Short name	T310
Test name
Test status
Simulation time	75533178328 ps
CPU time	37.84 seconds
Started	Feb 07 01:29:39 PM PST 24
Finished	Feb 07 01:30:18 PM PST 24
Peak memory	201656 kb
Host	smart-bf4fa5dc-e629-415f-8e95-96c43583ae32
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23054419 -assert nopos tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.23054419
Directory	/workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.adc_ctrl_alert_test.2073519650
Short name	T832
Test name
Test status
Simulation time	305214921 ps
CPU time	0.81 seconds
Started	Feb 07 01:29:53 PM PST 24
Finished	Feb 07 01:29:55 PM PST 24
Peak memory	201276 kb
Host	smart-3187cfeb-dd07-46da-94ee-fcdb82f1c973
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073519650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2073519650
Directory	/workspace/47.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.adc_ctrl_clock_gating.2967545555
Short name	T111
Test name
Test status
Simulation time	325539265983 ps
CPU time	746.22 seconds
Started	Feb 07 01:29:39 PM PST 24
Finished	Feb 07 01:42:06 PM PST 24
Peak memory	201576 kb
Host	smart-18c9e84b-f006-44d1-aa65-e741de744dcd
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967545555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat ing.2967545555
Directory	/workspace/47.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_both.1999622911
Short name	T201
Test name
Test status
Simulation time	161044260621 ps
CPU time	249.11 seconds
Started	Feb 07 01:29:45 PM PST 24
Finished	Feb 07 01:33:55 PM PST 24
Peak memory	201544 kb
Host	smart-51ca4fc6-e07a-4173-b0df-7bcf470ac0e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999622911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1999622911
Directory	/workspace/47.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_interrupt.2163613151
Short name	T684
Test name
Test status
Simulation time	328597210272 ps
CPU time	794.7 seconds
Started	Feb 07 01:29:40 PM PST 24
Finished	Feb 07 01:42:55 PM PST 24
Peak memory	201656 kb
Host	smart-8e67e91b-1db9-48eb-a2fb-8975bd615c7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163613151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2163613151
Directory	/workspace/47.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3332113835
Short name	T648
Test name
Test status
Simulation time	335263971291 ps
CPU time	773.4 seconds
Started	Feb 07 01:29:41 PM PST 24
Finished	Feb 07 01:42:35 PM PST 24
Peak memory	201632 kb
Host	smart-dd8ea9d1-fc1f-44d6-b542-3dafbcbfa174
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332113835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru pt_fixed.3332113835
Directory	/workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_polled.3937109397
Short name	T523
Test name
Test status
Simulation time	323936983723 ps
CPU time	150.04 seconds
Started	Feb 07 01:29:41 PM PST 24
Finished	Feb 07 01:32:11 PM PST 24
Peak memory	201700 kb
Host	smart-69dea3a4-eaf5-4e3d-a248-d247952bc834
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937109397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3937109397
Directory	/workspace/47.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.278262223
Short name	T527
Test name
Test status
Simulation time	164191848555 ps
CPU time	379.68 seconds
Started	Feb 07 01:29:36 PM PST 24
Finished	Feb 07 01:35:56 PM PST 24
Peak memory	201652 kb
Host	smart-0f33c95a-9258-4879-8a81-fec1b134001c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=278262223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe d.278262223
Directory	/workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_wakeup.892808526
Short name	T153
Test name
Test status
Simulation time	334090119067 ps
CPU time	286.19 seconds
Started	Feb 07 01:29:41 PM PST 24
Finished	Feb 07 01:34:28 PM PST 24
Peak memory	201652 kb
Host	smart-9f31d7ed-c860-4de2-93e8-fec9b2be6682
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892808526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_ wakeup.892808526
Directory	/workspace/47.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2692131643
Short name	T758
Test name
Test status
Simulation time	486113451759 ps
CPU time	1077.26 seconds
Started	Feb 07 01:29:37 PM PST 24
Finished	Feb 07 01:47:34 PM PST 24
Peak memory	201604 kb
Host	smart-af719996-bb25-40c8-be87-4cc13706c4ee
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692131643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .adc_ctrl_filters_wakeup_fixed.2692131643
Directory	/workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_fsm_reset.2852764202
Short name	T583
Test name
Test status
Simulation time	120913983478 ps
CPU time	409.67 seconds
Started	Feb 07 01:29:49 PM PST 24
Finished	Feb 07 01:36:39 PM PST 24
Peak memory	201840 kb
Host	smart-8e15d71e-a66c-4707-950f-146c194c3892
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852764202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2852764202
Directory	/workspace/47.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/47.adc_ctrl_lowpower_counter.3946498238
Short name	T399
Test name
Test status
Simulation time	38371868083 ps
CPU time	21.12 seconds
Started	Feb 07 01:29:51 PM PST 24
Finished	Feb 07 01:30:13 PM PST 24
Peak memory	201412 kb
Host	smart-0599fdce-e07f-4827-a4b3-fe9896c63de1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946498238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3946498238
Directory	/workspace/47.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/47.adc_ctrl_poweron_counter.1180572142
Short name	T18
Test name
Test status
Simulation time	4710296866 ps
CPU time	6.27 seconds
Started	Feb 07 01:29:44 PM PST 24
Finished	Feb 07 01:29:51 PM PST 24
Peak memory	201376 kb
Host	smart-2042a376-eff2-4027-8685-496eed1d5ef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180572142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1180572142
Directory	/workspace/47.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/47.adc_ctrl_smoke.3656379824
Short name	T137
Test name
Test status
Simulation time	5936307463 ps
CPU time	4.06 seconds
Started	Feb 07 01:29:38 PM PST 24
Finished	Feb 07 01:29:43 PM PST 24
Peak memory	201320 kb
Host	smart-6a621193-d47a-46af-b088-e59834b6b8a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656379824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3656379824
Directory	/workspace/47.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.adc_ctrl_stress_all.3212072510
Short name	T284
Test name
Test status
Simulation time	169467242879 ps
CPU time	126.86 seconds
Started	Feb 07 01:29:47 PM PST 24
Finished	Feb 07 01:31:54 PM PST 24
Peak memory	201552 kb
Host	smart-028e9bc5-e189-4401-b476-024cc72cb0f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212072510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all .3212072510
Directory	/workspace/47.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2046946843
Short name	T139
Test name
Test status
Simulation time	151163294292 ps
CPU time	169.83 seconds
Started	Feb 07 01:29:48 PM PST 24
Finished	Feb 07 01:32:39 PM PST 24
Peak memory	217984 kb
Host	smart-147cc43b-0018-4251-82f0-8668d8af1251
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046946843 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2046946843
Directory	/workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.adc_ctrl_alert_test.2122371896
Short name	T708
Test name
Test status
Simulation time	420288284 ps
CPU time	1.62 seconds
Started	Feb 07 01:30:00 PM PST 24
Finished	Feb 07 01:30:02 PM PST 24
Peak memory	201208 kb
Host	smart-ca0ba13c-c4c8-412c-9f9e-647656ea315e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122371896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2122371896
Directory	/workspace/48.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.adc_ctrl_clock_gating.1258963740
Short name	T818
Test name
Test status
Simulation time	164728521987 ps
CPU time	380.82 seconds
Started	Feb 07 01:29:56 PM PST 24
Finished	Feb 07 01:36:18 PM PST 24
Peak memory	201728 kb
Host	smart-4edd28b0-00f4-46e9-a9af-7c3d8d57f178
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258963740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat ing.1258963740
Directory	/workspace/48.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_both.3499398851
Short name	T247
Test name
Test status
Simulation time	492549535840 ps
CPU time	303.13 seconds
Started	Feb 07 01:29:55 PM PST 24
Finished	Feb 07 01:34:59 PM PST 24
Peak memory	201680 kb
Host	smart-3e664c96-8e4e-42ff-82cc-52fd39603032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499398851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3499398851
Directory	/workspace/48.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_interrupt.2873684676
Short name	T189
Test name
Test status
Simulation time	329510999315 ps
CPU time	236.02 seconds
Started	Feb 07 01:29:56 PM PST 24
Finished	Feb 07 01:33:52 PM PST 24
Peak memory	201616 kb
Host	smart-d45d7b61-a8d4-4fb5-a899-f8e5ffe41995
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873684676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2873684676
Directory	/workspace/48.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1861050001
Short name	T630
Test name
Test status
Simulation time	167483002745 ps
CPU time	101.95 seconds
Started	Feb 07 01:29:55 PM PST 24
Finished	Feb 07 01:31:38 PM PST 24
Peak memory	201620 kb
Host	smart-4ab1d3d7-76db-4665-a795-836e12286ea2
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861050001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru pt_fixed.1861050001
Directory	/workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_polled.3832463121
Short name	T467
Test name
Test status
Simulation time	168654399570 ps
CPU time	399.66 seconds
Started	Feb 07 01:29:54 PM PST 24
Finished	Feb 07 01:36:34 PM PST 24
Peak memory	201572 kb
Host	smart-88a15847-fb6f-4bbd-aab0-262e4c0b2ce0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832463121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3832463121
Directory	/workspace/48.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2731270965
Short name	T434
Test name
Test status
Simulation time	164960076226 ps
CPU time	101.22 seconds
Started	Feb 07 01:29:54 PM PST 24
Finished	Feb 07 01:31:36 PM PST 24
Peak memory	201520 kb
Host	smart-445d2aa4-87cc-466e-bdf0-5e9233202dda
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731270965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix ed.2731270965
Directory	/workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_wakeup.2896142272
Short name	T129
Test name
Test status
Simulation time	327399076553 ps
CPU time	169.76 seconds
Started	Feb 07 01:29:57 PM PST 24
Finished	Feb 07 01:32:47 PM PST 24
Peak memory	201632 kb
Host	smart-27b5e9a0-3eca-40e9-b201-09d773d60cea
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896142272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters _wakeup.2896142272
Directory	/workspace/48.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1266351582
Short name	T140
Test name
Test status
Simulation time	490305110042 ps
CPU time	292.76 seconds
Started	Feb 07 01:29:54 PM PST 24
Finished	Feb 07 01:34:48 PM PST 24
Peak memory	201604 kb
Host	smart-b0942a39-472a-40fa-8053-5800aa414855
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266351582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .adc_ctrl_filters_wakeup_fixed.1266351582
Directory	/workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_fsm_reset.2279149559
Short name	T186
Test name
Test status
Simulation time	98752000306 ps
CPU time	530.39 seconds
Started	Feb 07 01:30:00 PM PST 24
Finished	Feb 07 01:38:51 PM PST 24
Peak memory	201864 kb
Host	smart-8e08f00d-5f1c-4c5d-9cd6-c39fb5b42ae3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279149559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2279149559
Directory	/workspace/48.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/48.adc_ctrl_lowpower_counter.854189249
Short name	T520
Test name
Test status
Simulation time	45921968784 ps
CPU time	101.19 seconds
Started	Feb 07 01:29:54 PM PST 24
Finished	Feb 07 01:31:36 PM PST 24
Peak memory	201340 kb
Host	smart-d90d1e46-27f4-4471-9aad-f1c15ac3547b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854189249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.854189249
Directory	/workspace/48.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/48.adc_ctrl_poweron_counter.24062500
Short name	T599
Test name
Test status
Simulation time	4452362276 ps
CPU time	3.37 seconds
Started	Feb 07 01:29:55 PM PST 24
Finished	Feb 07 01:29:59 PM PST 24
Peak memory	201368 kb
Host	smart-8399b803-0fa7-40ff-8b52-50b2b5aa6e41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24062500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.24062500
Directory	/workspace/48.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/48.adc_ctrl_smoke.2946058991
Short name	T863
Test name
Test status
Simulation time	6017118635 ps
CPU time	12.17 seconds
Started	Feb 07 01:29:55 PM PST 24
Finished	Feb 07 01:30:08 PM PST 24
Peak memory	201380 kb
Host	smart-3ed02ae5-bf45-45cf-91c0-650b43b69260
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2946058991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2946058991
Directory	/workspace/48.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.adc_ctrl_stress_all.3472763831
Short name	T178
Test name
Test status
Simulation time	118822222070 ps
CPU time	446.11 seconds
Started	Feb 07 01:30:02 PM PST 24
Finished	Feb 07 01:37:29 PM PST 24
Peak memory	201808 kb
Host	smart-48295163-bdba-4322-bf20-580783914e26
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472763831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all .3472763831
Directory	/workspace/48.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.adc_ctrl_alert_test.2143790490
Short name	T707
Test name
Test status
Simulation time	564275040 ps
CPU time	0.69 seconds
Started	Feb 07 01:30:14 PM PST 24
Finished	Feb 07 01:30:17 PM PST 24
Peak memory	201224 kb
Host	smart-f8ec76ad-b569-41df-9353-f56e69751fd7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143790490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2143790490
Directory	/workspace/49.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.adc_ctrl_clock_gating.4066664933
Short name	T17
Test name
Test status
Simulation time	334810138470 ps
CPU time	229.17 seconds
Started	Feb 07 01:30:03 PM PST 24
Finished	Feb 07 01:33:53 PM PST 24
Peak memory	201532 kb
Host	smart-d9cbbd2d-7510-4dc0-b7c3-a8fc8a0a36fe
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066664933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat ing.4066664933
Directory	/workspace/49.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_both.1673448274
Short name	T194
Test name
Test status
Simulation time	319035116141 ps
CPU time	360.76 seconds
Started	Feb 07 01:30:03 PM PST 24
Finished	Feb 07 01:36:05 PM PST 24
Peak memory	201508 kb
Host	smart-0daecb24-b663-4729-9f9d-e8007fb8a873
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673448274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1673448274
Directory	/workspace/49.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_interrupt.1008596754
Short name	T696
Test name
Test status
Simulation time	490298464304 ps
CPU time	310.77 seconds
Started	Feb 07 01:30:04 PM PST 24
Finished	Feb 07 01:35:15 PM PST 24
Peak memory	201444 kb
Host	smart-5dc5f71a-fade-4ba7-86c1-b43bc8a8d8bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008596754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1008596754
Directory	/workspace/49.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.11284728
Short name	T725
Test name
Test status
Simulation time	484732105322 ps
CPU time	294.98 seconds
Started	Feb 07 01:30:00 PM PST 24
Finished	Feb 07 01:34:56 PM PST 24
Peak memory	201588 kb
Host	smart-f6c4cc1d-9986-482f-9fe1-a8b141e6bd33
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=11284728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt _fixed.11284728
Directory	/workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_polled.1154026497
Short name	T272
Test name
Test status
Simulation time	171927439483 ps
CPU time	113.23 seconds
Started	Feb 07 01:30:02 PM PST 24
Finished	Feb 07 01:31:57 PM PST 24
Peak memory	201500 kb
Host	smart-4aa661d8-1606-4625-9b3b-443a1ae72b0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154026497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1154026497
Directory	/workspace/49.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1031988492
Short name	T634
Test name
Test status
Simulation time	328592220026 ps
CPU time	774.45 seconds
Started	Feb 07 01:30:00 PM PST 24
Finished	Feb 07 01:42:55 PM PST 24
Peak memory	201484 kb
Host	smart-8bb4223a-23fd-4272-9de6-e1170c262760
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031988492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix ed.1031988492
Directory	/workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1001949690
Short name	T53
Test name
Test status
Simulation time	492627016906 ps
CPU time	118.28 seconds
Started	Feb 07 01:30:01 PM PST 24
Finished	Feb 07 01:32:00 PM PST 24
Peak memory	201700 kb
Host	smart-3ae3c82c-2790-475f-b855-f8fc9fb9c41f
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001949690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .adc_ctrl_filters_wakeup_fixed.1001949690
Directory	/workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_fsm_reset.2955281832
Short name	T543
Test name
Test status
Simulation time	91377573751 ps
CPU time	380.51 seconds
Started	Feb 07 01:30:12 PM PST 24
Finished	Feb 07 01:36:34 PM PST 24
Peak memory	201880 kb
Host	smart-5d948628-90f3-4442-8b25-4554cc5069ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955281832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2955281832
Directory	/workspace/49.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/49.adc_ctrl_lowpower_counter.1463274085
Short name	T440
Test name
Test status
Simulation time	44123756902 ps
CPU time	24.08 seconds
Started	Feb 07 01:30:16 PM PST 24
Finished	Feb 07 01:30:48 PM PST 24
Peak memory	201384 kb
Host	smart-d0eb731e-204e-41a2-9b6e-3faf951ce936
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463274085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1463274085
Directory	/workspace/49.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/49.adc_ctrl_poweron_counter.809090061
Short name	T562
Test name
Test status
Simulation time	4092468174 ps
CPU time	2.41 seconds
Started	Feb 07 01:30:12 PM PST 24
Finished	Feb 07 01:30:16 PM PST 24
Peak memory	201392 kb
Host	smart-6cecd31a-107d-443a-aee0-ec5bf69c5690
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809090061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.809090061
Directory	/workspace/49.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/49.adc_ctrl_smoke.4262724154
Short name	T80
Test name
Test status
Simulation time	5723809355 ps
CPU time	11.13 seconds
Started	Feb 07 01:30:01 PM PST 24
Finished	Feb 07 01:30:12 PM PST 24
Peak memory	201316 kb
Host	smart-bcbba8fe-9bc2-4f3a-b35a-dce1ac49c180
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262724154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4262724154
Directory	/workspace/49.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.adc_ctrl_stress_all.2275072103
Short name	T235
Test name
Test status
Simulation time	503575090138 ps
CPU time	196.78 seconds
Started	Feb 07 01:30:12 PM PST 24
Finished	Feb 07 01:33:30 PM PST 24
Peak memory	201632 kb
Host	smart-a383ae72-7633-4926-a939-0561fffcfbd4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275072103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all .2275072103
Directory	/workspace/49.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2391712332
Short name	T726
Test name
Test status
Simulation time	216987063707 ps
CPU time	92.63 seconds
Started	Feb 07 01:30:16 PM PST 24
Finished	Feb 07 01:31:56 PM PST 24
Peak memory	210268 kb
Host	smart-15dbea8d-ff9a-4b64-8e0e-9565f3f9b4c4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391712332 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2391712332
Directory	/workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.adc_ctrl_alert_test.3579144988
Short name	T38
Test name
Test status
Simulation time	320309709 ps
CPU time	1.37 seconds
Started	Feb 07 01:20:06 PM PST 24
Finished	Feb 07 01:20:08 PM PST 24
Peak memory	201204 kb
Host	smart-4c66d9d1-70f7-413a-b972-237e717bc180
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579144988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3579144988
Directory	/workspace/5.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.adc_ctrl_clock_gating.3245569809
Short name	T106
Test name
Test status
Simulation time	567809139635 ps
CPU time	707.26 seconds
Started	Feb 07 01:20:00 PM PST 24
Finished	Feb 07 01:31:49 PM PST 24
Peak memory	201552 kb
Host	smart-686c6a3c-5f85-43b5-af64-14a27f1d0b15
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245569809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati ng.3245569809
Directory	/workspace/5.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_interrupt.2150284832
Short name	T256
Test name
Test status
Simulation time	329202580254 ps
CPU time	734.35 seconds
Started	Feb 07 01:19:59 PM PST 24
Finished	Feb 07 01:32:14 PM PST 24
Peak memory	201588 kb
Host	smart-89d801c5-33bb-4866-b56d-2e2b944397eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2150284832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2150284832
Directory	/workspace/5.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2978847252
Short name	T740
Test name
Test status
Simulation time	163607522829 ps
CPU time	70.72 seconds
Started	Feb 07 01:20:05 PM PST 24
Finished	Feb 07 01:21:17 PM PST 24
Peak memory	201564 kb
Host	smart-26427754-b150-437e-bd82-eb8b50ff58ae
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978847252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup t_fixed.2978847252
Directory	/workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_polled.330346985
Short name	T125
Test name
Test status
Simulation time	328733605918 ps
CPU time	202.78 seconds
Started	Feb 07 01:19:55 PM PST 24
Finished	Feb 07 01:23:18 PM PST 24
Peak memory	201644 kb
Host	smart-8c4ed1cb-6463-44fc-a0c5-e25dabec834d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330346985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.330346985
Directory	/workspace/5.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.960937354
Short name	T652
Test name
Test status
Simulation time	167673068221 ps
CPU time	100.37 seconds
Started	Feb 07 01:19:58 PM PST 24
Finished	Feb 07 01:21:39 PM PST 24
Peak memory	201556 kb
Host	smart-0ca716dc-9e71-4176-8545-c158c69a83e4
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=960937354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed .960937354
Directory	/workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_wakeup.349199130
Short name	T768
Test name
Test status
Simulation time	364171110724 ps
CPU time	219.96 seconds
Started	Feb 07 01:19:56 PM PST 24
Finished	Feb 07 01:23:37 PM PST 24
Peak memory	201548 kb
Host	smart-1a34fd62-bcce-45ba-9590-414c8913dffa
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349199130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w akeup.349199130
Directory	/workspace/5.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3269937050
Short name	T738
Test name
Test status
Simulation time	160470360818 ps
CPU time	243.31 seconds
Started	Feb 07 01:20:01 PM PST 24
Finished	Feb 07 01:24:06 PM PST 24
Peak memory	201616 kb
Host	smart-2bc37229-22bc-4b85-8919-f79b61410243
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269937050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. adc_ctrl_filters_wakeup_fixed.3269937050
Directory	/workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_fsm_reset.1287882081
Short name	T172
Test name
Test status
Simulation time	130691450725 ps
CPU time	447.46 seconds
Started	Feb 07 01:19:58 PM PST 24
Finished	Feb 07 01:27:27 PM PST 24
Peak memory	202000 kb
Host	smart-8270ba0f-3969-4e49-be9f-3eb68d76ee27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287882081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1287882081
Directory	/workspace/5.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/5.adc_ctrl_lowpower_counter.4004458334
Short name	T674
Test name
Test status
Simulation time	38982474018 ps
CPU time	81.31 seconds
Started	Feb 07 01:19:55 PM PST 24
Finished	Feb 07 01:21:17 PM PST 24
Peak memory	201396 kb
Host	smart-abc19257-223b-49eb-bf88-a37c420e9ac5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004458334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.4004458334
Directory	/workspace/5.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/5.adc_ctrl_poweron_counter.3255037997
Short name	T424
Test name
Test status
Simulation time	5607830764 ps
CPU time	4.42 seconds
Started	Feb 07 01:20:01 PM PST 24
Finished	Feb 07 01:20:07 PM PST 24
Peak memory	201372 kb
Host	smart-80beb7bf-98a6-4a8b-ab4c-c9828d41acf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255037997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3255037997
Directory	/workspace/5.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/5.adc_ctrl_smoke.3646432620
Short name	T539
Test name
Test status
Simulation time	5979259546 ps
CPU time	1.78 seconds
Started	Feb 07 01:19:29 PM PST 24
Finished	Feb 07 01:19:33 PM PST 24
Peak memory	201372 kb
Host	smart-37831433-66df-4305-86d0-32db5cef5f68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646432620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3646432620
Directory	/workspace/5.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.adc_ctrl_stress_all.1740823916
Short name	T169
Test name
Test status
Simulation time	73127867702 ps
CPU time	268.16 seconds
Started	Feb 07 01:19:56 PM PST 24
Finished	Feb 07 01:24:25 PM PST 24
Peak memory	201856 kb
Host	smart-75ce9ebc-f83e-46a5-a18e-8b3fd0226958
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740823916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all. 1740823916
Directory	/workspace/5.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2390096401
Short name	T564
Test name
Test status
Simulation time	64371900547 ps
CPU time	140.75 seconds
Started	Feb 07 01:19:59 PM PST 24
Finished	Feb 07 01:22:20 PM PST 24
Peak memory	210260 kb
Host	smart-2d9f4d26-6f1d-4fc8-9f81-5c00adf51b01
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390096401 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2390096401
Directory	/workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.adc_ctrl_alert_test.3818486667
Short name	T572
Test name
Test status
Simulation time	427996878 ps
CPU time	1.04 seconds
Started	Feb 07 01:20:07 PM PST 24
Finished	Feb 07 01:20:09 PM PST 24
Peak memory	201216 kb
Host	smart-5e7c2672-a5d3-46de-a8a7-3f49c52bd22c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818486667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3818486667
Directory	/workspace/6.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.adc_ctrl_clock_gating.2775253931
Short name	T518
Test name
Test status
Simulation time	324152408460 ps
CPU time	347.74 seconds
Started	Feb 07 01:20:07 PM PST 24
Finished	Feb 07 01:25:56 PM PST 24
Peak memory	201508 kb
Host	smart-f2412631-71b2-407d-85ac-2668129432bb
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775253931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati ng.2775253931
Directory	/workspace/6.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_both.1999682006
Short name	T222
Test name
Test status
Simulation time	322427106695 ps
CPU time	736.17 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:32:21 PM PST 24
Peak memory	201656 kb
Host	smart-5bafed4d-f761-4b5d-8e7a-73b7a440f2e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999682006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1999682006
Directory	/workspace/6.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_interrupt.725078893
Short name	T862
Test name
Test status
Simulation time	479457125127 ps
CPU time	313.29 seconds
Started	Feb 07 01:19:58 PM PST 24
Finished	Feb 07 01:25:12 PM PST 24
Peak memory	201628 kb
Host	smart-e9bd1159-4633-47ec-99ea-7fe86d059067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725078893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.725078893
Directory	/workspace/6.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.334408325
Short name	T853
Test name
Test status
Simulation time	166484541334 ps
CPU time	203.5 seconds
Started	Feb 07 01:20:03 PM PST 24
Finished	Feb 07 01:23:28 PM PST 24
Peak memory	201556 kb
Host	smart-3567db76-221c-48e2-8303-9df1d55a9030
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=334408325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt _fixed.334408325
Directory	/workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_polled.2460935600
Short name	T730
Test name
Test status
Simulation time	156596717514 ps
CPU time	91.34 seconds
Started	Feb 07 01:19:58 PM PST 24
Finished	Feb 07 01:21:30 PM PST 24
Peak memory	201552 kb
Host	smart-16fe1986-c80f-441a-a31a-f281cb7092d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460935600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2460935600
Directory	/workspace/6.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1776820415
Short name	T598
Test name
Test status
Simulation time	159509249552 ps
CPU time	72.48 seconds
Started	Feb 07 01:19:55 PM PST 24
Finished	Feb 07 01:21:08 PM PST 24
Peak memory	201580 kb
Host	smart-d3234d92-bf3a-4adc-b68b-65b799791974
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776820415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe d.1776820415
Directory	/workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_wakeup.889753136
Short name	T227
Test name
Test status
Simulation time	490567173675 ps
CPU time	187.83 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:23:14 PM PST 24
Peak memory	201536 kb
Host	smart-99bdeabb-914e-4e4a-ab6e-f55b4f1719de
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889753136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w akeup.889753136
Directory	/workspace/6.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1708494852
Short name	T547
Test name
Test status
Simulation time	328196204364 ps
CPU time	178.08 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:23:04 PM PST 24
Peak memory	201576 kb
Host	smart-06b34fd0-3068-4224-adc8-17cda1b80aac
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708494852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. adc_ctrl_filters_wakeup_fixed.1708494852
Directory	/workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_fsm_reset.1246094107
Short name	T494
Test name
Test status
Simulation time	97631110636 ps
CPU time	479.62 seconds
Started	Feb 07 01:20:03 PM PST 24
Finished	Feb 07 01:28:05 PM PST 24
Peak memory	201776 kb
Host	smart-c44bfefd-1388-41c4-99f9-d96981f3f67c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246094107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1246094107
Directory	/workspace/6.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/6.adc_ctrl_lowpower_counter.2205891653
Short name	T813
Test name
Test status
Simulation time	33955616733 ps
CPU time	44.27 seconds
Started	Feb 07 01:20:06 PM PST 24
Finished	Feb 07 01:20:51 PM PST 24
Peak memory	201356 kb
Host	smart-ccbde91f-47f8-448d-99f5-c426f7f62532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205891653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2205891653
Directory	/workspace/6.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/6.adc_ctrl_poweron_counter.39857687
Short name	T396
Test name
Test status
Simulation time	5377290442 ps
CPU time	2.67 seconds
Started	Feb 07 01:20:02 PM PST 24
Finished	Feb 07 01:20:06 PM PST 24
Peak memory	201344 kb
Host	smart-c345b4f2-fe6b-426f-a1ec-30a5e81a3012
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39857687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.39857687
Directory	/workspace/6.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/6.adc_ctrl_smoke.3545150061
Short name	T533
Test name
Test status
Simulation time	5952284319 ps
CPU time	2.57 seconds
Started	Feb 07 01:19:59 PM PST 24
Finished	Feb 07 01:20:03 PM PST 24
Peak memory	201304 kb
Host	smart-bfa9462b-e616-43d1-98a3-761e9f298065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545150061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3545150061
Directory	/workspace/6.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.adc_ctrl_stress_all.111913098
Short name	T168
Test name
Test status
Simulation time	327858589828 ps
CPU time	669.71 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:31:15 PM PST 24
Peak memory	201912 kb
Host	smart-05e470d3-d8a6-4dec-906c-3203bde058e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111913098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.111913098
Directory	/workspace/6.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3536563870
Short name	T229
Test name
Test status
Simulation time	664602912279 ps
CPU time	119.67 seconds
Started	Feb 07 01:20:01 PM PST 24
Finished	Feb 07 01:22:03 PM PST 24
Peak memory	216884 kb
Host	smart-5091e122-ac42-4713-9aab-0541e3617bbb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536563870 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3536563870
Directory	/workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.adc_ctrl_alert_test.1387799560
Short name	T592
Test name
Test status
Simulation time	551304624 ps
CPU time	0.79 seconds
Started	Feb 07 01:20:05 PM PST 24
Finished	Feb 07 01:20:07 PM PST 24
Peak memory	201240 kb
Host	smart-9694ae56-143d-4075-b7e1-9db35cc22162
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387799560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1387799560
Directory	/workspace/7.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.adc_ctrl_clock_gating.344243542
Short name	T299
Test name
Test status
Simulation time	323488258611 ps
CPU time	713.08 seconds
Started	Feb 07 01:20:02 PM PST 24
Finished	Feb 07 01:31:57 PM PST 24
Peak memory	201568 kb
Host	smart-a28a89e0-977a-4600-909c-be21a1918234
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344243542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin g.344243542
Directory	/workspace/7.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_interrupt.1886482598
Short name	T230
Test name
Test status
Simulation time	159697453639 ps
CPU time	77.4 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:21:23 PM PST 24
Peak memory	201588 kb
Host	smart-b77b8dbc-820b-4c82-89a6-7b56d882ad28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886482598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1886482598
Directory	/workspace/7.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3042932412
Short name	T451
Test name
Test status
Simulation time	164989477086 ps
CPU time	27.2 seconds
Started	Feb 07 01:20:05 PM PST 24
Finished	Feb 07 01:20:33 PM PST 24
Peak memory	201528 kb
Host	smart-20889a87-6014-4203-941e-07af8daaeb0e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042932412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup t_fixed.3042932412
Directory	/workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_polled.2393390228
Short name	T98
Test name
Test status
Simulation time	328096798821 ps
CPU time	223.61 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:23:49 PM PST 24
Peak memory	201060 kb
Host	smart-10dae9c3-b21e-4d55-87f0-7b550a07faf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393390228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2393390228
Directory	/workspace/7.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.955790240
Short name	T703
Test name
Test status
Simulation time	332900738297 ps
CPU time	156.19 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:22:41 PM PST 24
Peak memory	201024 kb
Host	smart-e92e314c-dfe6-4436-bdde-54755f33420c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=955790240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed .955790240
Directory	/workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_wakeup.2684340520
Short name	T243
Test name
Test status
Simulation time	167017335845 ps
CPU time	74.35 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:21:20 PM PST 24
Peak memory	201564 kb
Host	smart-77b59413-780d-4e98-9cad-2ef2f3a10607
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684340520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_ wakeup.2684340520
Directory	/workspace/7.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3383210953
Short name	T761
Test name
Test status
Simulation time	164033012049 ps
CPU time	190.7 seconds
Started	Feb 07 01:20:07 PM PST 24
Finished	Feb 07 01:23:19 PM PST 24
Peak memory	201536 kb
Host	smart-8ccdfe61-5b0d-41da-a14c-a7d9b2e1305b
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383210953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. adc_ctrl_filters_wakeup_fixed.3383210953
Directory	/workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_fsm_reset.357301744
Short name	T622
Test name
Test status
Simulation time	80246461853 ps
CPU time	313.01 seconds
Started	Feb 07 01:20:06 PM PST 24
Finished	Feb 07 01:25:20 PM PST 24
Peak memory	201832 kb
Host	smart-c4af3941-80a4-4eda-b332-08cbaeff9e3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357301744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.357301744
Directory	/workspace/7.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/7.adc_ctrl_lowpower_counter.2489682348
Short name	T604
Test name
Test status
Simulation time	33879941367 ps
CPU time	39.39 seconds
Started	Feb 07 01:20:04 PM PST 24
Finished	Feb 07 01:20:45 PM PST 24
Peak memory	201432 kb
Host	smart-0e3950c0-bf5f-40cc-bbe1-562bc922bcd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489682348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2489682348
Directory	/workspace/7.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/7.adc_ctrl_poweron_counter.366190557
Short name	T390
Test name
Test status
Simulation time	3145633401 ps
CPU time	4.13 seconds
Started	Feb 07 01:20:02 PM PST 24
Finished	Feb 07 01:20:08 PM PST 24
Peak memory	201384 kb
Host	smart-87881978-494c-418d-8343-463e3ccec723
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366190557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.366190557
Directory	/workspace/7.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/7.adc_ctrl_smoke.1996886096
Short name	T553
Test name
Test status
Simulation time	5660113046 ps
CPU time	13.38 seconds
Started	Feb 07 01:20:03 PM PST 24
Finished	Feb 07 01:20:19 PM PST 24
Peak memory	201428 kb
Host	smart-76fe7622-a0cc-4b46-9489-9ebdd604df62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1996886096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1996886096
Directory	/workspace/7.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.adc_ctrl_stress_all.259626
Short name	T632
Test name
Test status
Simulation time	337014310204 ps
CPU time	794.85 seconds
Started	Feb 07 01:20:05 PM PST 24
Finished	Feb 07 01:33:21 PM PST 24
Peak memory	201640 kb
Host	smart-7b5d25f1-3261-4712-839e-0bf59ad3a72e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.259626
Directory	/workspace/7.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.88626668
Short name	T292
Test name
Test status
Simulation time	377430889482 ps
CPU time	200.44 seconds
Started	Feb 07 01:20:05 PM PST 24
Finished	Feb 07 01:23:26 PM PST 24
Peak memory	210276 kb
Host	smart-85b117d2-2b7f-4b77-a443-6089b5739973
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88626668 -assert nopos tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.88626668
Directory	/workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.adc_ctrl_alert_test.1593172006
Short name	T685
Test name
Test status
Simulation time	515734001 ps
CPU time	1.72 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:20:19 PM PST 24
Peak memory	201232 kb
Host	smart-007a63f6-38bf-4959-b863-3950c588e0ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593172006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1593172006
Directory	/workspace/8.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_interrupt.2240568800
Short name	T701
Test name
Test status
Simulation time	164272479036 ps
CPU time	203.8 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:23:42 PM PST 24
Peak memory	201536 kb
Host	smart-449efc73-aa2a-4755-9803-a548186e681a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240568800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2240568800
Directory	/workspace/8.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4171479465
Short name	T834
Test name
Test status
Simulation time	160823589429 ps
CPU time	335.34 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:25:54 PM PST 24
Peak memory	201688 kb
Host	smart-2fcd4296-aeb5-429c-a1c3-a87ac17a5c80
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171479465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup t_fixed.4171479465
Directory	/workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_polled.2301214101
Short name	T144
Test name
Test status
Simulation time	331860548331 ps
CPU time	66.7 seconds
Started	Feb 07 01:20:06 PM PST 24
Finished	Feb 07 01:21:13 PM PST 24
Peak memory	201532 kb
Host	smart-b925281c-d7bf-43a8-8798-9254034c021c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2301214101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2301214101
Directory	/workspace/8.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1152445873
Short name	T403
Test name
Test status
Simulation time	484271185732 ps
CPU time	513.14 seconds
Started	Feb 07 01:20:20 PM PST 24
Finished	Feb 07 01:28:54 PM PST 24
Peak memory	201564 kb
Host	smart-d7887341-cf14-4ca7-bde8-bf3f6bc095a3
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152445873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe d.1152445873
Directory	/workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_wakeup.980571650
Short name	T192
Test name
Test status
Simulation time	349605661178 ps
CPU time	840.98 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:34:19 PM PST 24
Peak memory	201488 kb
Host	smart-5bc173b3-4e1f-486d-8d2d-bf19036b7cc8
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980571650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w akeup.980571650
Directory	/workspace/8.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3571063448
Short name	T102
Test name
Test status
Simulation time	160815688501 ps
CPU time	396.78 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:26:55 PM PST 24
Peak memory	201528 kb
Host	smart-d0271fa4-3b3a-47d8-bc98-026c7550ed82
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571063448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. adc_ctrl_filters_wakeup_fixed.3571063448
Directory	/workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_fsm_reset.3467645122
Short name	T442
Test name
Test status
Simulation time	71097305906 ps
CPU time	308.89 seconds
Started	Feb 07 01:20:20 PM PST 24
Finished	Feb 07 01:25:29 PM PST 24
Peak memory	201880 kb
Host	smart-cdff08f2-022f-486d-8c70-2e5c84d2deae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467645122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3467645122
Directory	/workspace/8.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/8.adc_ctrl_lowpower_counter.2805130008
Short name	T638
Test name
Test status
Simulation time	43907793317 ps
CPU time	49.05 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:21:07 PM PST 24
Peak memory	201284 kb
Host	smart-48cc83ab-d7b6-4c21-aea4-b89ef17875b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805130008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2805130008
Directory	/workspace/8.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/8.adc_ctrl_poweron_counter.483482295
Short name	T601
Test name
Test status
Simulation time	4089754732 ps
CPU time	10.34 seconds
Started	Feb 07 01:20:23 PM PST 24
Finished	Feb 07 01:20:34 PM PST 24
Peak memory	201380 kb
Host	smart-d6a78007-1615-492f-abce-91c6789a4926
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=483482295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.483482295
Directory	/workspace/8.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/8.adc_ctrl_smoke.1232363548
Short name	T739
Test name
Test status
Simulation time	5890814440 ps
CPU time	4.25 seconds
Started	Feb 07 01:20:03 PM PST 24
Finished	Feb 07 01:20:10 PM PST 24
Peak memory	201376 kb
Host	smart-336fb758-9b41-4c73-b47b-efb16de503d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232363548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1232363548
Directory	/workspace/8.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.adc_ctrl_stress_all.2347199336
Short name	T479
Test name
Test status
Simulation time	35082940025 ps
CPU time	5.18 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:20:22 PM PST 24
Peak memory	201372 kb
Host	smart-6e75eb06-ebb5-472a-bc4c-7fc7c35094e9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347199336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all. 2347199336
Directory	/workspace/8.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.838471486
Short name	T731
Test name
Test status
Simulation time	62645286895 ps
CPU time	149.82 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:22:48 PM PST 24
Peak memory	201832 kb
Host	smart-b9b161b5-6709-45ea-b644-214111f72a0e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838471486 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.838471486
Directory	/workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.adc_ctrl_alert_test.4130284965
Short name	T812
Test name
Test status
Simulation time	312094722 ps
CPU time	1.34 seconds
Started	Feb 07 01:20:18 PM PST 24
Finished	Feb 07 01:20:21 PM PST 24
Peak memory	201280 kb
Host	smart-dd7b34f7-b538-4e17-91e9-05915c97db4b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130284965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.4130284965
Directory	/workspace/9.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.adc_ctrl_clock_gating.407896496
Short name	T470
Test name
Test status
Simulation time	160293489854 ps
CPU time	94.45 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:21:52 PM PST 24
Peak memory	201660 kb
Host	smart-9f46f588-c88a-450b-8eaf-a9d8d27ebd30
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407896496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin g.407896496
Directory	/workspace/9.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_interrupt.3610728062
Short name	T820
Test name
Test status
Simulation time	324182749608 ps
CPU time	198.6 seconds
Started	Feb 07 01:20:18 PM PST 24
Finished	Feb 07 01:23:37 PM PST 24
Peak memory	201708 kb
Host	smart-b7a3d326-1f01-4722-81d6-e4bdcc83526c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610728062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3610728062
Directory	/workspace/9.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1593311367
Short name	T611
Test name
Test status
Simulation time	327759288990 ps
CPU time	202.18 seconds
Started	Feb 07 01:20:22 PM PST 24
Finished	Feb 07 01:23:45 PM PST 24
Peak memory	201544 kb
Host	smart-66500f53-1f3e-4775-9508-471b2fbe5f4c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593311367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup t_fixed.1593311367
Directory	/workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_polled.1082164129
Short name	T644
Test name
Test status
Simulation time	329211153593 ps
CPU time	88.45 seconds
Started	Feb 07 01:20:18 PM PST 24
Finished	Feb 07 01:21:47 PM PST 24
Peak memory	201704 kb
Host	smart-c36a3fab-db85-4515-8f4c-be4844a5cb61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082164129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1082164129
Directory	/workspace/9.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4227196122
Short name	T402
Test name
Test status
Simulation time	164656548826 ps
CPU time	389.08 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:26:47 PM PST 24
Peak memory	201612 kb
Host	smart-cd8bcff7-fee2-4e00-88c8-2f5065f5e33f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227196122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe d.4227196122
Directory	/workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.105202658
Short name	T735
Test name
Test status
Simulation time	167131543627 ps
CPU time	203.82 seconds
Started	Feb 07 01:20:22 PM PST 24
Finished	Feb 07 01:23:46 PM PST 24
Peak memory	201536 kb
Host	smart-51e43890-4e46-4b63-afc7-47e48bf6f774
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105202658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a dc_ctrl_filters_wakeup_fixed.105202658
Directory	/workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_fsm_reset.4032943453
Short name	T486
Test name
Test status
Simulation time	76601757604 ps
CPU time	447.33 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:27:46 PM PST 24
Peak memory	202000 kb
Host	smart-d6bbcb26-0fa3-4a28-803c-b500c358c983
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032943453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4032943453
Directory	/workspace/9.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/9.adc_ctrl_lowpower_counter.331640614
Short name	T508
Test name
Test status
Simulation time	23669612431 ps
CPU time	26.6 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:20:44 PM PST 24
Peak memory	201380 kb
Host	smart-52a96a1e-91b3-497f-ae88-f22127f45e92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331640614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.331640614
Directory	/workspace/9.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/9.adc_ctrl_poweron_counter.1107171806
Short name	T844
Test name
Test status
Simulation time	4193745172 ps
CPU time	9.59 seconds
Started	Feb 07 01:20:17 PM PST 24
Finished	Feb 07 01:20:27 PM PST 24
Peak memory	201408 kb
Host	smart-8d35cf64-219b-4118-a0bc-fb5256fde04e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107171806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1107171806
Directory	/workspace/9.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/9.adc_ctrl_smoke.2117422050
Short name	T795
Test name
Test status
Simulation time	5968726041 ps
CPU time	14.39 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:20:32 PM PST 24
Peak memory	201320 kb
Host	smart-1a3ee321-4653-4a3d-a267-6da2f2d80b56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117422050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2117422050
Directory	/workspace/9.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.adc_ctrl_stress_all.2373311844
Short name	T689
Test name
Test status
Simulation time	504607084204 ps
CPU time	314.19 seconds
Started	Feb 07 01:20:16 PM PST 24
Finished	Feb 07 01:25:32 PM PST 24
Peak memory	201628 kb
Host	smart-739ea303-fa63-4bee-b630-514788072203
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373311844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all. 2373311844
Directory	/workspace/9.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.697577898
Short name	T526
Test name
Test status
Simulation time	26419040853 ps
CPU time	56.08 seconds
Started	Feb 07 01:20:20 PM PST 24
Finished	Feb 07 01:21:17 PM PST 24
Peak memory	209988 kb
Host	smart-8676de8d-9d7b-485a-9fbc-07204f10b507
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697577898 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.697577898
Directory	/workspace/9.adc_ctrl_stress_all_with_rand_reset/latest